JP2001159764A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent formation of a parasitic transistor between a source electrode and a drain electrode in a liquid crystal display device and to improve the yield without increasing the production cost. SOLUTION: The liquid crystal display device has a thin film transistor arranged at the intersection of a scanning signal line and a video signal line and having a gate electrode 1 connected to the scanning signal line, a source electrode 2 connected to the video signal line and a drain electrode 3 connected to a pixel electrode 9. A gate edge part is formed on the gate electrode, protruding in the longitudinal direction where the source electrode and drain electrode extend parallel, from between the source electrode and drain electrode to the pixel electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix type liquid crystal display device using thin film transistors.

[0002]

2. Description of the Related Art In recent years, active matrix type liquid crystal display devices using thin film transistors have been commercialized as liquid crystal display panels or liquid crystal display devices. For example, FIG. 4 is a plan view of a main part showing one pixel of a general liquid crystal display element of a liquid crystal display device and its periphery. In addition,
In this conventional example, an inverted staggered transistor in which an etching stopper is provided between a source electrode and a drain electrode is used as a thin film transistor.

[0003] 1 is a wiring extending from the scanning signal line,
It corresponds to the gate electrode of the transistor structure. The gate electrode 1 is made of a metal thin film and has a thickness that allows light to pass through. For example, the gate electrode 1 is made of an Al film and has a thickness of 150 n.
m. Reference numeral 2 denotes a wiring extending from the video signal line and corresponds to a source electrode of a transistor structure. Also,
3 corresponds to the drain electrode of the transistor structure. For example, the source electrode 2 and the drain electrode 3 have a thickness of 400 nm.
Of Al metal. Reference numeral 4 denotes an etching stopper for determining the performance of the transistor, which is made of, for example, a SiN film and has a thickness of 100 nm. Reference numeral 8 denotes a former gate capacitance pattern for providing a capacitance to the former gate of the gate electrode 1. The former gate capacitor 8 is made of an Al film similarly to the source electrode 2 and the drain electrode 3, and has a thickness of 400 nm. 9 is a pixel electrode, iT0
It is formed of a film. Reference numeral 11 denotes a gate edge portion, which is a portion where an a-Si film 6, which will be described later, may remain due to process formation.

FIG. 5 is a sectional view taken along the line AA 'in FIG. In FIG. 5, reference numeral 5 denotes a gate insulating film, which is made of, for example, a SiN film and has a thickness of 200 nm. Reference numeral 6 denotes a semiconductor layer made of an a-Si film,
m. 7 is an n + a-Si film having a thickness of 5
0 nm, which is provided for forming an ohmic contact between the a-Si film 6 and the source electrode 2 or between the a-Si film 6 and the drain electrode 3. 10 is a glass substrate. The gate insulating film 5, the a-Si film 6, and the etching stopper 4 are formed continuously by plasma CVD.

However, in the gate edge portion 11, a-Si
The film 6 is vertically deposited to a thickness of 100 to 250 nm. Then, after patterning the etching stopper 4, an n + a-Si film 7 is formed by plasma CVD. Again, at the gate edge 11, n + a-
The Si film 7 is deposited in a thickness of 100 to 250 nm in the vertical direction. (FIG. 6 shows a cutting line B at the gate edge portion.
FIG. 4 shows a cross-sectional view along the line −B ′. Then, the Al films of the source electrode 2 and the drain electrode 3 are formed. Thereafter, patterning of the source electrode 2 and the drain electrode 3 is performed to form a cross-sectional shape shown in FIG. The cross-sectional shape of the edge of the gate electrode 1 is formed at an angle of about 60 degrees, and the patterning etching method of the source electrode 2 and the drain electrode 3 is performed by overetching so that the a-Si film 6 does not remain at the gate edge portion 11. Going on condition.

[0006]

In the conventional method described above, if the semiconductor substrate area is small to some extent, the taper shape of the gate electrode 1 and the overetching condition of the patterning etching condition of the source electrode 2 and the drain electrode 3 are required. By preventing the a-Si film 6 from remaining on the gate edge portion 11, a transistor as designed is formed. However, if the area of the semiconductor substrate is increased and the processing accuracy in the cross-sectional direction is deteriorated, the a-Si film 6 remains at the gate edge portion 11 with a conventional planar pattern. Since a parasitic transistor is formed between the electrodes and a path of a parasitic current is formed, a transistor having electrical characteristics as designed cannot be formed.

In the future, even if the semiconductor substrate area does not increase, if the number of video signal lines to be formed per unit area increases or the unit area allocated to the video signal lines and the scanning signal lines decreases, The line width of the gate electrode 1 becomes small, and it becomes difficult to form a tapered shape.

Further, it is conceivable that the selection range of the patterning etching conditions for the source electrode 2 and the drain electrode 3 may be lost and the overetch condition may not be set.

Accordingly, the present invention solves the above-mentioned conventional problems and prevents a parasitic transistor from being formed between a source electrode and a drain electrode, thereby improving the yield without increasing the production cost. It is an object of the present invention to provide a liquid crystal display device.

[0010]

To achieve the above object, a liquid crystal display device according to the present invention comprises a plurality of scanning signal lines,
A video signal line provided to intersect with the scanning signal line; a pixel electrode disposed so as to be surrounded by the scanning signal line and the video signal line; and a pixel electrode disposed at an intersection of the scanning signal line and the video signal line. A liquid crystal display device comprising: a thin film transistor having a gate electrode connected to the scanning signal line, a source electrode connected to the video signal line, and a drain electrode connected to the pixel electrode. The electrode has a gate edge portion protruding toward the pixel electrode between the source electrode and the drain electrode in a longitudinal direction in which the source electrode and the drain electrode extend in parallel.

In the liquid crystal display device, it is preferable that the gate edge has a gate corner having an angle of at least 120 °.

According to the above configuration, the gate corner is formed at the gate edge at an angle with a plane pattern, so that the gate corner is formed on the a-Si.
By disconnecting the electrical connection of the film, a parasitic transistor is formed between the source electrode and the drain electrode to prevent a parasitic current from flowing, and the tapered shape of the gate electrode and the pattern of the source electrode and the drain electrode can be prevented. Even if there is no over-etching condition of the thinning etching condition, there is a variation in the process condition, and even if the semiconductor substrate becomes large, it is possible to form a thin film transistor having the designed electrical characteristics. As a result, it is possible to improve the yield without increasing the production cost.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of an essential part showing one pixel of a liquid crystal display device according to one embodiment of the present invention and its periphery, and FIG. 2 is a cross-sectional view taken along the line AA 'in FIG. FIG. 3 is a plan view in which the gate edge portion 11 of FIG. 1 is partially enlarged. In the description of the present embodiment,
As the thin film transistor, a transistor having an inverted staggered etching stopper structure is used.

In FIG. 1, reference numeral 1 denotes a gate electrode, which is a wiring extending from a scanning signal line. The gate electrode 1 is made of, for example, an Al film and has a thickness of 150 nm. Reference numeral 2 denotes a source electrode, which is a wiring extending from the video signal line. Reference numeral 3 denotes a drain electrode. For example, the source electrode 2 and the drain electrode 3 are formed of an Al metal having a thickness of 400 nm. Reference numeral 4 denotes an etching stopper pattern for determining the performance of the transistor, which is made of, for example, a SiN film and has a thickness of 100 nm. 8
Is a pre-stage gate capacitance pattern for providing capacitance to the pre-stage gate of the gate electrode 1. The former-stage gate capacitance pattern 8 has the same structure as the source electrode 2 and the drain electrode 3,
1 film having a thickness of 400 nm. Reference numeral 9 denotes a pixel electrode, which is formed of an iT0 film. 11 is
A gate edge protruding between the source electrode 2 and the drain electrode 3 toward the pixel electrode 9.
This is a portion where an a-Si film 6 described later can remain.

In FIG. 2, reference numeral 5 denotes a gate insulating film, which is made of a SiN film and has a thickness of 400 nm. 6
Is an a-Si film having a thickness of 50 nm. 7
Is an n + a-Si film having a thickness of 50 nm;
It is provided for forming an ohmic contact between the -Si film 6 and the source electrode 2 or between the a-Si film 6 and the drain electrode 3. Reference numeral 10 denotes a glass substrate.

Next, a process for forming each of the above films will be described.

First, Al is formed on the glass substrate 10 by sputtering, and the gate electrode 1 is processed by making use of a photolithography technique and an etching technique to taper the cross-sectional edge portion by 60 °. Next, the gate insulating film 5,
The a-Si film 6 and the etching stopper 4 are formed by continuous film formation in a plasma CVD vacuum apparatus. After that, patterning is performed only on the etching stopper 4 using the same photolithography method and etching method as described above. Thereafter, the oxide on the surface of the a-Si film 6 is removed, and the n + a-Si film 7 is
The film is formed in a D vacuum apparatus so that an ohmic contact with the a-Si film 6 can be formed. Finally, the Al thin films of the source electrode 2 and the drain electrode 3 are subjected to 40
A film is formed to a thickness of 0 nm, and a photolithography method and an etching method similar to the above are used.
The 1 metal and the n + a-Si film 7 are eroded, and other portions erode the Al metal and the n + a-Si film 7 and the a-Si film 6.

FIG. 3 is an enlarged view of the gate edge portion 11 of FIG. 1. As shown in FIG. 6, as a conventional technique, a-S is applied to the edge portion of the gate insulating film 5 above the gate taper portion.
This shows a state in which the i film 6 remains. Reference numeral 12 denotes a gate corner provided at the gate edge 11.
Reference numeral 13 denotes a residue of the a-Si film 6. Residual a-Si
The film 13 remains in the gate straight portion 14 of the gate edge portion 11, but the broken portion runs in the gate corner portion 12 and does not remain. As a result, a voltage difference occurs between the source electrode 2 and the drain electrode 3, and no current flows even if a voltage difference occurs at the gate edge portion 11. Therefore, a parasitic current of the transistor can be eliminated.

In this embodiment, the gate electrode 1
Was formed of an Al film, and the source electrode 2 and the drain electrode 3 were formed of an Al metal having a thickness of 400 nm. However, in the case of a thin film transistor structure, even if it was formed using an Al alloy or another low-resistance metal alloy, The same effect as the invention can be obtained.

In this embodiment, a thin film transistor having an inverted staggered etching stopper structure has been described. However, other structures, for example, a thin film transistor having a channel etching structure can provide the same effects as those of the present invention.

[0022]

As described above, according to the liquid crystal display device of the present invention, it is possible to prevent the occurrence of a parasitic transistor between the source electrode and the drain electrode, and to reduce the number of steps without increasing the number of steps. The yield can be improved without increasing the cost.

[Brief description of the drawings]

FIG. 1 is a main part plan view showing one pixel of a liquid crystal display element according to one embodiment of the present invention and the periphery thereof;

FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG. 1;

FIG. 3 is a partially enlarged plan view of a gate edge portion 11 of FIG. 1;

FIG. 4 is a main part plan view showing one pixel of a conventional liquid crystal display element and the periphery thereof;

FIG. 5 is a sectional view taken along the line A-A ′ of FIG. 4;

FIG. 6 is a sectional view taken along section line B-B ′ of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Source electrode 3 Drain electrode 4 Etching stopper 5 Gate insulating film 6 a-Si film 7 n + a-Si film 8 First stage gate capacitance 9 Pixel electrode 10 Glass substrate 11 Gate edge part 12 Gate corner part 13 Residual a-Si Membrane 14 Gate straight section

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yoneharu Takubo 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroshi Maeda 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. (reference) EA10 EB02 FA01 FB12 FB14 FB15 JA09

Claims (2)

[Claims] A plurality of scanning signal lines, a video signal line provided to intersect with the scanning signal line, a pixel electrode surrounded by the scanning signal line and the video signal line, A gate electrode connected to the scanning signal line, a source electrode connected to the video signal line, and a drain electrode connected to the pixel electrode; In a liquid crystal display device including a thin film transistor, the gate electrode protrudes toward the pixel electrode from between the source electrode and the drain electrode in a longitudinal direction in which the source electrode and the drain electrode extend in parallel. A liquid crystal display device having a gate edge portion. 2. The method according to claim 2, wherein the gate edge has at least 12
2. A gate corner portion having an angle of 0 °.
The liquid crystal display element as described in the above.