JPH09232585A - Electronic device with anodic oxide film, and etching of anodic oxide film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device having an anodic oxide film by conducting a small number of lithographic processes. SOLUTION: A Ta film 13, which has an etching selectivity ratio with an Al film 2, is formed on the Al film 12, and the film is patterned. A TaOx film 16 and an AIOX film 17 are formed by anodic oxidizing the laminated films. By having the above-mentioned structure, the etching selective ratio between the base layer Al film 12 and the Ta film above the film can be determined 12. As an anodic oxide film can be removed easily, the masking process using the resist of the Al film is unnecessitated, and the number of photolithographic process can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device having an anodic oxide film and a method for etching an anodic oxide film, and more specifically, to a thin film transistor (TFT: Th).
in Film Transistor) and MIM (Metal Insulator Meta)
l) A method for manufacturing an electronic device having a wiring structure having an anodic oxide film such as an element.

[0002]

2. Description of the Related Art An active matrix type LCD (AM-
Electronic devices such as TFTs and MIM elements have been put to practical use as switching elements of LCDs, so-called active elements. The TFT is suitable for the AM-LCD from the operating principle. Further, this TFT is an insulated gate field effect transistor, and a so-called bottom gate structure TFT composed of a gate, a gate insulating film, a semiconductor layer, a metal electrode and the like is used in many LCDs.
As the name implies, the MIM element is an element having a laminated structure of metal-insulator (film) -metal, and is formed of, for example, a material configuration of tantalum (Ta) -Ta oxide film-chromium (Cr). . As a method of manufacturing a TFT, there is generally known a method including a step of forming an anodic oxide film on the gate surface in order to improve the withstand voltage of the gate and prevent hillocks from being generated in the gate. .

FIG. 17 shows a TFT substrate in which TFTs and pixel electrodes are arranged in a matrix.
A liquid crystal cell can be prepared by making a T substrate and a common substrate (not shown) face each other, forming an alignment film on the facing inner surface of each substrate, and sealing the liquid crystal between both substrates. In the figure, reference numeral 1 is a glass substrate, on the surface of which pixel electrodes 2 are formed in a matrix, and each pixel electrode 2 is formed.
The TFT 3 is formed so as to be connected to. The drain electrodes of the TFTs 3 arranged in the column direction are connected to the drain line DL extending in the column direction. The gate electrodes of the TFTs 3 arranged in the row direction are connected to the gate line GL extending in the row direction. Each drain line DL extends toward one side edge of the glass substrate 1, and its end portion serves as a pad portion 4 used for mounting an IC or the like. In addition, each gate line GL
Also extends toward, for example, a side edge adjacent to the above-mentioned one side edge of the glass substrate 1, and an end portion thereof serves as a pad portion 5.

Conventionally, when the gate electrode, the gate line GL, and the pad portion 5 of such a TFT are formed, the procedure shown in FIGS. 18 (A) to 20 is performed.
In the figure, the left part shows the pad formation region and the right part shows the TFT formation region. First, FIG.
As shown in (A), the Al film 6 is deposited on the entire surface of the glass substrate 1 by the sputtering method. Next, a first photolithography step is performed to form a resist mask 7A for patterning the gate electrode in the TFT formation region and a lower layer pad portion in the pad portion formation region as shown in FIG. 18B. A resist mask 7B for patterning is formed. The gate line GL
A resist mask (not shown) is also formed on the part where
However, these resist masks for patterning the gate electrode, the gate line GL, and the pad portion 5 are formed as an integral resist pattern. Then, using this resist pattern as an etching mask, the underlying Al film 6 is wet-etched.
As a result, the gate electrode 6A as shown in FIG.
Lower layer pad portion 6B and gate line GL not shown
Can be formed. Then, as shown in FIG. 19A, a second photolithography process is performed to form a resist mask 8 in the center of the upper surface of the lower layer pad portion 6B. When the resist mask 8 is not formed in this way, an anodic oxide film is formed on the upper surface of the lower layer pad portion 6B, and it is necessary to remove the anodic oxide film when the upper layer pad portion is laminated later to make contact. In the wet etching at this time, since the underlying Al film has a remarkably higher etching rate than the anodic oxide film, the underlying Al film is also quickly etched when the underlying Al film is exposed, and the etching selectivity cannot be obtained. Therefore, the resist mask 8 is formed in advance to prevent anodization of the portion covered with the resist mask 8. No resist mask is formed on the gate electrode 6A (and the gate line GL). Anodizing in this state,
As shown in FIG. 19B, Al films (6A, 6B, G
An anodic oxide film 9 is formed on the exposed surface of L).

After performing such anodization, as shown in FIG.
, The gate insulating film 10 is deposited on the entire surface, and T
A semiconductor layer (not shown) is formed in the FT formation region. After that, the gate insulating film 10 in the pad portion forming region is removed to expose the lower pad portion 6B. Next, in the step of forming the source / drain electrodes, a metal film is deposited on the entire surface, and the metal film is used as a pad of the source electrode, the drain electrode, the drain line DL, and the drain line DL by using the photolithography technique and the etching technique. Part and the upper layer pad part 2 </ b> B which is laminated and connected to be processed as an upper layer pad part. In this way, the TFT 3 connected to the pad portion can be created on the glass substrate 1.

[0006]

However, in the conventional method described above, two photolithography steps (FIG. 18) are performed before the step of forming the gate insulating film 10.
(B) and FIG. 19 (A)), there is a problem of low throughput. In the resist stripping process that accompanies the photolithography process, the contamination caused by the resist residue left unpeeled and the stains on the stripping solution adversely affects the adhesion of the film and the device characteristics, but the yield increases as the number of photolithography processes increases. Will be a factor to reduce. Further, the chemical stripping of the resist does not have a clear evaluation parameter such as an etching rate as compared with other processes such as etching, and thus has a drawback that process control is difficult to perform. In particular, the gate electrode 6
A, the gate line GL, the lower pad portion 6B, etc. are LCDs.
Since the selection line of the pixel is formed, impairing the electrical characteristics leads to a decrease in yield.

An object of the present invention is to improve the throughput by reducing the number of photolithography steps, and what kind of means should be taken to manufacture an electronic device having good characteristics. is there. Another object of the present invention is what kind of means should be taken to obtain an etching method with good controllability of the anodic oxide film.

[0008]

According to the first aspect of the present invention,
An anodized film is formed on the surface of the first wiring layer, a connection opening is formed in an interlayer insulating film including the anodized film, and a first opening formed on the interlayer insulating film through the connection opening. Two
In an electronic device having a contact portion in which a wiring layer and the first wiring layer are connected to each other, the first wiring layer is formed by laminating a plurality of conductive material films, and among the conductive material films, It is characterized in that the upper conductive material film is formed of a material having an etching selection ratio with that of the underlying conductive material film.

In the present invention, the etching selection ratio between the uppermost conductive material film and the underlying conductive material film among the plurality of conductive material films forming the first wiring layer can be obtained. When the uppermost conductive material film is etched, the etching can be stopped when the underlying conductive material film is exposed. Therefore, the uppermost conductive material film in the first wiring layer can be anodized to form an anodic oxide film, which can improve the withstand voltage of the first wiring layer and prevent the occurrence of hillocks. The number of photolithography steps until formation can be reduced.

The invention according to claim 2 is characterized in that the conductive material film of the uppermost layer contains tantalum (Ta), and the underlying conductive material film contains aluminum (Al).

According to a third aspect of the present invention, the first wiring layer is a gate metal film of a thin film transistor, and the second wiring layer is a metal film for a gate of a thin film transistor.
The wiring layer is characterized by being a source / drain metal film.

The invention according to claim 4 is characterized in that the aluminum-based anodic oxide film anodized on the surface of the aluminum layer or the aluminum-based alloy layer is wet-etched using a barium hydroxide aqueous solution. Here, as the aluminum-based alloy, AlTi, AlN
b, AlMo, AlW, AlZr, AlNi, AlV,
An alloy such as AlPd can be applied.

According to a fifth aspect of the present invention, the etching temperature of the wet etching is set to 80 ° C. or higher. The invention according to claim 6 is characterized in that the concentration of the barium hydroxide aqueous solution is lower than 0.3 wt%.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, details of an electronic device having an anodized film and a method for etching an anodized film according to the present invention will be described based on each embodiment. (Embodiment 1) In this embodiment, the present invention is applied to a thin film transistor formed on a TFT substrate of an active matrix type LCD (AM-LCD).
(A) -FIG.4 (B) have shown the manufacturing process. First, in the present embodiment, as shown in FIG. 1A, on the glass substrate 11, the Al film 12 and Ta serving as the first wiring layer are formed.
The film 13 is continuously laminated by using the sputtering method. In addition,
To form these laminated films, for example, a multi-chamber process device is used to form the films without breaking the vacuum. Further, the film thickness of these laminated films is, for example, Al film 12, Ta
Each of the films 13 has a thickness of 150 nm.

Next, the Ta film 13 and the Al film 12 are processed by using the photolithography technique and the etching technique, and as shown in FIG.
The gate electrode 14 made of the I film 12 and the Ta film 13 is formed, and the lower layer pad part 15 made of a laminated film of the Al film 12 and the Ta film 13 is formed in the pad part formation region. Although not shown, a gate line is simultaneously formed using these laminated films.
Here, in the etching of the Ta film 13, dry etching using an etching gas of carbon tetrafluoride (CF ₄ ) and O ₂ (10%) is performed. Further, in the etching of the Al film 12, wet etching is performed in a temperature bath of 42 ° C. using a mixed acid of nitric acid, acetic acid, phosphoric acid and water.

After that, the exposed surfaces of the Al film 12 and the Ta film 13 patterned in the above steps are anodized. In the anodic oxidation in this embodiment, 1 mA / is applied until the voltage is raised to 80 V in a 3 wt% ammonium borate aqueous solution.
cm ² constant current oxidation, followed by constant voltage oxidation at 80V.
As a result, as shown in FIG. 1C, a TaOx film as an anodized film was formed on the surface of the Ta film 13, and an AlOx film 17 as an anodized film was formed on the sidewall of the Al film 12. . In this embodiment, the film thickness of the TaOx film is set to about 150 nm.

Next, as shown in FIG. 2A, a gate insulating film 18 made of SiN and a semiconductor layer 19 made of amorphous silicon (a-Si) are formed by using a plasma CVD method.
The SiN film 20 is sequentially deposited. In this embodiment, for example, the film thickness of the gate insulating film 18 is set to 300 nm and the film thickness of the semiconductor layer 19 is set to 50 nm. After that, the SiN film 20 is patterned by using a photolithography technique and an etching technique to form a blocking layer 20A as an etching stopper, as shown in FIG.

Then, as shown in FIG. 2B, an n ⁺ -Si film 21 as an ohmic contact film is formed on the entire surface by a plasma CVD method to a film thickness of about 25 nm.
After that, by using the photolithography technique and the etching technique, the semiconductor layer 19 and the n ⁺ -Si film 21 in the TFT formation region are patterned to form a device area, as shown in FIG. After that, the entire surface is ITO
The film is deposited to a film thickness of, for example, 50 nm by the sputtering method, and the pixel electrode 22 as shown in FIG. 3B is formed by using the photolithography technique and the etching technique.

Thereafter, as shown in FIG. 4A, a photoresist is applied to the entire surface, and exposure and development are performed to form a resist mask 23 for forming a contact hole in the pad portion forming region. And this resist mask 2
3A is used as a mask for etching, and FIG.
, The gate insulating film 18 in the pad portion forming region,
A contact hole 24 which penetrates the TaOx film 16 and the Ta film 13 and exposes the Al film 12 is opened. Note that this etching is performed with the gate insulating film (SiN) 18 and TaO.
The x film 16 and the Ta film 13 are dry-etched using CF ₄ —O ₂ (10%) gas, and a sufficient selection ratio with the Al film 12 can be obtained. In the present embodiment, when forming the anodic oxide film (TaOx film 16 and AlOx film 17), a photolithography process for covering the upper surface of the lower layer pad portion 15 with a photoresist so as not to be anodized is unnecessary, and gate insulation is performed. The number of photolithography steps until the film 18 is formed can be reduced. In the present embodiment, as described above, the Al film 12 and the gate insulating film (SiN) 18 and TaO formed thereon are formed.
Dry etching using a CF ₄ —O ₂ (10%)-based gas was performed as etching that can obtain a selective ratio with respect to the x film 16 and the Ta film 13, but the gate insulating film 18 and the Ta-based film (TaOx film 16 and Ta film 13) may be dry-etched with different etching gases.
In this case, S is used as an etching gas for the gate insulating film 18.
It is possible to use F ₆ and CF ₄ and O ₂ as etching gases for the Ta-based film.

Then, after removing the resist mask 23, chromium (C) as a source / drain metal film is formed.
r) After depositing the film on the entire surface by the sputtering method, the chromium film is patterned by using the photolithography technique and the etching technique, and as shown in FIG.
Upper layer pad portion 2 connected to Al film 12 and Ta film 13
5A, a source electrode 25C, a drain electrode 25B,
To form Needless to say, the drain line (not shown) is simultaneously formed by patterning the chromium film. In this way, the TFT 26 is formed in the TFT formation region and the pad portion 27 is formed in the pad portion formation region as shown in FIG.

As described above, in this embodiment, the gate metal film (Al film 1) is used as the electronic device having the anodic oxide film.
2. TF with an anodized film formed on the surface of Ta film 13)
T was explained. In the present embodiment, masking in the anodic oxidation of the pad portion (terminal portion) of the metal film for gate is not necessary, so the number of photolithography steps can be reduced. By reducing the number of steps as described above, the manufacturing cost of the electronic device can be reduced. In addition, it is possible to suppress adverse effects on the device characteristics due to the photolithography process.

(Embodiment 2) Next, the present invention will be described with reference to AM-L.
A second embodiment applied to a TFT as a protection element for preventing dielectric breakdown due to static electricity in a CD will be described. The TFT of this embodiment is also an electronic device having an anodic oxide film, and an outline thereof will be described using an equivalent circuit plan view shown in FIG. 5 prior to the description of the structure.

For example, T is used as a pixel switching element.
When manufacturing an AM-LCD having an FT, in order to improve productivity, a transparent substrate made of glass or the like, which is a base of the TFT substrate, having a size corresponding to a plurality of TFT substrates is prepared. In some cases, up to a predetermined process, a plurality of pieces are collectively manufactured, and then the individual pieces are divided and manufactured. Further, when manufacturing such a TFT substrate, for example, static electricity generated when rubbing the alignment film is used before dividing into individual pieces, and after dividing into individual pieces, high voltage such as static electricity is generated. By contacting with another object having a charge, dielectric breakdown may occur in the pixel TFT or the voltage-current characteristics of the pixel TFT may change. Therefore, countermeasures against static electricity are taken to prevent such a situation.

FIG. 5 is a plan view of an equivalent circuit in a state where pixel TFTs and the like are formed on a glass substrate having a size corresponding to a plurality of TFT substrates. TFT
A glass substrate 31 having a size corresponding to a plurality of substrates is finally cut along a cut line 32 indicated by a chain line so that the glass substrate 31 is cut into individual pieces. In this case, the area surrounded by the cut line 32 is the panel forming area 33, and the periphery thereof is the surplus portion 34. In the panel formation region 33, a plurality of pixel electrodes 35 arranged in a matrix and these pixel electrodes 3 are formed.
5, a plurality of pixel TFTs 36 connected to each other, a plurality of gate lines GL arranged in the row direction to supply a gate signal to the pixel TFT 36, and a plurality of gate lines GL arranged in the column direction to supply a data signal to the pixel TFT 36. A plurality of data lines DL and a plurality of auxiliary capacitance lines 39 which are arranged in the row direction and which form an auxiliary capacitance Cs in relation to the plane element electrode 35;
A plurality of protection rings (wirings) 40A arranged around the plurality of pixel electrodes 35, and two protection TFTs 41a and 41b connected to the protection ring 40A and each gate line GL outside the protection ring 40A. Of the gate line side protection element 41 and a plurality of data line side protection elements 42 each including two protection TFTs 42a and 42b connected to the protection ring 40A and each data line DL outside the protection ring. ing. Short lines 43 are provided in the surplus portion 34 in a grid pattern.

The left end of each gate line GL and the upper end of each data line DL are connected to the short line 43. The right end of each auxiliary capacitance line 39 is connected to the short line 43 via a common line 39a arranged parallel to the right side of the protection ring 40A and a connection line 39b extending from this common line 39a. The gate line side protection element 41 is a state in which two protection TFTs 41a and 41b having their respective gate electrodes G and source electrodes S connected to each other have their respective source electrodes S and drain electrodes D oriented in opposite directions. The gate line GL and the protection ring 40A are connected in parallel. The data line side protection element 42 is
The two protection TFTs 42a and 42b having their respective gate electrodes G and source electrodes S connected to each other have their respective source electrodes S and drain electrodes D oriented in opposite directions, and the protection ring 40A and the data line. It has a structure connected in parallel with the GL.

FIG. 6 is an explanatory plan view of a portion surrounded by a broken line in FIG. As shown in the figure, the protection TFT 41a,
The gate electrode G of 41b is formed by patterning the same metal film for gate as the gate line GL, and the source electrode S and the drain electrode D of both protection TFTs 41a and 41b are formed.
Are formed by patterning a common source / drain metal film. The metal film for gate and the metal film for source / drain are connected via contact holes 43, 44, 45, 46 as shown in FIG.

FIG. 7 is a cross-sectional view taken along the line AA of FIG. 6, showing the protection TFT 41a and the pad portion P formed at the end of the gate line GL, and the gate metal film (first wiring). The structure shows that the source / drain metal film (second wiring layer) is connected to the (layer). As shown in FIG. 7, also in this embodiment, an anodized film is formed on the surface of the gate metal film. The gate metal film is formed by stacking an Al film 37A and a Ta film 37B, and an anodic oxide film (AlOx film 48, TaOx film 49) is formed on the surface of these stacked films. The gate insulating film 5 made of, for example, SiN is formed on the glass substrate 31 on which the gate metal film covered with the anodic oxide film is formed.
0 is deposited. Gate insulating film 5 in the TFT formation region
On 0, a semiconductor layer 51 made of a-Si, a blocking layer 52 made of SiN, and an n ⁺ -Si film 53 are formed. Further, a contact hole 43 penetrating the gate insulating film 50, the TaOx film 49, and the Ta film 37B is formed in the pad portion formation region. Also, protection TFT
A contact hole 44 for connecting the source electrode S (40C) of 41a and the gate line GL is formed. Then, in the pad portion formation region, the upper pad portion 40D made of chromium (Cr) through the contact hole 43.
Are formed. In the contact hole 44, the source electrode 40C connecting the gate line GL and the protective TFT 41a is formed, and the protective TFT 41a is formed.
The drain electrode 40B is provided on the drain side of the protective ring 40.
It is formed integrally with A. The upper pad portion 40
The D, the source electrode 40C, the drain electrode 40B, and the protection ring 40A are formed of the same chromium film.

Also in this embodiment, masking in anodic oxidation of the pad portion (terminal portion) of the gate metal film and the contact hole forming portion is unnecessary, so that the number of photolithography steps can be reduced. By reducing the number of steps as described above, the manufacturing cost of the TFT can be reduced. In addition, it is possible to suppress adverse effects on the device characteristics due to the photolithography process.

(Embodiment 3) FIGS. 8A to 9B.
FIG. 7A is a process sectional view showing the manufacturing method of the third embodiment in which the present invention is applied to an MIM (Metal Insulator Metal) element. First, in the present embodiment, as shown in FIG. 8A, an Al film 62 and a Ta film 63 are formed on a glass substrate 61.
It is sequentially deposited by the sputtering method. The thickness of the Al film 62 is 100 nm, and the thickness of the Ta film 63 is 150 nm.
And Next, an address wiring (or a signal line) 64 is formed as shown in FIG. 8B using a photolithography technique and an etching technique. Thereafter, the same anodic oxidation as in the above-described first embodiment is performed to form a TaOx film 65 on the surface of the Ta film 63 as shown in FIG.
An AlOx film 66 is formed on the side wall of the I film 12. Thereafter, a pixel electrode 67 made of ITO is patterned in the MIM formation region, and a contact hole 68 exposing the Al film 62 is formed in the pad portion formation region. The method of etching the contact hole 68 is the same as in the first embodiment described above. Also in this embodiment, since the etching can be stopped when the Al film 62 is exposed (because the etching selection ratio can be obtained) regardless of having the anodic oxide film, a photoresist process unnecessary for forming the pad portion. There is no need to perform (masking step). Regarding Embodiments 1 to 3 described above, TaMo, T instead of the Ta film is used.
aW or TaNb may be used, and Al is used instead of Al film.
Ti, AlNb, AlMo, AlW, AlZr, AlN
An alloy film of i, AlV, AlPd or the like can be applied.

(Embodiment 4) This embodiment is an embodiment in which the method for etching an anodized film according to the present invention is applied to a method for manufacturing a thin film transistor. 10 (A) to 1
3B is a process sectional view of the present embodiment. First, in the present embodiment, the Al film 72 is formed on the glass substrate 71 by the sputtering method to have a film thickness of, for example, about 3000 Å. After that, the Al film is patterned by using the photolithography technique and the etching technique to form the gate electrode 72A in the TFT formation region and the lower pad portion 72B in the pad formation region. At this time, although not shown, the gate line is similarly patterned.

After that, as shown in FIG.
The gate electrode 72A made of a film, the lower layer pad portion 72B and the gate line are anodized. Here, the anodic oxidation condition is 150 wt% in a 2.5 wt% ammonium borate aqueous solution.
8 mA / cm ² constant current oxidation up to V, then 150 V
At a constant voltage to form an anodic oxide film 73 made of AlOx having a film thickness of 1500Å. At this time, the thickness of the Al film remaining without being anodized is about 2000 Å.

Next, as shown in FIG. 10C, a gate insulating film 74 made of SiN, a semiconductor layer 75 made of amorphous silicon, and a blocking layer (etching stopper layer) 76 made of SiN are sequentially formed by a plasma CVD method. The film is continuously formed. At this time, the film thickness of the gate insulating film 74 was set to 3000Å and the film thickness of the semiconductor layer 75 was set to 500Å. Then, the blocking layer 76 is formed by using a photolithography technique and an etching technique, as shown in FIG.
Patterning as shown in FIG.

Subsequently, as shown in FIG. 11A, an n ⁺ -Si film 77 is deposited on the entire surface to a thickness of, for example, about 250 Å by the plasma CVD method. Then, Figure 11
As shown in (B), the semiconductor layer 7 is formed only in the TFT formation region.
5 and the n ⁺ -Si film 77 remain, and the n ⁺ -Si film 77
Are patterned on the blocking layer 76 so as to be divided into a source side and a drain side. Further, for example, a pixel electrode 78 made of ITO is formed so as to be connected to the n ⁺ -Si film 77 on the source side.

Then, after applying photoresist on the entire surface, exposure and development are performed to pattern a resist pattern 79 as shown in FIG. 11C. And FIG.
As shown in FIG. 2A, the gate insulating film 74 is dry-etched using the resist pattern 79 as a mask. The etching gas for this dry etching is carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ : 10%).
Is used.

Then, as shown in FIG.
The anodic oxide film 73 made of Ox is wet-etched using a barium hydroxide aqueous solution described later to expose the lower pad portion 72B made of Al. In this way, the contact hole 80 exposing the lower layer pad portion 72B is formed in the pad portion forming region. Then, FIG.
As shown in (A), a source / drain metal film made of, for example, chromium (Cr) is deposited by a sputtering method, and then patterned to form a source electrode 81A, a drain electrode 81B, and an upper pad portion 81C. To do. Finally, as shown in FIG. 13B, after depositing an overcoat film 82 of SiN by the plasma CVD method,
A window is opened on the upper layer pad portion 81C and the pixel electrode 78, and the manufacturing of the thin film transistor of this embodiment is completed.

Next, the anodic oxide film (AlOx) 7 described above is used.
The selective etching method of No. 3 will be described. As a normal AlOx wet etching solution, various kinds of etching solutions such as phosphoric acid and hydrofluoric acid are known. Table 1 below
Shows the etching rate of Al and AlOx and the selection ratio of AlOx (AlOx etching rate / Al etching rate) of these etching solutions and the aqueous barium solution used in the present invention. In addition,
TMAH in the table indicates tetramethylammonium hydroxide.

[0037]

[Table 1]

As can be seen from Table 1 above, 0.27% by weight
It is understood that Ba (OH) ₂ and 0.054 wt% Ba (OH) ₂ have a selectivity of 0.3 or more at 80 ° C., which is higher than those of other etching solutions. For this reason,
Etching solutions other than the barium hydroxide solution are AlO
Since Al has a several times higher etching rate than x,
It can be seen that Al is rapidly etched at the end of etching AlOx.

Next, the temperature dependence and concentration dependence of the barium hydroxide aqueous solution will be described with reference to the graphs shown in FIGS. FIG. 14 shows the relationship between the etching temperature of the barium hydroxide aqueous solution and the etching rates of Al and AlOx. From this figure, it is understood that the etching rates of both Al and AlOx are increased by increasing the etching temperature. Also, it can be seen that the selection ratio is also improved.

Further, FIG. 15 shows the relationship between the barium hydroxide aqueous solution concentration and the etching rates of Al and AlOx. From this figure, it is understood that the etching rates of both Al and AlOx are lowered by decreasing the concentration of the barium hydroxide aqueous solution, but the etching rate of AlOx is 1000Å / min even at 0.054 wt%.

FIG. 16 shows the relationship between the barium hydroxide aqueous solution concentration and the selection ratio. From this figure, it can be seen that the selection ratio is dramatically improved by lowering the concentration of the barium hydroxide aqueous solution.

As described above, according to the present invention, by using the barium hydroxide aqueous solution, the AlOx / Al selectivity ratio of 0.86 can be obtained, and the AlOx etching rate is sufficiently high at 1000 / min. Thick AlOx
Even if the etching is performed, the underlying Al having a thickness of 2000 Å can be processed without being removed, and selective etching can be performed.

Although the respective embodiments have been described above, the present invention is not limited to these and can be applied to various electronic devices. Further, in the fourth embodiment, the anodic oxide film AlOx of the Al film was described as the anodic oxide film, but in addition to this, as alternative aluminum alloys for the Al film, AlTi, AlNb, A
1Mo, AlW, AlZr, AlNi, AlV, AlP
Alloys such as d can be applied.

[0044]

As is apparent from the above description, according to the present invention, in the manufacture of an electronic device having an anodic oxide film, the number of photolithography steps is reduced to improve the throughput and further improve the characteristics. The effect is that an excellent electronic device can be manufactured. Further, according to the present invention, it is possible to realize an etching method with good controllability of the anodic oxide film.

[Brief description of drawings]

1A to 1C are process cross-sectional views of Embodiment 1 of the present invention.

2A and 2B are process sectional views of Embodiment 1 of the present invention.

3A and 3B are process sectional views of Embodiment 1 of the present invention.

4A and 4B are process sectional views of Embodiment 1 of the present invention.

FIG. 5 is an equivalent circuit plan view of the second embodiment of the present invention.

6 is an explanatory plan view of a broken line area in FIG.

FIG. 7 is a sectional view taken along the line AA of FIG. 6;

8A and 8B are process cross-sectional views showing the manufacturing process of the MIM element that is Embodiment 3 of the present invention.

9A and 9B are process cross-sectional views showing a manufacturing process of an MIM element that is Embodiment 3 of the present invention.

10A to 10C are process cross-sectional views showing a fourth embodiment of the present invention.

11A to 11C are process cross-sectional views showing a fourth embodiment of the present invention.

12A and 12B are process cross-sectional views showing a fourth embodiment.

13A and 13B are process cross-sectional views showing a fourth embodiment.

FIG. 14 is a graph showing the relationship between the etching rate temperature of a barium hydroxide aqueous solution and the etching rates of Al and AlOx.

FIG. 15: Barium hydroxide aqueous solution concentration, Al, AlO
The graph which shows the relationship with the etching rate of x.

FIG. 16: Barium hydroxide aqueous solution concentration and AlOx / Al
A graph showing the relationship with the selection ratio of.

FIG. 17 is an explanatory plan view of a TFT substrate.

18A to 18C are process cross-sectional views showing a conventional method of manufacturing a thin film transistor.

19A and 19B are process cross-sectional views showing a method of manufacturing a conventional thin film transistor.

FIG. 20 is a process cross-sectional view showing the method of manufacturing a conventional thin film transistor.

[Explanation of symbols]

 12 Al film 13 Ta film 14 Gate electrode (first wiring layer) 15 Lower pad portion (first wiring layer) 16 TaOx film 17 AlOx 18 Gate insulating film 24 Contact hole 25A Upper pad portion (second wiring layer)

Claims (6)

[Claims] 1. An anodized film is formed on a surface of a first wiring layer, a connection opening is formed in an interlayer insulating film including the anodized film, and the interlayer insulating film is formed on the interlayer insulating film through the connection opening. In the electronic device having a contact portion in which the second wiring layer formed in the above and the first wiring layer are connected to each other, the first wiring layer is formed by stacking a plurality of conductive material films, An electronic device having an anodic oxide film, characterized in that the uppermost conductive material film of the material films is formed of a material having an etching selection ratio with the underlying conductive material film. 2. The electron having an anodic oxide film according to claim 1, wherein the uppermost conductive material film contains tantalum (Ta) and the underlying conductive material film contains aluminum (Al). device. 3. The anode according to claim 1, wherein the first wiring layer is a metal film for a gate of a thin film transistor, and the second wiring layer is a metal film for a source / drain. An electronic device having an oxide film. 4. A method of etching an anodic oxide film, which comprises wet-etching an aluminum anodic oxide film anodized on the surface of an aluminum layer or an aluminum alloy layer with an aqueous barium hydroxide solution. 5. The etching temperature of the wet etching is set to 80 ° C. or higher.
A method for etching an anodic oxide film as described above. 6. The concentration of the barium hydroxide aqueous solution is
The method for etching an anodic oxide film according to claim 4 or 5, wherein the content is lower than 0.3 wt%.