JP3094610B2 - Method for manufacturing thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, thin film transistors (TFTs)
It has the following configuration.

FIG. 7 is a cross-sectional view of a conventional thin film transistor. Here, a thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device is shown.

The above-mentioned TFT panel has a pixel electrode 2 and a thin film transistor 3 as an active element formed on a transparent substrate 1 made of glass or the like. The thin film transistor 3 generally has an inverted stagger structure. I have.

The above-mentioned thin film transistor 3 having an inverted stagger structure
A gate electrode G formed on the substrate 1, a gate insulating film (transparent film) 4 covering the gate electrode G, an i-type semiconductor layer 5 formed on the gate insulating film 4, It comprises a source electrode S and a drain electrode D formed on the semiconductor layer 5 via an n-type semiconductor layer 6 and a contact layer 7.

The i-type semiconductor layer 5 is formed of a-Si (amorphous silicon), the n-type semiconductor layer 6 is formed of a-Si doped with an n-type impurity, and the contact layer 7 is formed.
Is C having good ohmic contact with the n-type semiconductor layer 6
The n-type semiconductor layer 6 and the contact layer 7 are formed of a metal such as r (chromium), and correspond to a channel region (a region between the source electrode S and the drain electrode D) of the i-type semiconductor layer 5. Are separated and separated.

The gate electrode G of the thin film transistor 3 is connected to a gate line (not shown) formed on the substrate 1.
The gate insulating film 4 is formed over substantially the entire surface of the substrate 1 so as to cover the gate electrode G and the gate line. The gate insulating film 4 is formed of SiN (silicon nitride) or the like, and a data line (not shown) connected to the drain electrode D is formed on the gate insulating film 4. The gate electrode G and the gate line and the drain electrode D and the data line are
It is formed of Al (aluminum) or an Al alloy.

On the channel region of the i-type semiconductor layer 4, a blocking layer 8 made of SiN or the like is formed. The blocking layer 8 is used to separate the channel region corresponding to the channel region of the n-type semiconductor layer 6 formed on the i-type semiconductor layer 5 by etching when the thin film transistor 3 is manufactured. It is provided to prevent etching.

On the other hand, the pixel electrode 2 is formed on the gate insulating film 4 so as to cover the thin film transistor 3.
It is formed on a protective insulating film (transparent film) 9 made of iN or the like. The pixel electrode 2 is formed of a transparent conductive film made of ITO or the like, and its end is connected to the source electrode S of the thin film transistor 3 at a contact hole 9 a provided in the protective insulating film 9.

The thin film transistor 3 is manufactured by the following steps.

[Step 1] A metal film for a gate is formed on the substrate 1, and the metal film is patterned by photolithography to form a gate electrode G and a gate line.

[Step 2] A gate insulating film 4 is formed on the substrate 1 so as to cover the gate electrode G and the gate line.
An i-type semiconductor layer 5 and a blocking layer 8 are sequentially formed.

[Step 3] The blocking layer 8 is patterned by photolithography so as to cover the channel region of the i-type semiconductor layer 5.

[Step 4] An n-type semiconductor layer 6 and a contact layer 7 are sequentially formed.

[Step 5] The contact layer 7, the n-type semiconductor layer 6, and the i-type semiconductor layer 5 are patterned by photolithography so as to have an outer shape of a transistor element region.

[Step 6] A metal film for source and drain is formed.

[Step 7] The source and drain metal films are patterned by photolithography to form source and drain electrodes S and D and data lines, and the contact layer 7 is formed with the source and drain electrodes S and D The n-type semiconductor layer is patterned to have the same shape, and the portion between the source and drain electrodes S and D of the n-type semiconductor layer 6 is etched while the resist mask used for patterning the metal film and the contact layer 7 is left. 6
Are separated and separated to complete the thin film transistor 3.

In this case, the n-type semiconductor layer 6 is separated on the blocking layer 8 formed on the i-type semiconductor layer 4, so that when the n-type semiconductor layer 6 is etched, The channel region of layer 5 is not etched and damaged. However, since the n-type semiconductor layer 6 removes not only the portion between the source and drain electrodes S and D, but also the portions protruding outside the ends of the source and drain electrodes S and D and the pixel electrode, this portion is removed. In this case, the i-type semiconductor layer 5 is also etched, but since this portion does not affect the characteristics of the thin film transistor 3, even if the surface of the i-type semiconductor layer 5 is etched in this portion,
Alternatively, there is no particular problem even if the i-type semiconductor layer 5 is removed.

The TFT panel is manufactured by the following steps after forming the thin film transistor 3 on the substrate 1 in the above steps.

[Step 8] A protective insulating film 9 is formed.

[Step 9] A contact hole 9a corresponding to the source electrode S of the thin film transistor 3 and an opening (not shown) corresponding to a terminal portion of a data line and a gate line are formed in the protective insulating film 9 by photolithography. At the same time, an opening is formed in a portion of the gate insulating film 4 above the gate line terminal.

[Step 10] A transparent conductive film is formed.

[Step 11] The transparent conductive film is patterned by photolithography to form the contact hole 9.
At a, the pixel electrode 2 connected to the source electrode S of the thin film transistor 3 is formed.

[0024]

However, the above-mentioned conventional thin film transistor 3 has an insulating material (SiN) similar to the gate insulating film 4 on the channel region of the i-type semiconductor layer 5.
Since the blocking layer 8 is formed in the gate insulating film 4 under the i-type semiconductor layer 5 when the blocking layer 8 is patterned in the manufacturing process of the thin film transistor 3, defects such as pinholes are generated. There was a thing.

This is because a pinhole may be formed in the i-type semiconductor layer 5. Even if a pinhole is formed in the i-type semiconductor layer 5, the semiconductor characteristics do not change so much. If the layer 5 has a pinhole, when the blocking layer 8 formed on the i-type semiconductor layer 5 is patterned, the etching solution reaches the gate insulating film 4 through the pinhole of the i-type semiconductor layer 5. . And Si N
Since the patterning of the blocking layer 8 is performed using a hydrofluoric acid-based etchant such as BHF, when the etchant reaches the gate insulating film 4, the gate insulating film 4 is also etched to remove defects such as pinholes. Occurs.

If there is no defect in the i-type semiconductor layer 5,
Although the gate insulating film 4 is not etched during the patterning of the blocking layer 8, it is desirable to reduce the thickness of the i-type semiconductor layer 5 as much as possible in order to improve the characteristics of the thin film transistor. It is difficult to form the semiconductor layer 5.

Since the n-type semiconductor layer 6 and the source and drain electrodes S and D are formed after patterning the blocking layer 8 as described above, the above-described pinholes are generated in the gate insulating film 4. In this case, an interlayer short circuit occurs between the gate electrode G and the source and drain electrodes S and D. This interlayer short-circuit also occurs at the intersection of the gate line and the data line.

Therefore, the conventional thin film transistor 3
Have a problem that interlayer short-circuits often occur during the manufacturing process, and therefore the manufacturing yield is poor.

An object of the present invention is to electrically separate an n-type semiconductor layer without providing a blocking layer on the i-type semiconductor layer and without damaging a channel region of the i-type semiconductor layer. It is an object of the present invention to provide a method for manufacturing a thin film transistor capable of manufacturing a thin film transistor having no short circuit with a high yield.

[0030]

A method of manufacturing a thin film transistor according to the present invention comprises a first step of forming a gate electrode on a substrate, and a step of forming a gate insulating film, an i-type semiconductor layer and an n-type semiconductor layer on the substrate. A second step of sequentially forming a contact layer and a contact layer; a third step of patterning the contact layer, the n-type semiconductor layer and the i-type semiconductor layer to the outer shape of the transistor element region; A fourth step of forming a film and patterning the source and drain metal films to form source and drain electrodes;
A fifth step of patterning the contact layer into the shape of the source and drain electrodes, and oxidizing the n-type semiconductor layer while leaving the resist mask used for patterning the source and drain metal films and the contact layer. A sixth step of forming a portion between the source and drain electrodes of the n-type semiconductor layer as an oxide insulating layer.

[0031]

According to the method of manufacturing a thin film transistor of the present invention, an n-type semiconductor layer is electrically separated into a source side and a drain side by forming a portion between its source and drain electrodes as an insulating layer by oxidation. Since this manufacturing method does not separate the n-type semiconductor layer by etching, the channel region of the i-type semiconductor layer may be damaged without providing a blocking layer on the i-type semiconductor layer. Will not give. According to this manufacturing method, there is no need to provide a blocking layer on the i-type semiconductor layer. Therefore, unlike a conventional thin film transistor, a defect such as a pinhole is generated in the gate insulating film at the time of patterning the blocking layer. Therefore, an interlayer short-circuit between the gate electrode and the source / drain electrodes can be prevented, and the production yield can be improved.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, taking as an example the manufacture of a thin film transistor formed on a TFT panel used for an active matrix liquid crystal display device.

First, the structure of the thin film transistor manufactured by the manufacturing method of this embodiment will be described. Figure 3 shows the above TFT
FIG. 4, FIG. 5, FIG. 6 and FIG.
It is an expanded sectional view which follows the IV-IV line, the VV line, and the VI-VI line.

This TFT panel has a pixel electrode 20 and a thin film transistor (TFT) 30 as an active element formed on a transparent substrate 10 made of glass or the like.

As shown in FIGS. 3 and 4, the thin film transistor 30 has a gate electrode G formed on a substrate 10.
And a gate insulating film 12 covering the gate electrode G, and an i-type semiconductor layer 13 formed on the gate insulating film 12
And a source electrode S and a drain electrode D formed on the i-type semiconductor layer 13 via the n-type semiconductor layer 14 and the contact layer 15.

The i-type semiconductor layer 13 is formed of a-Si, and the n-type semiconductor layer 14 is formed of a-type semiconductor doped with an n-type impurity.
The contact layer 15 is made of a metal such as Cr.

The gate electrode G is formed integrally with the gate line GL formed on the substrate 10, and the gate insulating film 12 is formed on almost the entire surface of the substrate 10 so as to cover the gate electrode G and the gate line GL. I have. The gate insulating film 12 is formed of SiN or the like, and a data line DL connected to the drain electrode D is formed on the gate insulating film 12. The gate electrode G and the gate line GL are formed of a gate metal film 11 such as Al or an Al alloy.
D and the data line DL are formed of a source / drain metal film 16 such as Al or an Al alloy.

The contact layer 15 is separated and separated into a source side and a drain side. The source side contact layer 15 is formed in the same shape as the source electrode S.
The drain-side contact layer 15 is formed in the same shape as the drain electrode D.

Further, the n-type semiconductor layer 14 is formed over the entire area of the i-type semiconductor layer 13,
The portion between the source and drain electrodes S and D of the n-type semiconductor layer 14 is an oxide insulating layer 14a obtained by oxidizing this portion over the entire thickness. That is, the n-type semiconductor layer 14 is electrically separated into a source side and a drain side by using a portion between the source and drain electrodes S and D as an oxide insulating layer 14a. Note that the outer peripheral portions of the i-type semiconductor layer 13 and the n-type semiconductor layer 14 extend outside the source and drain electrodes S and D, and the portions of the n-type semiconductor layer 14 extending outside the drain electrode D are also oxidized. The surface of the portion protruding outside the source electrode S together with the oxide insulating layer 14a is slightly oxidized, though not shown.

On the other hand, the pixel electrode 20 is formed on a protective insulating film 17 made of SiN or the like formed on the gate insulating film 12 so as to cover the thin film transistor 30. The pixel electrode 20 is formed of a transparent conductive film 18 made of ITO or the like, and its end is connected to the source electrode S of the thin film transistor 30 at a contact hole 17 a provided in the protective insulating film 17.

The terminal portion DL of the data line DL
a has a two-layer structure as shown in FIG. 3 and FIG. 5. The lower layer film is formed by the source and drain metal films 16 and the upper layer film is formed by the transparent conductive film 18. The upper film (transparent conductive film) 18 is formed of a protective insulating film 17.
Is formed on the lower layer film (metal film for source and drain) 16 in the opening 17b provided in the substrate.

Further, the terminal G of the gate line GL
La has a two-layer structure as shown in FIGS. 3 and 6. The lower layer is formed by the gate metal film 11, and the upper layer is formed by the transparent conductive film 18. The upper layer (transparent conductive film) 18 is laminated on the lower layer (gate metal film) 11 in openings 12 a and 17 c provided in the gate insulating film 12 and the protective insulating film 17.

Next, a method of manufacturing the TFT panel will be described.

FIG. 1 is a view showing a manufacturing process of the thin film transistor 13, and FIG.
FIGS. 1A to 1D and FIGS. 2E to 2H show cross sections of a thin film transistor portion, a data line terminal portion, and a data line terminal portion of a TFT panel, respectively. ing.

[Step 1] First, as shown in FIG. 1A, a gate electrode G is formed on a transparent substrate 10 made of glass or the like.
And a gate line GL (see FIG. 3). The gate electrode G and the gate line GL are formed by forming a gate metal film 11 on the substrate 10 and patterning the metal film 11 by photolithography. Note that the metal film 11 shown at the right end in FIG.
Is a lower layer film of the gate line terminal portion GLa.

[Step 2] Next, as shown in FIG. 1A, a gate insulating film 12 and an i-type semiconductor layer are formed on the substrate 10 so as to cover the gate electrode G and the gate line GL. 13, an n-type semiconductor layer 14, and a contact layer 15
Are sequentially formed.

[Step 3] Next, as shown in FIG. 1B, the contact layer 15, the n-type semiconductor layer 14, and the i-type semiconductor layer 13 are formed on the outer shape of the transistor element region by photolithography. Perform patterning.

[Step 4] Next, as shown in FIG. 1C, a patterned layer 1 is formed on the gate insulating film 12.
5, 14 and 13, the source and drain metal films 16
Is formed.

[Step 5] Next, as shown in FIG. 1D, the metal film 16 for source and drain is patterned by photolithography to form source and drain electrodes S and D and a data line DL (FIG. 3), and the contact layer 15 is patterned into the shapes of the source and drain electrodes S and D using the resist mask 19 used for patterning the source and drain metal films 16. In FIG. 1D, the metal film 16 shown on the right side of the drawing is a lower layer film of the data line terminal portion DLa.

[Step 6] Next, as shown in FIG. 1D, the resist mask 1 used for patterning the source / drain metal film 16 and the contact layer 15 is used.
9 is left as it is, the n-type semiconductor layer 15 is oxidized to form an oxide insulating layer 14a in which a portion between the source and drain electrodes S and D is oxidized over the entire thickness thereof. The semiconductor layer 14 is electrically separated into a source side and a drain side to form a thin film transistor 30.
To complete.

The oxidation of the n-type semiconductor layer 14 is performed, for example, by anodic oxidation.
Is immersed in the electrolytic solution so that the n-type semiconductor layer 14 faces the counter electrode (platinum electrode) in the electrolytic solution.
4 is used as an anode, and the opposite electrode is used as a cathode, by applying a voltage between the two electrodes. As described above, when a voltage is applied between the n-type semiconductor layer 14 and the counter electrode in the electrolytic solution, a region (a region in contact with the electrolytic solution) of the n-type semiconductor layer 14 serving as an anode that is not covered with the resist mask 19 is formed. An anodization is caused by a chemical reaction, and an oxidized region of the n-type semiconductor layer 14 becomes an oxide insulating layer 14a.

In this case, the n-type semiconductor layer 14 is oxidized from the surface side, but the oxidation depth is mainly determined by the applied voltage. With this setting, the oxidized region of the n-type semiconductor layer 14 can be oxidized over its entire thickness.

The current supply to the n-type semiconductor layer 14 in the anodic oxidation can be performed through the data line DL through the drain electrode D using the data line DL as a current path. The n-type semiconductor layers 14 of all the formed thin film transistors 30 can be uniformly anodized. In this case, the side surfaces of the drain electrode D and the data line DL are formed by a resist mask 1
9, the side surfaces of the drain electrode D and the data line DL are also anodized (an oxide layer is not shown).
, Only the side surface becomes an oxide insulating layer, and the central portion is not oxidized.

Since the outer peripheral portions of the i-type semiconductor layer 13 and the n-type semiconductor layer 14 extend outside the source and drain electrodes S and D (outside the resist mask 19), the n-type semiconductor layer 14 The portion projecting outside the drain electrode D is also oxidized to become the oxide insulating layer 14a, and the surface of the portion projecting outside the source electrode S and the side surface of the source electrode S are slightly oxidized, though not shown. You.

The resistivity of the i-type semiconductor layer 13 (resistivity when no gate voltage is applied to the gate electrode G) is three orders of magnitude greater than the resistivity of the n-type semiconductor layer 14. When anodizing the n-type semiconductor layer 14, the i-type semiconductor layer 13 thereunder is not oxidized.

The TFT panel is manufactured by the following process after forming the thin film transistor 30 on the substrate 11 in the above process.

[Step 7] First, the resist mask 19
Then, as shown in FIG. 2E, a protective insulating film 17 is formed on the gate insulating film 12 so as to cover the thin film transistor 30.

[Step 8] Next, as shown in FIG. 2F, the protective insulating film 17 is patterned by photolithography to form a contact hole 17 a corresponding to the source electrode S of the thin film transistor 30 and a data line. Openings 17b and 17c corresponding to the terminal portion DLa and the gate line terminal portion GLa are formed, and an opening 12a corresponding to the gate line terminal portion GLa is also formed in the gate insulating film 12.

[Step 9] Next, as shown in FIG. 2G, a transparent conductive film 18 such as an ITO film is formed. At this time, the transparent conductive film 18 is also formed in the contact hole 17a and the openings 17b and 17c provided in the protective insulating film 17 and in the opening 12a of the gate insulating film 12, and the source electrode S of the thin film transistor 30 and the data Line terminal section DLa
And a lower layer film (source and drain metal film and gate metal film) 16 and 11 of the gate line terminal portion GLa.

[Step 10] Next, as shown in FIG. 2 (h), the transparent conductive film 18 is formed by photolithography on the pixel electrode 20 and the upper layer film of the data line terminal portion DLa and the gate line terminal portion GLa. Patterned into
Complete the TFT panel.

That is, in the above manufacturing method, the n-type semiconductor layer 14 of the thin film transistor 30 is oxidized at the portion between the source and drain electrodes S and D to form an insulating layer 14a. Since this manufacturing method does not separate and separate the n-type semiconductor layer by etching as in the conventional method,
Even if the blocking layer is not provided on the i-type semiconductor layer 14, the channel region of the i-type semiconductor layer 14 will not be damaged.

According to this manufacturing method, since there is no need to provide a blocking layer on the i-type semiconductor layer 13, defects such as pinholes are generated in the gate insulating film at the time of patterning the blocking layer as in the related art. Therefore, an interlayer short circuit between the gate electrode G and the source and drain electrodes S and D and between the gate line GL and the data line DL can be prevented, and the manufacturing yield can be improved. .

In the above embodiment, the n-type semiconductor layer 14
The portion between the source and drain electrodes S and D of the n-type semiconductor layer 14 is oxidized by an oxidation treatment that causes a chemical reaction in the electrolytic solution. Plasma oxidation.

In the above embodiment, the manufacture of a thin film transistor formed on a TFT panel used for an active matrix liquid crystal display device has been described. However, the present invention is not limited to the thin film transistor of the TFT panel, but may be applied to various circuit boards and the like. It can be widely applied to the manufacture of a formed thin film transistor.

[0065]

The method of manufacturing a thin film transistor according to the present invention comprises:
The n-type semiconductor layer is electrically separated into a source side and a drain side by oxidizing a portion between its source and drain electrodes to form an insulating layer. Since it is not separated by etching, the channel region of the i-type semiconductor layer is not damaged even if the blocking layer is not provided on the i-type semiconductor layer. According to this manufacturing method, there is no need to provide a blocking layer on the i-type semiconductor layer. Therefore, unlike a conventional thin film transistor, a defect such as a pinhole is generated in the gate insulating film at the time of patterning the blocking layer. Will not be lost and therefore
An interlayer short-circuit between the gate electrode and the source and drain electrodes can be prevented, and the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a thin film transistor formed on a TFT panel according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a TFT panel after manufacturing a thin film transistor.

FIG. 3 is a plan view of a part of the manufactured TFT panel.

FIG. 4 is an enlarged sectional view taken along the line VI-IV in FIG. 3;

FIG. 5 is an enlarged sectional view taken along line VV of FIG. 3;

FIG. 6 is an enlarged sectional view taken along the line IV-IV in FIG. 3;

FIG. 7 is a cross-sectional view of a thin film transistor formed on a conventional TFT panel.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Substrate, 20 ... Pixel electrode, 30 ... Thin film transistor, 11 ... Gate metal film, G ... Gate electrode, GL ... Gate line, GLa ... Terminal part, 12 ... Gate insulating film, 1
3 ... i-type semiconductor layer, 14 ... n-type semiconductor layer, 14a ... oxide insulating layer, 15 ... contact layer, 16 ... metal film for source and drain, S ... source electrode, D ... drain electrode, DL ...
Data line, DLa: terminal section, 17: protective insulating film, 1
8: transparent conductive film, 19: resist mask.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 H01L 21/336 H01L 29/786

Claims (1)

(57) [Claims] A first step of forming a gate electrode on a substrate; and a second step of sequentially forming a gate insulating film, an i-type semiconductor layer, an n-type semiconductor layer, and a contact layer on the substrate. And the contact layer, the n-type semiconductor layer and the i-type semiconductor layer,
A third step of patterning the outer shape of the transistor element region, a fourth step of forming a source / drain metal film, and forming a source / drain electrode by patterning the source / drain metal film. A fifth step of patterning the contact layer into the shape of the source and drain electrodes; and the n step while leaving the resist mask used for patterning the source and drain metal films and the contact layer.
A sixth step of oxidizing the type semiconductor layer and using the portion between the source and drain electrodes of the n-type semiconductor layer as an oxide insulating layer.