CN110233109A - Transistor and preparation method thereof, array substrate and preparation method thereof and display panel - Google Patents
Transistor and preparation method thereof, array substrate and preparation method thereof and display panel Download PDFInfo
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- CN110233109A CN110233109A CN201910549814.3A CN201910549814A CN110233109A CN 110233109 A CN110233109 A CN 110233109A CN 201910549814 A CN201910549814 A CN 201910549814A CN 110233109 A CN110233109 A CN 110233109A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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Abstract
The present invention provides a kind of transistor and preparation method thereof, array substrate and preparation method thereof and display panel.The transistor includes substrate; grid, gate insulation layer, active layer, ohmic contact layer, source electrode and drain electrode successively far from substrate setting; source electrode and drain electrode is divided into the opposite end of active layer; ohmic contact layer is correspondingly arranged in source electrode and drain electrode region; transistor further includes protective layer; protective layer is arranged between active layer and ohmic contact layer, and protective layer can form protection to the active layer part between source electrode and drain electrode in preparation process.The transistor is avoided by setting protective layer and is fallen metal atom contamination active layer part, active layer segment thickness homogeneity difference in active layer part etc. when ohmic contact layer etching causes damage, ohmic contact layer to etch the active layer part between transistor source and drain electrode after ion bombardment source electrode and drain electrode side wall and lead to that leakage current is bigger than normal, problem of transistor characteristic homogeneity difference.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of transistor and preparation method thereof, array substrate and its system
Preparation Method and display panel.
Background technique
Liquid crystal display panel (TFT-LCD) has many advantages, such as that good brightness, contrast are high, low in energy consumption, small in size, light-weight.
As market requires higher and higher and frame requirement more and more narrow liquid crystal display panel PPI (resolution ratio), using GOA (grid
Pole driving circuit design in array substrate) design can significantly reduce display screen left and right side frame and reduce IC (driving chip) at
This；On the other hand, using GI (gate insulation layer) via hole that Gate (grid) metal and SD (source-drain electrode) is golden for GOA design section
Belong to steam during overlap the frame that can further decrease display screen, and improvement high temperature and humidity reliability and enters GOA
It's the problem of hole site conductive layer pasts region post-etching.
For using a-Si as the display products of active layer material, in order to reduce the electricity of the contact between a-Si and SD metal
Resistance needs and then to deposit one layer of n+a-Si film layer above a-Si, it is subsequent must be by n+a-Si Etch (etching technics) by channel
Place's n+a-Si thin layer is got rid of, and is needed to carve and etched n+a-Si thin layer completely to ensure that TFT (thin film transistor (TFT)) is played
Normal switching effect.But n+a-Si Etch crosses quarter process can cause many adverse effects, first, n+a-Si to TFT characteristic
Etch can have damage back channel surface, increase back channel a-Si dangling bonds；The ionization ion meeting portion of second, n+a-Si Etch
Divide bombardment to SD side wall at channel, the SD metallic atom for being sputtered out, which is fallen on, can pollute back channel above TFT channel；Third, n
The homogeneity of a-Si remaining thickness can be deteriorated with respect to a-Si itself after+Si film layer is carved excessively, these factors can all cause TFT to manage
There is the leakage current problem bigger than normal with TFT property uniformity difference in son.
As shown in Figure 1, when TFT pipe leakage current increases, it may appear that grayscale different zones pixel voltage is pulled and occurs
Crosstalk is bad；As shown in Fig. 2, there is the residual sand phenomenon of apparent ITO at TFT channel；According to existing design technique, at SD layers
Before technique carries out, Si film layer needs to contact many chemical liquids or gas by many processes in TFT pipe, this will increase
Technique manages difficulty, as shown in figure 3, channel region n+a-Si caused by P/T or technological fluctuation is remained during processing procedure.From Fig. 3
It can be seen that n+a-Si caused by having ITO to remain at channel etches a- at channel caused by sordid kick, technological fluctuation
Metallic pollutes channel after Si residual thickness is partially thin, SD side wall is sputtered by n+a-Si Etch ionization.These problems will cause
TFT leakage current increase, property uniformity be deteriorated and deteriorate, finally by the production yield of serious shadow product, final display effect and
Reliability evaluation, also will increase the control difficulty of TFT Array (tft array substrate) making technology.
Summary of the invention
The present invention is directed to the problems of the prior art, provides a kind of transistor and preparation method thereof, array substrate and its system
Preparation Method and display panel.The transistor is avoided that ohmic contact layer etching to transistor source and leakage by setting protective layer
It causes to fall after ion bombardment source electrode and drain electrode side wall active when damage, ohmic contact layer etching in active layer part between pole
The layer metal atom contamination active layer part of part, active layer segment thickness homogeneity difference etc. lead to that leakage current is bigger than normal, transistor
The problem of property uniformity difference.
The present invention provides a kind of transistor, including substrate, successively far from the substrate setting grid, gate insulation layer, have
Active layer, ohmic contact layer, source electrode and drain electrode, the source electrode and described drain are divided into the opposite end of the active layer, described
Ohmic contact layer is correspondingly arranged in the source electrode and the drain electrode region, and the transistor further includes protective layer, the guarantor
Sheath is arranged between the active layer and the ohmic contact layer, and the protective layer can be in preparation process to positioned at the source
The active layer part between pole and the drain electrode forms protection.
Preferably, the active layer uses amorphous silicon material, and the ohmic contact layer uses the amorphous silicon material of n-type doping
Material, the protective layer use inorganic insulating material.
Preferably, the protective layer includes one or more sub- film layers, and multiple sub- film layers are stacked on top of each other.
Preferably, the thickness range of the protective layer is 50~200nm.
The present invention also provides a kind of preparation methods of above-mentioned transistor, including successively prepare to form grid, grid in substrate
Insulating layer, active layer, ohmic contact layer, source electrode and drain electrode after preparation forms the active layer and are being prepared described in formation
Before ohmic contact layer further include: preparation forms protective layer.
The present invention also provides a kind of array substrates, including above-mentioned transistor.
It preferably, further include pixel electrode, the pixel electrode connects the drain electrode of the transistor, and the pixel electrode is set
It is placed on the protective layer of the transistor.
The present invention also provides a kind of preparation methods of above-mentioned array substrate, including form transistor.
Preferably, the protective layer of the transistor is formed after preparation forms the active layer of the transistor and in preparation
It prepares to be formed before pixel electrode.
The present invention also provides a kind of display panels, including above-mentioned array substrate.,
Beneficial effects of the present invention: transistor provided by the present invention, by being set between active layer and ohmic contact layer
Protective layer is set, contacts active layer part of the ohmic contact layer in etching completely not between source electrode and drain electrode, to avoid
When ohmic contact layer etching causes damage, ohmic contact layer to etch active layer part between transistor source and drain electrode from
It falls after son bombardment source electrode and drain electrode side wall in the metal atom contamination active layer part of active layer part, active layer segment thickness
Homogeneity difference etc. leads to that leakage current is bigger than normal, problem of transistor characteristic homogeneity difference.
Array substrate provided by the present invention can be avoided ohmic contact layer etching to crystalline substance by using above-mentioned transistor
Ion bombardment source electrode and drain electrode side wall when active layer part between body pipe source electrode and drain electrode causes damage, ohmic contact layer to etch
Falling the metal atom contamination active layer part in active layer part, active layer segment thickness homogeneity difference etc. afterwards leads to leakage current
Bigger than normal, transistor characteristic homogeneity difference problem；It it can also be used in preparation simultaneously forms the conductive film layer of pixel electrode and etch
It does not contact directly with active layer part, is remained at active layer part when so as to avoid conductive film layer etching completely in the process
Lead to the problem that transistor drain current is bigger than normal and its property uniformity is poor, improves production yield, the display effect of the array substrate
Fruit and reliability evaluation.
Display panel provided by the present invention, by using above-mentioned array substrate, improve display panel production yield,
Display effect and reliability evaluation, while not will increase display panel making technology difficulty also.
Detailed description of the invention
Fig. 1 is the bad schematic diagram of Crosstalk caused by existing transistor drain current；
Fig. 2 is the existing residual sand picture of transistor active layer channel ITO；
Fig. 3 is existing transistor active layer channel picture；
Fig. 4 is that existing array substrate prepares the schematic structural cross-sectional view to form grid；
Fig. 5 is that existing array substrate prepares the schematic structural cross-sectional view to form active layer；
Fig. 6 is that existing array substrate prepares to form n+a-Si layers of schematic structural cross-sectional view；
Fig. 7 is that existing array substrate prepares the schematic structural cross-sectional view to form pixel electrode；
Fig. 8 is that existing array substrate prepares the schematic structural cross-sectional view to form source-drain electrode figure；
Fig. 9 is that existing array substrate prepares the schematic structural cross-sectional view to form passivation layer；
Figure 10 is that existing array substrate prepares the schematic structural cross-sectional view to form common electrode layer；
Figure 11 is the schematic structural cross-sectional view of transistor in the embodiment of the present invention；
Figure 12 is the schematic structural cross-sectional view that preparation forms transistor gate in Figure 11；
Figure 13 is the schematic structural cross-sectional view that preparation forms transistor active layer in Figure 11；
Figure 14 is the schematic structural cross-sectional view that preparation forms transistor protection layer in Figure 11；
Figure 15 is the schematic structural cross-sectional view that preparation forms the first via hole in transistor protection layer in Figure 11；
Figure 16 is the schematic structural cross-sectional view that preparation forms transistor ohmic contact layer and source electrode, drain electrode in Figure 11；
Figure 17 is the schematic structural cross-sectional view of array substrate in the embodiment of the present invention.
Wherein appended drawing reference are as follows: 10, glass substrate；11, grid；12, gate insulation layer；13, active layer；14, n+a-Si layers；
15, pixel electrode；16, source-drain electrode figure；17, passivation layer；18, common electrode layer；19, TFT carries on the back channel；20, substrate；21, Europe
Nurse contact layer；22, source electrode, 23, drain electrode；24, protective layer；25, active layer part；32, the first via hole；51, public electrode；53,
Grid insulating layer through hole；55, passivation layer via hole；56, common pattern of electrodes.
Specific embodiment
Technical solution in order to enable those skilled in the art to better understand the present invention, with reference to the accompanying drawing and specific embodiment party
Formula further retouches a kind of transistor of the present invention and preparation method thereof, array substrate and preparation method thereof and display panel work in detail
It states.
Existing array substrate is with HADS (High-Advanced Dimension Switch, high aperture and advanced super
Tie up field switch) for product, according to Gate (grid) → ACT (active layer) → 1st ITO (pixel electrode layer) → GI (gate insulation
Layer) → SD (source-drain electrode) → PVX (passivation layer) → 2TO (common electrode layer) 7Mask process flow prepares to be formed, such as Fig. 4-10 institute
Show,
Step 1 completes grid 11 first on the glass substrate 10 and public electrode 51 makes.Grid 11 and public electrode
51 can select the single layers such as Al, Mo, Cu, Ag, Ti or multiple layer metal to make, and thickness is about 200~600nm.
Step 2, on the basis of above-mentioned array substrate, deposition gate insulation layer 12 is covered on grid 11 and public electrode 51.
Redeposited a-Si active layer 13, n+a-Si layer 14, and complete the production of silicon island figure above TFT pipe grid.Gate insulation layer 12
SiN can be selectedx、SiO2、SiNOxEqual single layers or combination film layer, thickness is about 300~450nm；Active layer 13 selects a-Si half
Conductor material, thickness are about 150~300nm；N+a-Si layer 14 is realized by doping trivalent nitrogen, is mainly used to realize SD gold
Belong to the Ohmic contact with a-Si, reduces contact resistance, thickness is about 10~60nm.
Step 3, after the completion of above-mentioned steps two, using Sputter sputtering method pixel deposition electrode film layer and complete picture
The production of plain 15 figure of electrode, general to select transparent ITO material as pixel electrode 15, thickness is about 30~120nm.
Step 4 after the completion of above-mentioned steps three, completes the production of peripheral circuit grid insulating layer through hole 53.
Step 5, after the completion of above-mentioned steps four, the method elder generation sedimentary origin drain metal layer sputtered using Sputter, then
SD layers of gluing, exposure, development, wet etching process formation source-drain electrode figure 16 and common pattern of electrodes 56 are completed, then carries out n+
A-Si etching is clean by the n+a-Si etching at channel and ensures that remaining certain thickness a-Si retains, and completes after n+a-Si etching
TFT carries on the back the formation of channel 19, is stripped clean the PR glue covered on SD metal finally by removing medical fluid；Source-drain electrode figure 16 and public affairs
Common electrode figure 56 can select the single layers such as Al, Mo, Cu, Ag, Ti or multiple layer metal to make, and thickness is about 200~600nm.
Step 6 on the basis of above-mentioned array substrate, then successively completes the system of passivation layer 17 deposition and passivation layer via hole 55
Make and common electrode layer deposits and 18 graphic making of common electrode layer；Passivation layer 17 can select SiNx、SiO2、SiNOxEqual single layers
Or combination film layer, thickness is about 250~800nm；Common electrode layer 18 generally selects transparent ITO material, and thickness is about 30~
120nm。
After the completion of active layer process, pixel electrode layer process need to be carried out, since ITO material easily crystallizes, 1st ITO etching
After be easy have residual at TFT channel, remaining ITO can to TFT channel generate pollution；In addition, according to HADS 7Mask technique
Process, before the progress of SD layer process, the time is longer in the exposed air of a-Si, it may appear that the surface a-Si is oxidized or film quality is abnormal
Problem；ITO residual and Si film matter are abnormal at the TFT channel of above-mentioned generation, will lead to TFT pipe leakage current increase and
The homogeneity and bad stability of TFT characteristic.TFT leakage current increases, property uniformity is deteriorated and deteriorates, and can not only reduce product
Production yield, also result in product final display effect be deteriorated and the bad problem of reliability.
In order to solve the above problem existing for transistor in existing array substrate, the present embodiment provides a kind of transistors, such as
Shown in Figure 11, including substrate 20, grid 11, the gate insulation layer 12, active layer 13, ohmic contact layer being successively arranged far from substrate 20
21, source electrode 22 and drain electrode 23, source electrode 22 and drain electrode 23 are divided into the opposite end of active layer 13, and ohmic contact layer 21 is correspondingly arranged
In 23 regions of source electrode 22 and drain electrode, transistor further includes protective layer 24, and the setting of protective layer 24 connects in active layer 13 with ohm
Between contact layer 21, protective layer 24 can be protected being formed in preparation process to the active layer part 25 being located between source electrode 22 and drain electrode 23
Shield.
By the way that protective layer 24 is arranged between active layer 13 and ohmic contact layer 21, keep ohmic contact layer 21 complete in etching
Active layer part 25 between Quan Buyu source electrode 22 and drain electrode 23 contacts, and etches so as to avoid ohmic contact layer 21 to transistor
Ion bombardment source electrode 22 and leakage when active layer part 25 between source electrode 22 and drain electrode 23 causes damage, ohmic contact layer 21 to etch
Metal atom contamination active layer part 25 in active layer part 25,25 caliper uniformity of active layer part are fallen after 23 side wall of pole
Difference etc. leads to that leakage current is bigger than normal, problem of transistor characteristic homogeneity difference.
In the present embodiment, active layer 13 uses amorphous silicon material, and ohmic contact layer 21 uses the amorphous silicon material of n-type doping
Material, protective layer 24 use inorganic insulating material.Wherein, ohmic contact layer 21 realizes n-type doping by doping trivalent nitrogen.It protects
Sheath 24 includes a sub- film layer, and sub- film layer uses SiNx、SiO2Or SiNOx.Ohmic contact layer 21 can reduce source electrode 22 and leakage
Contact resistance between pole 23 and active layer 13.
It should be noted that protective layer 24 also may include multiple sub- film layers, multiple sub- film layers are stacked on top of each other.
Preferably, the thickness range of protective layer 24 is 50~200nm.The protective layer 24 of the thickness range is in array substrate
The active layer part 25 between above-mentioned protection source electrode 22 and drain electrode 23 can be played the role of in preparation process.
In the present embodiment, source electrode 22 and drain electrode 23 use conductive metal material, such as Al, Mo, Cu, Ag, Ti metallic conduction
Material.Active layer 13 uses transparent conductive material, such as ITO material.
Above structure based on transistor, the present embodiment also provide a kind of preparation method of transistor, are included in substrate
Upper successively preparation forms grid, gate insulation layer, active layer, ohmic contact layer, source electrode and drain electrode, after preparation forms active layer
And before preparation forms ohmic contact layer further include: preparation forms protective layer.
The specific preparation process of transistor in the present embodiment are as follows: as shown in figs. 12-16,
Step 1 is completed grid 11 on the substrate 20 first and is made.Grid 11 can select Al, Mo, Cu, Ag, Ti etc. single
Layer or multiple layer metal production, thickness is about 200~600nm.
Step 2, on the basis of above-mentioned transistor arrangement, deposition gate insulation layer 12 is covered on grid 11, redeposited active
Layer 13, and complete the production of silicon island figure above TFT pipe grid.Gate insulation layer 12 can select SiNx、SiO2、SiNOxDeng single
A or multiple film layer combinations, thickness is about 300~450nm；Active layer 13 selects a-Si semiconductor material, and thickness is about 150~
300nm。
Step 3 after the completion of step 2, first with the method for PECVD, deposits a protective layer 24 to protect source electrode and leakage
Active layer part 25 between pole；Protective layer 24 can select SiNx、SiO2、SiNOxIt is combined etc. single or multiple film layers, thickness
About 50~200nm.
Step 4 after the completion of step 3, then completes to connect the first via hole 32 in the protective layer 24 of source-drain electrode on the silicon island TFT
Production.
Step 5, first with the method for PECVD, deposits n+a-Si film layer on the basis of above-mentioned transistor arrangement, then sharp
The method sedimentary origin drain electrode layer metal sputtered with Sputter.Then source-drain electrode layer metal gluing, exposure, development, wet process quarter are completed
It loses process and forms the figure of source electrode 22 and drain electrode 23, then carry out n+a-Si film layer etching for source electrode 22 and drain electrode 23 with exterior domain
N+a-Si film layer etching is clean, forms the figure of ohmic contact layer 21, will be on source electrode 22 and drain electrode 23 finally by removing medical fluid
The PR glue of covering is stripped clean, the equal protected seam in active layer part 25 in above-mentioned entire processing procedure, between source electrode 22 and drain electrode 23
24 protections.Ohmic contact layer 21 is realized by doping trivalent nitrogen, is mainly used to realize source electrode 22 and drain electrode 23 and active layer
13 Ohmic contact reduces contact resistance, and thickness is about 10~60nm；Source electrode 22 and drain electrode 23 can select Al, Mo, Cu, Ag,
The single layers such as Ti or multiple layer metal production, thickness is about 200~600nm.
The present embodiment the utility model has the advantages that transistor provided by the present embodiment, by active layer and ohmic contact layer it
Between protective layer is set, contact ohmic contact layer active layer part completely not between source electrode and drain electrode in etching, thus
It avoids ohmic contact layer etching and causes damage, ohmic contact layer to etch the active layer part between transistor source and drain electrode
When ion bombardment source electrode and drain electrode side wall after fall in metal atom contamination active layer part, the active layer part of active layer part
Caliper uniformity difference etc. leads to that leakage current is bigger than normal, problem of transistor characteristic homogeneity difference.
Transistor arrangement in based on the above embodiment, the embodiment of the present invention also provide a kind of array substrate, such as Figure 17 institute
Show, including the transistor in above-described embodiment.
In the present embodiment, array substrate further includes pixel electrode 15, and pixel electrode 15 connects the drain electrode 23 of transistor, pixel
Electrode 15 is set on the protective layer 24 of transistor.
Protective layer 24 be set using in preparation formed the conductive film layer of pixel electrode 15 in etching process completely not with
Active layer part 25 directly contacts, so as to avoid residual leads to transistor at active layer part 25 when conductive film layer etching
The problem that leakage current is bigger than normal and its property uniformity is poor；In addition, product is shown for narrow frame, due to being used to form and protective layer
The mask plate of the identical film layer of 24 figures is ready-made, so the setting of protective layer 24 increases exposure mask without additional in the present embodiment
Process, so that the control difficulty of array substrate making technology will not be increased.
In the present embodiment, array substrate further includes passivation layer 17 and common electrode layer 18, passivation layer 17 and common electrode layer
18 are sequentially stacked above transistor.
Array substrate in the present embodiment be HADS (High-Advanced Dimension Switch, high aperture and
Advanced super dimension field switch) mode array substrate.
It should be noted that the array substrate in the present embodiment may be TN (Twisted Nematic, twisted-nematic)
The array substrate of mode or ADS (Advanced Dimension Switch surpasses dimension field switch) mode, details are not described herein again.
Above structure based on array substrate, the present embodiment also provide a kind of preparation method of array substrate, including shape
At transistor.
In the present embodiment, the protective layer of transistor forms pixel after preparation forms the active layer of transistor and in preparation
It prepares to be formed before electrode.Then the method that pixel electrode utilizes Sputter sputtering, pixel deposition electrode layer use composition work
The production of skill completion pixel electrode figure.Pixel electrode generally selects transparent ITO material, and thickness is about 30~120nm.Such energy
It is used in preparation and forms the conductive film layer of pixel electrode and do not contacted directly with active layer part completely in etching process, to keep away
Residual leads to that transistor drain current is bigger than normal and its property uniformity is poor at active layer part when having exempted from conductive film layer etching
Problem；In addition, showing product for narrow frame, the mask plate due to being used to form film layer identical with protection layer pattern is ready-made
, so the setting of protective layer increases process masks without additional in the present embodiment, to will not increase array substrate processing procedure work
The control difficulty of skill.
In addition, in the present embodiment the preparation method of array substrate further include on transistor preparation form passivation layer and public
Electrode layer.Specific preparation process are as follows: passivation film deposition and passivation layer figure are successively completed in the substrate for completing transistor preparation
The production of shape, the production of public electrode film layer deposition and public electrode layer pattern；Passivation layer can select SiNx、SiO2、SiNOx
It is combined etc. single or multiple film layers, thickness is about 250~800nm；Common electrode layer generally selects transparent ITO material, and thickness is about
For 30~120nm.The preparation process of passivation layer and common electrode layer is the patterning processes of comparative maturity, and which is not described herein again.
Array substrate provided in the present embodiment can be avoided ohmic contact layer etching by using above-mentioned transistor
Ion bombardment source electrode and drain electrode when causing damage, ohmic contact layer etching to the active layer part between transistor source and drain electrode
The metal atom contamination active layer part in active layer part, active layer segment thickness homogeneity difference etc. are fallen after side wall to be caused to leak
Electric current is bigger than normal, transistor characteristic homogeneity difference problem；It it can also be used in preparation simultaneously forms the conductive film layer of pixel electrode and exist
It is not contacted directly with active layer part completely in etching process, when being etched so as to avoid the conductive film layer at active layer part
Residual leads to the problem that transistor drain current is bigger than normal and its property uniformity is poor, improves the production yield of the array substrate, shows
Show effect and reliability evaluation.
The embodiment of the present invention also provides a kind of display panel, including the array substrate in above-described embodiment.
By using the array substrate in above-described embodiment, the production yield, display effect and letter of display panel are improved
Rely property evaluation, while not will increase display panel making technology difficulty also.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses
Mode, however the present invention is not limited thereto.For those skilled in the art, essence of the invention is not being departed from
In the case where mind and essence, various changes and modifications can be made therein, these variations and modifications are also considered as protection scope of the present invention.
Claims (10)
1. a kind of transistor, including substrate, grid, gate insulation layer, active layer, Ohmic contact successively far from substrate setting
Layer, source electrode and drain electrode, the source electrode and described drain are divided into the opposite end of the active layer, and the ohmic contact layer is corresponding
It is set to the source electrode and the drain electrode region, which is characterized in that the transistor further includes protective layer, the protective layer
Be arranged between the active layer and the ohmic contact layer, the protective layer can in preparation process to be located at the source electrode and
The active layer part between the drain electrode forms protection.
2. transistor according to claim 1, which is characterized in that the active layer uses amorphous silicon material, described ohm
Contact layer uses the amorphous silicon material of n-type doping, and the protective layer uses inorganic insulating material.
3. transistor according to claim 2, which is characterized in that the protective layer includes one or more sub- film layers, more
A sub- film layer is stacked on top of each other.
4. transistor according to claim 2, which is characterized in that the thickness range of the protective layer is 50~200nm.
5. a kind of preparation method of the transistor as described in claim 1-4 any one, including shape is successively prepared in substrate
At grid, gate insulation layer, active layer, ohmic contact layer, source electrode and drain electrode, which is characterized in that form the active layer in preparation
Later and before preparation forms the ohmic contact layer further include: preparation forms protective layer.
6. a kind of array substrate, which is characterized in that including transistor described in claim 1-4 any one.
7. array substrate according to claim 6, which is characterized in that it further include pixel electrode, the pixel electrode connection
The drain electrode of the transistor, the pixel electrode are set on the protective layer of the transistor.
8. a kind of preparation method of array substrate as claimed in claims 6 or 7, which is characterized in that including forming transistor.
9. the preparation method of array substrate according to claim 8, which is characterized in that the protective layer of the transistor is being made
It prepares after the standby active layer for forming the transistor and before preparation forms pixel electrode and is formed.
10. a kind of display panel, which is characterized in that including array substrate described in claim 6-7 any one.
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