CN107316875A - Preparation method, array base palte and the liquid crystal panel of array base palte - Google Patents
Preparation method, array base palte and the liquid crystal panel of array base palte Download PDFInfo
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- CN107316875A CN107316875A CN201710697585.0A CN201710697585A CN107316875A CN 107316875 A CN107316875 A CN 107316875A CN 201710697585 A CN201710697585 A CN 201710697585A CN 107316875 A CN107316875 A CN 107316875A
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- base palte
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
Abstract
The invention discloses a kind of preparation method of array base palte, including：The first metal layer is deposited on substrate, the grid and public electrode of the first mask patterning the first metal layer formation mutually insulated is utilized；Gate insulator is deposited on the substrate, and the gate insulator covers the grid and the public electrode；Semiconductor layer and second metal layer are sequentially depositing on the gate insulator, pattern the semiconductor layer formation active layer, using the second mask patterning second metal layer formation source electrode, drain electrode and pixel electrode, the upright projection of the pixel electrode on the substrate and the public electrode are non-intersect.The present invention also disclosed a kind of array base palte and liquid crystal panel.The light shield step of exposure for independently forming public electrode and pixel electrode is eliminated, so as to reduce a light shield step of exposure, the manufacturing process of the array base palte of IPS mode liquid crystal panels is simplified, so as to reduce the cost of manufacture of array base palte and liquid crystal display.
Description
Technical field
The present invention relates to display technology field, more particularly, to a kind of preparation method of array base palte, array base palte and liquid
Crystal panel.
Background technology
With the development of Display Technique, Thin Film Transistor-LCD (Thin Film Transistor Liquid
Crystal Display, TFT-LCD) etc. flat display apparatus because with high image quality, power saving, fuselage is thin and has a wide range of application
Advantage, and it is widely used in mobile phone, TV, personal digital assistant, digital camera, notebook computer, desktop computer etc.
Various consumption electronic products, as the main flow in display device.Liquid crystal display device on existing market is largely backlight
Type liquid crystal display, it includes liquid crystal mesogenses panel and backlight module (backlight module).On current mainstream market
TFT-LCD, for the drive pattern of liquid crystal, can be divided into three types, be respectively twisted-nematic (Twisted Nematic,
TN) or super twisted nematic (Super Twisted Nematic, STN) type, (In-Plane Switching, IPS) is changed in face
Type and vertical orientation (Vertical Alignment, VA) type.Wherein IPS patterns are to utilize the electric field almost parallel with real estate
Drive pattern of the liquid crystal molecule along substrate rotation in surface to respond, due to excellent viewing angle characteristic and pressing characteristic by
Extensive concern and application.
In the prior art, the complex manufacturing process of the array base palte of IPS mode liquid crystals panel, improves the system of array base palte
Make cost, cause the production cost of the liquid crystal display of IPS patterns higher.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method of array base palte, array base palte and liquid crystal surface
Plate, the problem of production cost to solve the liquid crystal display of IPS patterns in the prior art is higher.
In order to solve the above technical problems, the present invention provides a kind of preparation method of array base palte, including：
The first metal layer is deposited on substrate, the first mask patterning the first metal layer formation mutually insulated is utilized
Grid and public electrode；
Gate insulator is deposited on the substrate, and the gate insulator covers the grid and the public electrode；
Semiconductor layer and second metal layer are sequentially depositing on the gate insulator, the semiconductor layer is patterned and is formed
Active layer, using the second mask patterning second metal layer formation source electrode, drain electrode and pixel electrode, the pixel electrode exists
Upright projection and the public electrode on the substrate is non-intersect.
In a kind of embodiment, after the source electrode, the drain electrode and the pixel electrode is formed, the array base palte
Preparation method also includes：
In the surface deposit passivation layer of the source electrode, the drain electrode and the pixel electrode, and utilize the 3rd mask pattern
Change the passivation layer.
In a kind of embodiment, the process that the patterning semiconductor layer forms the active layer includes：
The active layer is formed using the 4th mask patterning semiconductor layer.
In a kind of embodiment, second light shield is many gray-level masks, and patterning the semiconductor layer and being formed described has
The process of active layer includes：
The second metal layer is patterned using second light shield simultaneously and the semiconductor layer forms the source electrode, institute
State drain electrode, the pixel electrode and the active layer.
In a kind of embodiment, the public electrode is formed using the described first mask patterning the first metal layer
Meanwhile, by the described first mask patterning the first metal layer formation common signal line, the common signal line with it is described
Public electrode is electrically connected.
The present invention also provides a kind of array base palte, the array base palte include substrate, the first metal layer, gate insulator,
Active layer and second metal layer, the first metal layer are located at the substrate surface, and the first metal layer includes mutually insulated
Grid and public electrode, the gate insulator is located at the real estate to the side of the first metal layer and covers described
Grid and the public electrode, the active layer and the second metal layer are stacked gradually on the gate insulator, described
Second metal layer includes source electrode, drain electrode and pixel electrode, and the source electrode and the drain electrode pass through the active layer one-way conduction, institute
State the upright projection of pixel electrode on the substrate and the public electrode is non-intersect.
In a kind of embodiment, the pixel electrode also includes passivation layer, and the passivation layer is stacked in described second
On metal level.
In a kind of embodiment, the first metal layer also includes common signal line, the common signal line and the public affairs
Common electrode is electrically connected.
In a kind of embodiment, the quantity of the pixel electrode be it is multiple, the quantity of the public electrode be it is multiple, it is described
The upright projection of pixel electrode on the substrate is staggered with the public electrode.
The present invention also provides a kind of liquid crystal panel, and the liquid crystal panel includes color membrane substrates, liquid crystal layer and any of the above one
Array base palte described in, the liquid crystal layer is located between the color membrane substrates and the array base palte, and the liquid crystal panel leads to
The voltage difference crossed between the pixel electrode and the public electrode controls the liquid crystal molecule of the liquid crystal layer to rotate, and passes through institute
State color membrane substrates display image.
Beneficial effects of the present invention are as follows：Public electrode is formed with grid in a light shield exposure, will form public affairs
The processing procedure of common electrode is combined with the processing procedure of grid, pixel electrode and source electrode and the formation in a light shield exposure that drains, will
The processing procedure for forming pixel electrode is combined with source electrode and the processing procedure of drain electrode, eliminates the light for independently forming public electrode and pixel electrode
Cover step of exposure, so as to reduce a light shield step of exposure, simplifies the making of the array base palte of IPS mode liquid crystal panels
Journey, so as to reduce the cost of manufacture of array base palte and liquid crystal display.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other substantially modes of texturing are obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention.
Fig. 2 is the step S101 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 3 is the step S102 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 4 and Fig. 5 is the step S103 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 6 is the step S104 of the preparation method of array base palte provided in an embodiment of the present invention schematic diagram.
Fig. 7 is the sectional view of array base palte provided in an embodiment of the present invention.
Fig. 8 is the top view of array base palte provided in an embodiment of the present invention.
Fig. 9 is the schematic diagram of liquid crystal panel provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiment of the present invention provides a kind of preparation method of array base palte, the array base for making liquid crystal display
The array base palte of plate, the especially liquid crystal display of IPS patterns.Specifically, array base palte includes thin film transistor (TFT) (Thin-
Film transistor, TFT), pixel electrode, public electrode, common signal line, data wire, the element such as scan line, wherein, sweep
The grid that line is electrically connected to thin film transistor (TFT) is retouched, data wire and pixel electrode are respectively electrically connected to source electrode or the leakage of thin film transistor (TFT)
One of pole, scan line provides connection or off-state of the scanning signal control source electrode with drain electrode, when source electrode is connected with drain electrode, number
The voltage swing that data-signal controls pixel electrode is transmitted according to line, common signal line electrical connection public electrode simultaneously controls public electrode
Voltage swing, by controlling the voltage difference of pixel electrode and public electrode to control liquid crystal molecule to rotate, so that liquid crystal panel is aobvious
The content of diagram picture.
Referring to Fig. 1, the preparation method of array base palte provided in an embodiment of the present invention includes：
S101, on the substrate 10 deposition the first metal layer 20, utilize the patterned first metal of the first light shield 901 layer 20 to be formed
The grid 22 of mutually insulated and public electrode 24.
Referring to Fig. 1, the first light shield 901 includes expose corresponding with the grid 22 and the pattern of public electrode 24 for needing to be formed
Light area, ultraviolet light or other light sources irradiate from the first light shield 901 away from a lateral direction of substrate 10 of substrate 10, and pass through exposure
Area forms the grid 22 and public electrode 24 of specific pattern after being exposed to the first metal layer 20.In a kind of embodiment, the first gold medal
Belonging to layer 20 can be by physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) method film forming on substrate 10.This
In embodiment, substrate 10 is made up of transparent materials such as glass substrate or plastic bases.
In a kind of embodiment, the first metal layer 20 can be the metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or aoxidize
Indium tin (ITO), indium zinc oxide (IZO), the zinc oxide (AZO) of aluminium doping, indium gallium zinc oxide (IGZO), zinc-tin oxide (ZTO)
Deng the laminated construction of one or more multi-element metal oxide conductive materials in multi-element metal oxide conductive material, and
The thickness of one metal level 20 can be 500A~20000A.
The grid 22 that patterned first metal layer 20 is formed is used to be subsequently formed thin film transistor (TFT), patterned first metal layer
The pixel electrode 56 that 20 public electrodes 24 formed are used for being subsequently formed interacts to control liquid crystal deflection.With reference to Fig. 8, one
Plant in embodiment, public electrode 24 is strip.In a kind of embodiment, grid 22 and the mutually insulated of public electrode 24.
Public electrode 24 is formed with grid 22 in a light shield exposure, will form the processing procedure and grid of public electrode 24
The processing procedure of pole 22 is combined, and eliminates the light shield step of exposure for independently forming public electrode 24, so as to reduce a light shield exposure
Step, simplifies the manufacturing process of the array base palte of IPS mode liquid crystal panels, so as to reduce array base palte and liquid crystal display
Cost of manufacture.
With reference to Fig. 8, in a kind of embodiment, public electrode is formed using the patterned first metal of the first light shield 901 layer 20
While 24, common signal line 26 is formed by the first light shield 901 patterned first metal layer 20, common signal line 26 with it is public
Electrode 24 is electrically connected.Specifically, the first light shield 901 includes exposure region pattern corresponding with common signal line 26, so that in exposure
While public electrode 24 is formed with grid 22, common signal line 26 is also synchronous to be formed.Common signal line 26 is public for controlling
The common electric voltage of electrode 24, so that the pixel voltage formation voltage difference with pixel electrode 56.Common signal line 26, public electrode 24
And grid 22 is formed in a light shield exposure, simplifies the manufacturing process of the array base palte of IPS mode liquid crystal panels, so that
Reduce the cost of manufacture of array base palte and liquid crystal display.
In a kind of embodiment, while forming public electrode 24 using the patterned first metal of the first light shield 901 layer 20,
Scan line 28 is formed by the patterned first metal of the first light shield 901 layer 20, scan line 28 is electrically connected with grid 22.Specifically,
First light shield 901 includes exposure region pattern corresponding with scan line 28, so as to form public electrode 24 and grid 22 in exposure
Meanwhile, scan line 28 is also synchronous to be formed.Scan line 28 exports the voltage of grid 22 to grid 22, so as to control the company of thin film transistor (TFT)
On-off open state.Scan line 28, public electrode 24 and grid 22 are formed in a light shield exposure, simplify IPS patterns
The manufacturing process of the array base palte of liquid crystal panel, so as to reduce the cost of manufacture of array base palte and liquid crystal display.
S102, on the substrate 10 deposition gate insulator 30, the covering grid 22 of gate insulator 30 and public electrode 24.
Referring to Fig. 3, gate insulator 30 is by grid 22, public electrode 24 and is subsequently formed on gate insulator 30
Active layer mutually completely cuts off.Gate insulator 30 can be one kind or many in the insulating dielectric materials such as SiOx, SiNx, HfO2, Al2O3
The laminated construction of insulating dielectric materials is planted, the thickness of gate insulator 30 can be 100A~10000A, and can pass through chemical gas
Mutually deposit (Chemical Vapor Deposition, CVD) method film forming.In a kind of embodiment, gate insulator 30 is
SiNx and SiOx laminated construction, SiNx thickness is 100nm, and SiOx thickness is 300nm, and by being increased by plasma
Vapour deposition process (Plasma Enhanced Chemical Vapor Deposition, PECVD) method film forming of extensive chemical.
S103, semiconductor layer and second metal layer 50, patterned semiconductor layer shape are sequentially depositing on gate insulator 30
Into active layer 40, using the second light shield 902 patterning formation of second metal layer 50 source electrode 52, drain 54 and pixel electrode 56, as
Plain electrode 56 upright projection on the substrate 10 and public electrode 24 are non-intersect.
In the present embodiment, the electrical connection source electrode 52 of pixel electrode 56 or drain electrode 54.In a kind of embodiment, step S103 includes
Following two sub-steps：
1st, the deposited semiconductor layer on gate insulator 30, forms active using the patterned semiconductor layer of the 4th light shield 904
Layer 40.
With reference to Fig. 4, specifically, the 4th light shield 904 includes exposure region corresponding with the pattern of the active layer 40 of needs formation,
Ultraviolet light or other light sources irradiate from the 4th light shield 904 away from a lateral direction of substrate 10 of substrate 10, and pass through exposure region pair
The active layer 40 of specific pattern is formed after semiconductor layer exposure.
2nd, the depositing second metal layer 50 on active layer 40, is formed using the second light shield 902 patterning second metal layer 50
Source electrode 52, drain electrode 54 and pixel electrode 56.
With reference to Fig. 5, specifically, the second light shield 902 includes and the source electrode 52 for needing to be formed, drain electrode 54 and pixel electrode 56
The corresponding exposure region of pattern, ultraviolet light or other light sources shine from the second light shield 902 away from a lateral direction of substrate 10 of substrate 10
Penetrate, and pass through source electrode 52, drain electrode 54 and pixel electrode 56 of the exposure region to formation specific pattern after the exposure of second metal layer 50.
Pixel electrode 56 is formed with source electrode 52 and drain electrode 54 in a light shield exposure, will form pixel electrode 56
Processing procedure is combined with the processing procedure of source electrode 52 and drain electrode 54, the light shield step of exposure for independently forming pixel electrode 56 is eliminated, so as to subtract
A light shield step of exposure is lacked, the manufacturing process of the array base palte of IPS mode liquid crystal panels has been simplified, so as to reduce array
The cost of manufacture of substrate and liquid crystal display.
In another embodiment, active layer 40, source electrode 52, drain electrode 54 and pixel electrode 56 are in a light shield exposure process
It is middle to be formed.Specifically, the second light shield 902 is many gray-level masks, exposure region and half-penetration type of many gray-level masks including full-transparency type
Exposure region, the light source such as ultraviolet light is through the exposure region of full-transparency type and the exposure region of half-penetration type to base material (semiconductor layer and the second gold medal
Belong to layer 50) exposure effect it is different, so as to pattern second metal layer 50 simultaneously using the second light shield 902 and semiconductor layer is formed
Source electrode 52, drain electrode 54, pixel electrode 56 and active layer 40.
Active layer 40, source electrode 52, drain electrode 54 and pixel electrode 56 are formed in a light shield exposure process, are eliminated individually
The light shield step of exposure of active layer 40 is formed, the number of times of light shield exposure is further reduced, simplifies IPS mode liquid crystal panels
The manufacturing process of array base palte, so as to reduce the cost of manufacture of array base palte and liquid crystal display.
In the present embodiment, semiconductor layer is oxide semiconductor, specifically, active layer 40 can be indium gallium zinc oxide
(IGZO), zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGTO), zinc-tin oxide (ZTO) of aluminium doping etc. are saturating
Bright oxide semiconductor material.The thickness of semiconductor layer can be 300A~1000A.In a kind of embodiment, semiconductor layer material
For IGZO, thickness is 50nm, by magnetically controlled sputter method film forming.
In the present embodiment, second metal layer 50 can be the metal materials such as Cu, Mo, Ti, Al, Cr, Ag, Au, or tin indium oxide
(ITO), indium zinc oxide (IZO), zinc oxide (AZO), indium gallium zinc oxide (IGZO), the zinc-tin oxide (ZTO) of aluminium doping etc. are more
The laminated construction of one or more multi-element metal oxide conductive materials in first metal conductive oxide material, and the second gold medal
The thickness for belonging to layer 50 can be 500A~20000A.In a kind of embodiment, the material of second metal layer 50 is Cu, and thickness is 300nm,
By magnetically controlled sputter method film forming.
With reference to Fig. 8, in the present embodiment, the second light shield 902 patterning second metal layer 50 formation source electrode 52 and drain electrode are utilized
While 54, the formation data wire 58 of second metal layer 50, data wire 58 and source electrode 52 or drain electrode are patterned by the second light shield 902
54 electrical connections.Specifically, the second light shield 902 includes exposure region pattern corresponding with data wire 58, so as to form source electrode in exposure
52 and while drain electrode 54, data wire 58 is also synchronous to be formed.Data wire 58 to source electrode 52 or drain electrode 54 output data voltages so that
Control the pixel voltage size of pixel electrode 56.Data wire 58, source electrode 52 and drain electrode 54 are formed in a light shield exposure, letter
The manufacturing process of the array base palte of IPS mode liquid crystal panels is changed, so as to reduce the making of array base palte and liquid crystal display
Cost.
S104, the surface deposit passivation layer 60 in source electrode 52, drain electrode 54 and pixel electrode 56, and utilize the 3rd light shield 903
Patterned passivation layer 60.
Referring to Fig. 6, the 3rd light shield 903 includes exposure region corresponding with the pattern of the passivation layer 60 of needs formation, it is ultraviolet
Light or other light sources from the 3rd light shield 903 away from substrate 10 the lateral direction of substrate 10 irradiation, and after being exposed by exposure region
Form the passivation layer 60 of specific pattern.Passivation layer 60 is used to protect source electrode 52, drain electrode 54 and pixel electrode 56, it is to avoid metal material
Source electrode 52, drain electrode 54 and pixel electrode 56 aoxidize.In a kind of embodiment, passivation layer 60 is provided with perforate, for array base
The drive circuit of plate and source electrode 52, drain electrode 54 or the electrical connection of pixel electrode 56.
In the present embodiment, passivation layer 60 can be for the one or more in the insulating materials such as SiOx, SiNx, HfO2, Al2O3 absolutely
The laminated construction of edge material, the thickness of passivation layer 60 can be 1000A~10000A, and can pass through CVD method film forming.A kind of embodiment party
In formula, gate insulator 30 is SiOx and SiNx laminated construction, and SiOx thickness is 300nm, and SiNx thickness is 100nm, grid
Pole insulating barrier 30 is by PECVD method film forming.
Public electrode 24 is formed with grid 22 in a light shield exposure, will form the processing procedure and grid of public electrode 24
The processing procedure of pole 22 is combined, and pixel electrode 56 is formed with source electrode 52 and drain electrode 54 in a light shield exposure, will form pixel
The processing procedure of electrode 56 is combined with the processing procedure of source electrode 52 and drain electrode 54, is eliminated and is independently formed public electrode 24 and pixel electrode 56
Light shield step of exposure, so as to reduce a light shield step of exposure, simplifies the making of the array base palte of IPS mode liquid crystal panels
Process, so as to reduce the cost of manufacture of array base palte and liquid crystal display.
Fig. 7 and Fig. 8 are referred to, the embodiment of the present invention also provides a kind of array base palte 100.Array base palte 100 includes substrate
10th, the first metal layer 20, gate insulator 30, active layer 40 and second metal layer 50, the first metal layer 20 are located at the table of substrate 10
Face, grid 22 and the public electrode 24 of the first metal layer 20 including mutually insulated, gate insulator 30 is located at substrate 10 in face of the
The side of one metal level 20 simultaneously covers grid 22 and public electrode 24, and active layer 40 and second metal layer 50 are stacked gradually in grid
On insulating barrier 30, second metal layer 50 includes source electrode 52, drain electrode 54 and pixel electrode 56, and source electrode 52 and drain electrode 54 pass through active layer
40 one-way conductions, the upright projection of pixel electrode 56 on the substrate 10 and public electrode 24 are non-intersect.
In the present embodiment, pixel electrode 56 also includes passivation layer 60, and passivation layer 60 is stacked in second metal layer 50.
Passivation layer 60 is used to protect source electrode 52, drain electrode 54 and pixel electrode 56, it is to avoid source electrode 52, drain electrode 54 and the pixel electricity of metal material
Pole 56 is aoxidized.
In the present embodiment, the first metal layer 20 also includes common signal line 26, common signal line 26 and the electricity of public electrode 24
Connection.Public electrode 24 is used to interact to control liquid crystal deflection with pixel electrode 56.In a kind of embodiment, public electrode
24 be strip.
In the present embodiment, the first metal layer 20 also includes scan line 28, and scan line 28 is electrically connected with grid 22, scan line 28
The voltage of grid 22 is exported to grid 22, so as to control connection or the off-state of thin film transistor (TFT).
In the present embodiment, second metal layer 50 also includes data wire 58, and data wire 58 is electrically connected with source electrode 52 or drain electrode 54,
Data wire 58 is to 54 output data voltages of source electrode 52 or drain electrode, so as to control the pixel voltage size of pixel electrode 56.
In a kind of embodiment, the quantity of pixel electrode 56 is multiple, and the quantity of public electrode 24 is multiple, pixel electrode
56 upright projection on the substrate 10 is staggered with public electrode 24, so that in adjacent pixel electrode 56 and public electrode 24
Between formed electric field controls liquid crystal molecule rotation.
Public electrode 24 is formed with grid 22 in a light shield exposure, will form the processing procedure and grid of public electrode 24
The processing procedure of pole 22 is combined, and pixel electrode 56 is formed with source electrode 52 and drain electrode 54 in a light shield exposure, will form pixel
The processing procedure of electrode 56 is combined with the processing procedure of source electrode 52 and drain electrode 54, is eliminated and is independently formed public electrode 24 and pixel electrode 56
Light shield step of exposure, so as to reduce a light shield step of exposure, simplifies the array base palte 100 of IPS mode liquid crystal panels
Manufacturing process, so as to reduce the cost of manufacture of array base palte 100 and liquid crystal display.
Referring to Fig. 9, the embodiment of the present invention also provides a kind of liquid crystal panel, liquid crystal panel includes color membrane substrates 200, liquid crystal
Layer 300 and array base palte provided in an embodiment of the present invention 100, liquid crystal layer 300 be located at color membrane substrates 200 and array base palte 100 it
Between, liquid crystal panel controls the liquid crystal molecule of liquid crystal layer 300 to rotate by the voltage difference between pixel electrode 56 and public electrode 24,
And pass through the display image of color membrane substrates 200.
Above disclosed is only several preferred embodiments of the invention, can not limit the power of the present invention with this certainly
Sharp scope, one of ordinary skill in the art will appreciate that all or part of flow of above-described embodiment is realized, and according to present invention power
Profit requires made equivalent variations, still falls within and invents covered scope.
Claims (10)
1. a kind of preparation method of array base palte, it is characterised in that including：
The first metal layer is deposited on substrate, the grid of the first mask patterning the first metal layer formation mutually insulated is utilized
With public electrode；
Gate insulator is deposited on the substrate, and the gate insulator covers the grid and the public electrode；
Semiconductor layer and second metal layer are sequentially depositing on the gate insulator, the semiconductor layer is patterned and forms active
Layer, using the second mask patterning second metal layer formation source electrode, drain electrode and pixel electrode, the pixel electrode is described
Upright projection and the public electrode on substrate is non-intersect.
2. the preparation method of array base palte according to claim 1, it is characterised in that forming the source electrode, the leakage
Behind pole and the pixel electrode, the preparation method of the array base palte also includes：
In the surface deposit passivation layer of the source electrode, the drain electrode and the pixel electrode, and utilize the 3rd mask patterning institute
State passivation layer.
3. the preparation method of array base palte according to claim 2, it is characterised in that the patterning semiconductor layer is formed
The process of the active layer includes：
The active layer is formed using the 4th mask patterning semiconductor layer.
4. the preparation method of array base palte according to claim 2, it is characterised in that second light shield is many GTG light
Cover, the process that the patterning semiconductor layer forms the active layer includes：
The second metal layer is patterned using second light shield simultaneously and the semiconductor layer forms the source electrode, the leakage
Pole, the pixel electrode and the active layer.
5. the preparation method of the array base palte according to Claims 1-4 any one, it is characterised in that utilize described the
While the one mask patterning the first metal layer forms the public electrode, pass through described first mask patterning described
One metal level formation common signal line, the common signal line is electrically connected with the public electrode.
6. a kind of array base palte, it is characterised in that the array base palte includes substrate, the first metal layer, gate insulator, active
Layer and second metal layer, the first metal layer are located at the substrate surface, and the first metal layer includes the grid of mutually insulated
Pole and public electrode, the gate insulator are located at the real estate to the side of the first metal layer and cover the grid
With the public electrode, the active layer and the second metal layer are stacked gradually on the gate insulator, and described second
Metal level includes source electrode, drain electrode and pixel electrode, and the source electrode and the drain electrode pass through the active layer one-way conduction, the picture
The upright projection of plain electrode on the substrate and the public electrode are non-intersect.
7. array base palte according to claim 6, it is characterised in that the pixel electrode also includes passivation layer, described blunt
Change layer stackup to be arranged in the second metal layer.
8. array base palte according to claim 7, it is characterised in that the first metal layer also includes common signal line,
The common signal line is electrically connected with the public electrode.
9. the array base palte according to claim 6 to 8 any one, it is characterised in that the quantity of the pixel electrode is
Multiple, the quantity of the public electrode is multiple, the upright projection of the pixel electrode on the substrate and the common electrical
Pole is staggered.
10. a kind of liquid crystal panel, it is characterised in that the liquid crystal panel includes color membrane substrates, liquid crystal layer and claim 6 to 9
Array base palte described in any one, the liquid crystal layer is located between the color membrane substrates and the array base palte, the liquid crystal
Panel controls the liquid crystal molecule of the liquid crystal layer to rotate by the voltage difference between the pixel electrode and the public electrode, and
Pass through the color membrane substrates display image.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919321A (en) * | 2017-11-22 | 2018-04-17 | 深圳市华星光电半导体显示技术有限公司 | FFS type thin-film transistor array base-plates and preparation method thereof |
| CN108646487A (en) * | 2018-05-15 | 2018-10-12 | 深圳市华星光电技术有限公司 | The production method and FFS type array substrates of FFS type array substrates |
| CN108922966A (en) * | 2018-06-19 | 2018-11-30 | 信利半导体有限公司 | A kind of Organic Thin Film Transistors and preparation method thereof |
| CN109273458A (en) * | 2018-09-21 | 2019-01-25 | 惠科股份有限公司 | Array substrate and preparation method thereof and display panel |
| US10304866B1 (en) | 2017-11-22 | 2019-05-28 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | FFS type TFT array substrate and the manufacturing method thereof |
| CN110400832A (en) * | 2019-06-12 | 2019-11-01 | 北海惠科光电技术有限公司 | The preparation method and array substrate of array substrate |
| CN114326232A (en) * | 2021-12-30 | 2022-04-12 | 广州华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901839A (en) * | 2009-05-29 | 2010-12-01 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| CN102543864A (en) * | 2012-02-07 | 2012-07-04 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN102723308A (en) * | 2012-06-08 | 2012-10-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105679773A (en) * | 2016-01-29 | 2016-06-15 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
-
2017
- 2017-08-15 CN CN201710697585.0A patent/CN107316875A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901839A (en) * | 2009-05-29 | 2010-12-01 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| CN102543864A (en) * | 2012-02-07 | 2012-07-04 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN102723308A (en) * | 2012-06-08 | 2012-10-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105679773A (en) * | 2016-01-29 | 2016-06-15 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919321A (en) * | 2017-11-22 | 2018-04-17 | 深圳市华星光电半导体显示技术有限公司 | FFS type thin-film transistor array base-plates and preparation method thereof |
| US10304866B1 (en) | 2017-11-22 | 2019-05-28 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | FFS type TFT array substrate and the manufacturing method thereof |
| WO2019100495A1 (en) * | 2017-11-22 | 2019-05-31 | 深圳市华星光电半导体显示技术有限公司 | Ffs-type thin-film transistor array substrate and manufacturing method therefor |
| CN108646487A (en) * | 2018-05-15 | 2018-10-12 | 深圳市华星光电技术有限公司 | The production method and FFS type array substrates of FFS type array substrates |
| CN108646487B (en) * | 2018-05-15 | 2020-12-25 | Tcl华星光电技术有限公司 | FFS (fringe field switching) type array substrate and manufacturing method thereof |
| CN108922966A (en) * | 2018-06-19 | 2018-11-30 | 信利半导体有限公司 | A kind of Organic Thin Film Transistors and preparation method thereof |
| CN109273458A (en) * | 2018-09-21 | 2019-01-25 | 惠科股份有限公司 | Array substrate and preparation method thereof and display panel |
| WO2020056906A1 (en) * | 2018-09-21 | 2020-03-26 | 惠科股份有限公司 | Array substrate, manufacturing method therefor, and display panel |
| CN110400832A (en) * | 2019-06-12 | 2019-11-01 | 北海惠科光电技术有限公司 | The preparation method and array substrate of array substrate |
| CN114326232A (en) * | 2021-12-30 | 2022-04-12 | 广州华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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