JPH0287526A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0287526A JPH0287526A JP63238754A JP23875488A JPH0287526A JP H0287526 A JPH0287526 A JP H0287526A JP 63238754 A JP63238754 A JP 63238754A JP 23875488 A JP23875488 A JP 23875488A JP H0287526 A JPH0287526 A JP H0287526A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist
- forming
- electrode
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 31
- 239000007788 liquid Substances 0.000 claims abstract description 4
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 33
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 229910052804 chromium Inorganic materials 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract 3
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、半導体技術さらに詳しくは半導体チップの実
装技術に適用して特に有効な技術に関するものある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to semiconductor technology, and more particularly, to a technology that is particularly effective when applied to semiconductor chip mounting technology.
[従来の技術]
半導体チップをパッケージ等の基板に接合する技術の一
つに例えばCCB技術があり、このCCB技術では半導
体チップのAQ配線上に半田の突起電極を形成し、この
突起電極を介して半導体チップをパッケージ等の基板に
直接固着するようになっている。このような技術につい
ては、例えば、1984年9月24日に日経マグロウヒ
ル社から発行された「日経エレクトロニクス」第265
頁〜第294頁に記載されている。[Prior Art] One of the technologies for bonding a semiconductor chip to a substrate such as a package is the CCB technology. In this CCB technology, protruding solder electrodes are formed on the AQ wiring of the semiconductor chip, and solder is bonded through the protruding electrodes. The semiconductor chip is directly fixed to a substrate such as a package. Regarding such technology, for example, "Nikkei Electronics" No. 265, published by Nikkei McGraw-Hill on September 24, 1984,
It is described on pages 294 to 294.
第2図(A)〜(D)には上記突起電極の形成方法の一
例が示されている。その形成方法を具体的に説明すれば
次のとおりである。FIGS. 2A to 2D show an example of a method for forming the protruding electrodes. The method of forming it will be specifically explained as follows.
先ず、最終配線工程が終了した後に、AQ配線3上全面
にプラズマCVD法によって窒化シリコン膜を形成する
。その後、上記窒化シリコン膜上に被着させたホトレジ
スト膜(図示せず)をマスクにしてAQ配線3の表面の
一部が露出されるように上記窒化シリコン膜を選択的に
除去する。これによって窒化シリコン膜からなる第1の
プロテクション膜1が形成される。ここまで終了した状
態が第2図(A)に示されている。First, after the final wiring process is completed, a silicon nitride film is formed over the entire surface of the AQ wiring 3 by plasma CVD. Thereafter, using a photoresist film (not shown) deposited on the silicon nitride film as a mask, the silicon nitride film is selectively removed so that a part of the surface of the AQ wiring 3 is exposed. As a result, a first protection film 1 made of a silicon nitride film is formed. The state that has been completed up to this point is shown in FIG. 2(A).
次いで、マスクとなった上記ホトレジスト膜を除去した
後、スパッタリング法によって酸化シリコン膜を上記プ
ロテクション膜1上全面に被着させる。そして、再び、
ホトレジスト膜(図示せず)をマスクとして上記酸化シ
リコン膜を選択的に除去して第2図(B)に示すように
酸化シリコン膜からなる第2のプロテクション膜5を形
成する。Next, after removing the photoresist film serving as a mask, a silicon oxide film is deposited over the entire surface of the protection film 1 by sputtering. And again,
The silicon oxide film is selectively removed using a photoresist film (not shown) as a mask to form a second protection film 5 made of a silicon oxide film as shown in FIG. 2(B).
次に、マスクとなったホトレジスト膜を除去し、その後
全面にCr、CuおよびAuの3層からなる積層膜を形
成する。そして、その積層膜をホトエツチング技術にて
パターンニングすることによって下地電極6が形成され
る。ここまで終了した状態が第2図(C)に示されてい
る。Next, the photoresist film serving as a mask is removed, and then a laminated film consisting of three layers of Cr, Cu, and Au is formed on the entire surface. Then, the base electrode 6 is formed by patterning the laminated film using a photoetching technique. The state that has been completed up to this point is shown in FIG. 2(C).
その後、半導体ウェハ裏面に冷却用のメタライズ層を形
成する。次に、液状のホ1ヘレジス1へ膜およびドライ
フィルム状のホトレジスト膜を順次形成し、その両ホト
レジス1へ膜の突起電極形成予定領域に対応する部分を
選択的に除去して開口させ、その後Pb−8nの導体膜
を全面に形成する。その後、リフトオフ技術によって突
起電極形成予定領域に対応する部分のみ導体膜が残るよ
うに上記導体膜を選択的に除去し、さらにウエツ1−バ
ンク(熱処理)によって残りの導体膜を溶融させること
によってボール状の突起電極7を形成する。ここまで終
了した状態が第2図(D)に示されている。After that, a metallized layer for cooling is formed on the back surface of the semiconductor wafer. Next, a film and a dry film-like photoresist film are sequentially formed on the liquid photoresist 1, and the portions of the film corresponding to the regions where the protruding electrodes are to be formed are selectively removed and opened in both photoresists 1. A conductor film of Pb-8n is formed over the entire surface. Thereafter, the conductor film is selectively removed using a lift-off technique so that the conductor film remains only in the area corresponding to the area where the protruding electrodes are to be formed, and the remaining conductor film is melted by wet 1-bank (heat treatment) to form a ball. A protruding electrode 7 having a shape is formed. The state that has been completed up to this point is shown in FIG. 2(D).
[発明が解決しようとする課題]
しかしながら、上記のような方法で導体膜を形成する場
合には下記のような問題が惹起されることになる。[Problems to be Solved by the Invention] However, when a conductive film is formed by the method described above, the following problems arise.
即ち、上記方法によれば、突起電極の形成にあたって、
第1および第2のプロテクション膜1゜5の形成を行っ
ており、さらしこ下地電極6となる積層膜の選択除去と
突起室i7どなる導体j漠の選択除去とを別個の工程で
行っているため、突起電極7の形成に長時間要すること
となり、その結果。That is, according to the above method, in forming the protruding electrode,
The first and second protection films 1.5 are formed, and the selective removal of the laminated film that will become the exposed base electrode 6 and the selective removal of the conductor in the protrusion chamber (i7) are performed in separate steps. As a result, it takes a long time to form the protruding electrode 7.
半導体装置の製造ラインにおけるスループットが悪くな
ってしまうという問題があった。There has been a problem in that the throughput in the semiconductor device manufacturing line deteriorates.
また、上記技術では、下地電極6形成の後、それのエツ
チングのためのホトリソグラフィ工程や裏面メタライズ
層を形成するための熱処理工程が入るので下地電極6が
酸化され、その部分にボイドが発生し、下地電極6の半
田濡れ性が悪化するという問題があった。In addition, in the above technique, after forming the base electrode 6, a photolithography process for etching it and a heat treatment process for forming a backside metallized layer are performed, so the base electrode 6 is oxidized and voids are generated in that part. , there was a problem that the solder wettability of the base electrode 6 deteriorated.
さらに、下地電極6形成のためのエツチングの際に下地
電極6を構成するCuがエツチングされる恐れがある。Furthermore, there is a risk that Cu constituting the base electrode 6 may be etched during etching for forming the base electrode 6.
なお、プロテクション膜1,5を用いないものでは、下
地電極6のエツチングの際に下地のAQ配線3がエツチ
ングされてしまう恐れもある。Note that in the case where the protection films 1 and 5 are not used, there is a risk that the underlying AQ wiring 3 may be etched when the underlying electrode 6 is etched.
本発明は、かかる点に鑑みなされたもので、スループッ
トの向上が図れ、しかも信頼性の高い突起電極の形成が
可能な半導体装置の製造方法を提供することを主たる目
的としている。The present invention has been devised in view of these points, and its main object is to provide a method for manufacturing a semiconductor device that can improve throughput and form highly reliable protruding electrodes.
この発明の前記ならびにそのほかの目的と新規な特徴に
ついては、本明細書の記述および添附図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[課題を解決するための手段]
本願において開示される発明のうち代表的なものの概要
を説明すれば、下記のとおりである。[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.
即ち、本発明に係る半導体装置の製造方法は。That is, the method for manufacturing a semiconductor device according to the present invention is as follows.
突起電極形成予定領域が開口されたホトレジスト膜を上
記配線の上に直に形成し、その後下地重陽と゛なる積層
膜と突起電極となる導体膜とを順次に形成した後、上記
積層膜および導体膜の上記ホ1〜レジスト膜上に存在す
る部分を上記ホトレジスト膜の除去の際に同時に除去し
、その残りの導体膜を溶融させるこによって上記突起電
極を形成するようにしたものである。A photoresist film with an opening in the area where the protruding electrodes are to be formed is formed directly on the wiring, and then a laminated film serving as a base layer and a conductive film serving as the protruding electrodes are sequentially formed. The protruding electrodes are formed by simultaneously removing the portions existing on the photoresist film and melting the remaining conductive film.
[作用コ
上記した手段によれば、プロテクション膜形成の工程が
存在しないので、その分突起電極形成のための工数が低
減される6その結果、突起電極形成時間の短縮化が図れ
、さらには半導体装置の製造ラインにおけるスルーブツ
トの向上が図れることになる。[Function] According to the above-mentioned means, since there is no step of forming a protection film, the number of man-hours for forming the protruding electrodes is reduced accordingly.6 As a result, the time for forming the protruding electrodes can be shortened, and furthermore, the process of forming the protruding electrodes can be shortened. Throughput on the device manufacturing line can be improved.
また、上記した手段によれば、下地電極および導体膜の
選択除去にあたり、リフトオフ技術を用いて両者を同時
に選択除去するようにしているので、それらの選択除去
を別々に行っていた従来技術に比べて工程が短縮化され
、その分半導体装置の製造ラインにおけるスループット
が向上されることになる。Furthermore, according to the above-mentioned means, when selectively removing the base electrode and the conductor film, both are selectively removed at the same time using a lift-off technique, compared to the conventional technology in which the selective removal of the base electrode and the conductive film is performed separately. The process is shortened, and the throughput in the semiconductor device manufacturing line is improved accordingly.
さらに、上記した手段によれば、下地電極と導体膜とを
セルファライン化して共通マスクで形成しているので、
下地電極の形成から導体膜の形成までにホトリソグラフ
ィの工程、熱処理工程が入らない。したがって、下地電
極の酸化によるボイ1〜の発生が防げ、その結果、信頼
性の高い突起電極が得られることになる。Furthermore, according to the above-mentioned means, since the base electrode and the conductor film are formed in a self-lined manner using a common mask,
No photolithography process or heat treatment process is required from the formation of the base electrode to the formation of the conductor film. Therefore, the occurrence of voids 1 to 1 due to oxidation of the underlying electrode can be prevented, and as a result, a highly reliable protruding electrode can be obtained.
[実施例]
以下、本発明に係る半導体装置の製造方法の実施例を図
面に基づいて説明する。[Example] Hereinafter, an example of the method for manufacturing a semiconductor device according to the present invention will be described based on the drawings.
第1図(A)〜(F)には実施例の半導体装置の製造方
法が示されている。順をおって説明すれば下記のとおり
である。FIGS. 1A to 1F show a method for manufacturing a semiconductor device according to an embodiment. The explanation is as follows in order.
第1−図(A)は最終配線工程を終了した半導体ウェハ
を示している。ここで符号11は半導体ウェハを、符号
12はAQ’?Il極を表している。FIG. 1A shows a semiconductor wafer that has undergone the final wiring process. Here, reference numeral 11 indicates a semiconductor wafer, and reference numeral 12 indicates AQ'? It represents the Il pole.
このように最終配線工程が終了したならば、第1図(B
)に示すように半導体ウェハ11の裏面にメタライズ層
13を形成する。Once the final wiring process has been completed in this way, the wiring shown in Figure 1 (B
), a metallized layer 13 is formed on the back surface of the semiconductor wafer 11.
次に、半導体ウェハ11の主面に密着性の良い液状のホ
トレジスト
14を被着させ、さらにドライフィルム状のホトレジス
ト膜(第2のホトレジスト膜)15を被着させる。その
後,両ホトレジスト膜14,1.5の突起電極形成予定
領域に対応する部分を除去して頚部に開口16を形成し
、AΩ配線12の表面の一部を露出させて第1図(C)
の状態となる。Next, a liquid photoresist 14 with good adhesion is applied to the main surface of the semiconductor wafer 11, and a photoresist film (second photoresist film) 15 in the form of a dry film is further applied. Thereafter, the portions of both photoresist films 14 and 1.5 corresponding to the areas where the protruding electrodes are to be formed are removed to form an opening 16 in the neck, exposing a part of the surface of the AΩ wiring 12, as shown in FIG. 1(C).
The state will be as follows.
次いで、開口16内を含む全面に下地電極となる積層膜
、即ち特に制限はされないがCr.CuおよびAuの3
層からなる積層膜17を形成する。Next, the entire surface including the inside of the opening 16 is coated with a laminated film to serve as a base electrode, that is, a Cr. Cu and Au 3
A laminated film 17 consisting of layers is formed.
ここまで終了した状態が第1図(D)に示されている。The state that has been completed up to this point is shown in FIG. 1(D).
さらに、上記積層膜17の上にPb−Snの導体膜18
を形成する(第1図(E))。Furthermore, a Pb-Sn conductor film 18 is disposed on the laminated film 17.
(Fig. 1(E)).
その後、第1図(F)に示すように,ホトレジスト剥趙
液によって第1および第2のホトレジスト膜14.15
を除去する際に同時に、積層膜17および・導体1]5
j18の第1のホトレジスト膜14。Thereafter, as shown in FIG. 1(F), the first and second photoresist films 14 and 15 are removed using a photoresist stripping solution.
At the same time, when removing the laminated film 17 and the conductor 1]5
j18 first photoresist film 14.
15上に存在する部分を除去する。その後、ウェットバ
ックによって残りの導体膜18を溶融させることによっ
て,ボール状の突起電極(半田バンプ)を形成する。15 is removed. Thereafter, the remaining conductor film 18 is melted by wet-back to form a ball-shaped protruding electrode (solder bump).
上記した半導体装置の製造方法によれば下記の効果を得
ることができる。According to the method for manufacturing a semiconductor device described above, the following effects can be obtained.
即ち、上記製造方法によれば、従来行われていたプロテ
クション膜形成の工程が存在しないので、その分突起電
極形成のための工数が低減されるという作用によって、
突起電極形成時間の短縮化が図れ、さらには半導体装置
の製造ラインにおけるスループットの向上が図れること
になる。That is, according to the above manufacturing method, since there is no step of forming a protection film, which was conventionally performed, the number of man-hours for forming the protruding electrodes is reduced accordingly.
The time required to form the protruding electrodes can be shortened, and the throughput in the semiconductor device manufacturing line can also be improved.
また、上記製造方法によれば,下地電極となる積層膜1
7と突起電極となる導体膜18の選択除去にあたり、リ
フトオフ技術を用いて両者を同時に選択除去するように
しているので、それらの選択除去を別々に行っていた従
来技術に比べて工程が短縮化されるという作用によって
、そ切分半導体装置の製造ラインにおけるスループット
が向上されることになる。Further, according to the above manufacturing method, the laminated film 1 serving as the base electrode
7 and the conductor film 18 that will become the protruding electrode, lift-off technology is used to selectively remove both at the same time, which shortens the process compared to the conventional technology that selectively removes them separately. This effect improves the throughput in the production line for semiconductor devices cut into strips.
さらに、上記製造方法によれば、下地電極なる積層膜1
7と突起電極となる導体膜18とをセルファライン化し
て共通マスクで形成しているので、積層膜17の形成か
ら導体膜17の形成までにホトリソグラフィの工程、熱
処理工程が入らない。Furthermore, according to the above manufacturing method, the laminated film 1 serving as the base electrode
7 and the conductor film 18 which becomes the protruding electrode are formed in a self-aligned manner using a common mask, so that no photolithography process or heat treatment process is required between the formation of the laminated film 17 and the formation of the conductor film 17.
したがって、下地電極が酸化されず,ボイドの発生が防
げるという作用によって、半田濡れ性の劣化が生ぜず、
その結果、信頼性の高い突8電極が得られることになる
。Therefore, the base electrode is not oxidized and the generation of voids is prevented, thereby preventing deterioration of solder wettability.
As a result, a highly reliable protruding 8-electrode can be obtained.
また、上記実施例によれば、下地電極となる積層膜17
と突起電極となる導体膜18の選択除去にあたり、リフ
トオフ技術を用いて両者を同時に選択除去するようにし
ているので、下地電嘆形成にあたり下地電極を構成する
Cuがエツチングされることはない。さらに、下地電極
形成にあたりその下側のAQx[i12がエツチングさ
れることはない。Further, according to the above embodiment, the laminated film 17 serving as the base electrode
When selectively removing the conductor film 18 that will become the protruding electrode, both are simultaneously selectively removed using a lift-off technique, so that the Cu constituting the base electrode is not etched during the formation of the base electrode. Furthermore, when forming the base electrode, the underlying AQx[i12 is not etched.
なお、上記の製造方法は、AQ電極12の大きさがリフ
トオフマスク14,15より大きい場合に有効である。Note that the above manufacturing method is effective when the size of the AQ electrode 12 is larger than the lift-off masks 14 and 15.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
例えば、上記実施例によれば、下地電極としてCr、C
uおよびAuの3層からなる積層膜を用いているが、T
i、NiおよびAuの3M膜、CrおよびCuの2層膜
等であっても良い。For example, according to the above embodiment, as the base electrode, Cr, C
A laminated film consisting of three layers of u and Au is used, but T
It may be a 3M film of i, Ni and Au, a two-layer film of Cr and Cu, or the like.
また、突起電極を形成するに際して上記実施例では、P
b−8nの導体膜を用いたが、In−Pbの導体膜等を
用いるようにしても良い。In addition, when forming the protruding electrode, in the above embodiment, P
Although a b-8n conductor film is used, an In-Pb conductor film or the like may also be used.
[発明の効果]
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.
即ち、本発明に係る半導体装置の製造方法は、突起電極
形成予定領域が開口されたホ1−レジスト膜を上記配線
の上に直に形成し、その後下地電極となる積層膜と突起
電極となる導体膜とを順次に形成した後、上記積層膜お
よび導体膜の上記ホトレジスト膜上に存在する部分を上
記ホ1−レジスト膜の除去の際に同時に除去し、その残
りの導体膜を溶融させるこによって上記突起電極を形成
するようにしたみで、プロテクション膜形成の工程が存
在しないので、その分突起電極形成のための工数が低減
される。その結果、突起電極形成時間の短縮化が図れ、
さらには半導体装置の製造ラインにおけるスループット
の向上が図れることになる。That is, in the method of manufacturing a semiconductor device according to the present invention, a resist film having an opening in a region where a protruding electrode is to be formed is formed directly on the wiring, and then a laminated film that becomes a base electrode and a laminated film that becomes a protruding electrode are formed. After sequentially forming the conductor film, the portions of the laminated film and the conductor film that are present on the photoresist film are removed at the same time as the photoresist film is removed, and the remaining conductor film is melted. Since the protruding electrodes are simply formed using the method described above and there is no step of forming a protection film, the number of man-hours for forming the protruding electrodes is reduced accordingly. As a result, the time required to form protruding electrodes can be shortened.
Furthermore, the throughput in the semiconductor device manufacturing line can be improved.
また、下地電極および導体膜の選択除去にあたり、リフ
トオフ技術を用いて両者を同時に選択除去するようにし
ているので、それらの選択除去を別々に行っていた従来
技術に比べて工程が短縮化され、その分生導体装置の製
造ラインにおけるスループットが向上されることになる
。In addition, when selectively removing the base electrode and the conductor film, lift-off technology is used to selectively remove both at the same time, which shortens the process compared to the conventional technology that selectively removes them separately. Accordingly, the throughput in the production line of the live conductor device is improved.
さらに、本発明によれば、下地電極と導体膜とをセルフ
ァライン化して共通マスクで形成しているので、下地電
極の形成から導体膜の形成までにホトリソグラフィの工
程、熱処理工程が入らない。Further, according to the present invention, since the base electrode and the conductor film are formed in a self-aligned manner using a common mask, no photolithography process or heat treatment process is required between the formation of the base electrode and the formation of the conductor film.
したがって、下地電極の酸化が生ぜず、ボイドの発生が
防げる結果、信頼性の高い突起電極が得られることにな
る。Therefore, oxidation of the underlying electrode does not occur and the generation of voids can be prevented, resulting in a highly reliable protruding electrode.
第1図(A)〜(F)は本発明に係る半導体装置の盈造
方法の実施例の各工程における半導体基板の縦断面図、
第2図(A)〜(D)は従来の半導体装置の製造方法の
各工程における半導体基板の縦断面図である。
11・・・・半導体ウェハ、12・・・・AQ配線、1
4.15・・・・ホトレジスト膜、17・・・・積層膜
、18・・・・導体膜。
第 1 図
どA)
(g)
第
図
(E)
/7
(F)
第2
(A)
図
(D)FIGS. 1(A) to (F) are longitudinal cross-sectional views of a semiconductor substrate in each step of an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2(A) to (D) are longitudinal sectional views of a conventional semiconductor device. FIG. 3 is a vertical cross-sectional view of the semiconductor substrate in each step of the manufacturing method. 11... Semiconductor wafer, 12... AQ wiring, 1
4.15...Photoresist film, 17...Laminated film, 18...Conductor film. Figure 1 (A) (g) Figure (E) /7 (F) Figure 2 (A) Figure (D)
Claims (1)
を形成するにあたり、突起電極形成予定領域が開口され
たホトレジスト膜を上記配線の上に直に形成し、その後
下地電極となる積層膜と突起電極となる導体膜とを順次
に形成した後、上記積層膜および導体膜の上記ホトレジ
スト膜上に存在する部分を上記ホトレジスト膜の除去の
際に同時に除去し、その残りの導体膜を溶融させるこに
よって上記突起電極を形成するようにしたことを特徴と
する半導体装置の製造方法。 2、上記ホトレジスト膜は2層構造となっており、その
うち下層が液状ホトレジスト膜となっており、上層がド
ライフィルム状のホトレジスト膜となっていることを特
徴とする請求項1記載の半導体装置の製造方法。[Claims] 1. When forming a protruding electrode on the wiring of a semiconductor chip via a base electrode, a photoresist film in which a region where the protruding electrode is to be formed is opened is directly formed on the wiring, and then a base electrode is formed. After sequentially forming a laminated film that will become an electrode and a conductor film that will become a protruding electrode, the portions of the laminated film and conductor film that are present on the photoresist film are simultaneously removed when the photoresist film is removed, and the remaining portions are removed. A method of manufacturing a semiconductor device, characterized in that the protruding electrodes are formed by melting a conductor film. 2. The semiconductor device according to claim 1, wherein the photoresist film has a two-layer structure, of which the lower layer is a liquid photoresist film and the upper layer is a dry film-like photoresist film. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63238754A JPH0287526A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63238754A JPH0287526A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0287526A true JPH0287526A (en) | 1990-03-28 |
Family
ID=17034766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63238754A Pending JPH0287526A (en) | 1988-09-26 | 1988-09-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0287526A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0422131A (en) * | 1990-05-17 | 1992-01-27 | Sharp Corp | Bump |
US6649507B1 (en) * | 2001-06-18 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Dual layer photoresist method for fabricating a mushroom bumping plating structure |
-
1988
- 1988-09-26 JP JP63238754A patent/JPH0287526A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0422131A (en) * | 1990-05-17 | 1992-01-27 | Sharp Corp | Bump |
US6649507B1 (en) * | 2001-06-18 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Dual layer photoresist method for fabricating a mushroom bumping plating structure |
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