JPH02164039A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02164039A JPH02164039A JP63321244A JP32124488A JPH02164039A JP H02164039 A JPH02164039 A JP H02164039A JP 63321244 A JP63321244 A JP 63321244A JP 32124488 A JP32124488 A JP 32124488A JP H02164039 A JPH02164039 A JP H02164039A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding pads
- forming
- bonding pad
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000007747 plating Methods 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 20
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に′＋１！
極用金属膜で形成したボンディングパッド上に金などで
バンプを形成する場合の工程改善に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, '+1!
This invention relates to process improvement when forming bumps with gold or the like on bonding pads formed with electrode metal films.
ワイヤレスボンディングのために、チップのボンディン
グパッド上にめっきにより金属のバンプを形成している
半導体装置の製造方法において、従来の公知のバンプ製
造工程を第２図を参照して説明する。In a semiconductor device manufacturing method in which metal bumps are formed by plating on bonding pads of chips for wireless bonding, a conventional and well-known bump manufacturing process will be described with reference to FIG.
第２図（ａ）に示すように、半導体基板２０１上に所定
の回路を形成し、層間絶縁［Ｉ２０２を被着し、その上
に配線用アルミニウム膜を形成する０図で２０３はボン
ディングパッドを示す６次に表面保護用酸化Ｈ２Ｏ４を
被着後、ボンディングパッド２０３上を開口する。As shown in FIG. 2(a), a predetermined circuit is formed on a semiconductor substrate 201, an interlayer insulator [I202] is deposited, and an aluminum film for wiring is formed on it. 6 After depositing oxidized H2O4 for surface protection, an opening is made above the bonding pad 203.
以上の工程後に、バンプを形成するために、アルミニウ
ムＭ ２０５を被覆する。このアルミニウム膜２０５は
バンプ形成のため電気めっきする際に、チップ上のすべ
てのボンディングパッド２０３を同電位に保ち、均一な
バンプを形成するためのものである。このアルミニウム
膜２０５上に塗布したホトレジス） ２０Ｂをボンディ
ングパッド２０３上に開口部がくるようパターニングし
た後に、チタン等が主成分の中間合Ｊｉ！８２０７をス
パッタ法等により積層する。この中間金属膜はアルミニ
ウム膜２０５と後で形成する金バンプとの密着性を良く
するとともに、金の拡散を防ぐために必要なものである
。中間金属＄ ２０７はエツチングにより除去すること
が困難であるので、ホトレジスト２０Ｂを用いたリフト
オフ法によりボンディングパッド２０３上にのみ残すよ
うにパターニングする。After the above steps, aluminum M205 is coated to form bumps. This aluminum film 205 is used to keep all bonding pads 203 on the chip at the same potential during electroplating to form bumps, thereby forming uniform bumps. After patterning the photoresist (20B) coated on this aluminum film 205 so that the opening is located on the bonding pad 203, an intermediate layer containing titanium or the like as a main component is patterned. 8207 is laminated by sputtering or the like. This intermediate metal film is necessary to improve the adhesion between the aluminum film 205 and the gold bumps to be formed later, and to prevent gold from diffusing. Since it is difficult to remove the intermediate metal $ 207 by etching, it is patterned by a lift-off method using a photoresist 20B so that it remains only on the bonding pad 203.
次に第２図（ｂ）に示すように、ボンディングパッド２
０３上を開口したホトレジスト２０８をマスクとして金
バンブ２０８をめっき法により成長させる。この後第２
図（Ｃ）に示すように、ホトレジスト２０８を除去し、
中間金ｍ 膜２０７と金バンプ２０９をマスクとして、
アルミニウム膜２０５をエツチング除去し、組立のとき
の緩衝材としてポリイミド樹脂２１０を塗布し、金バン
プ２０９上を開口してパターニングすることによって半
導体装置を完成する。Next, as shown in FIG. 2(b), the bonding pad 2
Gold bumps 208 are grown by a plating method using a photoresist 208 with an opening above 03 as a mask. After this, the second
As shown in Figure (C), remove the photoresist 208,
Using the intermediate gold film 207 and gold bumps 209 as a mask,
The semiconductor device is completed by etching away the aluminum film 205, applying polyimide resin 210 as a buffer material during assembly, and patterning with openings on the gold bumps 209.
〔発明が解決しようとする課題〕
上述した半導体装置の製造工程では、バンプをめっきで
成長させる際にボンディングパッドをすべて同電位にす
るために、表面保護用酸化膜上にアルミニウム膜を形成
し、めっき後にアルミニウム膜をバンプ下部を除き除去
している。このため、工程が複雑になるだけでなく、半
導体装置の表面保護用酸化膜にクラックが生じている場
合には、上記のアルミニウム膜のエツチング除去の際に
、配線用アルミニウム膜までエツチングされてしまい、
所望の回路が動作しなくなるという欠点がある。[Problems to be Solved by the Invention] In the manufacturing process of the semiconductor device described above, in order to make all the bonding pads the same potential when growing bumps by plating, an aluminum film is formed on the surface protective oxide film, After plating, the aluminum film is removed except for the lower part of the bump. This not only complicates the process, but if cracks occur in the oxide film for protecting the surface of semiconductor devices, the wiring aluminum film may also be etched away when the aluminum film is etched away. ,
The disadvantage is that the desired circuit will no longer work.
本発明の目的は、上記の欠点を除去し、バンプ形成工程
において工程の簡素化と、配線用アルミニウム膜を損傷
しない半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, simplifies the bump forming process, and does not damage the wiring aluminum film.
本発明の製造方法では、チップのボンディングパッドを
すべて同電位とする結線膜を形成する工程と１表面保護
用酸化膜を被着後、前記ボンディングパッド上部を開口
する工程と、前記開口部にのみ中間金属膜を形成し、そ
の上にバンプをめっき法により形成する工程と、前記結
線導体を所定の位置において、レーザビームにより溶断
する工程とにより、バンプを形成するようにしている。The manufacturing method of the present invention includes a step of forming a connecting film that makes all the bonding pads of the chip have the same potential, a step of opening the upper part of the bonding pad after depositing a surface protective oxide film, and a step of opening the upper part of the bonding pad only in the opening. The bumps are formed by forming an intermediate metal film and forming the bumps thereon by plating, and by cutting the connecting conductor at a predetermined position using a laser beam.
なお、チップのボンディングパッドを結ぶ結線膜を形成
する工程は、パッド形成と同時に、または別途でよい、
また材質として、アルミニウム等の金属膜、多結晶シリ
コン膜などを用いることができる。Note that the step of forming a connecting film connecting the bonding pads of the chip may be performed at the same time as the pad formation, or may be performed separately.
Further, as the material, a metal film such as aluminum, a polycrystalline silicon film, etc. can be used.
ボンディングパッドを結ぶ結線膜は、バンプ形成前にな
され、バンプ形成後にレーザビームにより溶断する。結
線膜の形成は、ボンディングパッド形成と同一工程でも
形成できる。また、結線膜を幅の狭い膜とすれば、レー
ザビームで局所的に容易に溶断可渣である。A connecting film connecting the bonding pads is formed before the bump is formed, and is fused by a laser beam after the bump is formed. The connection film can be formed in the same process as the bonding pad formation. Furthermore, if the connecting film is a narrow film, the residue can be easily locally fused with a laser beam.
以下、本発明の一実施例について図面を参照して説明す
る。第１図（Ｃ）に本実施例により形成したバンプ構造
の縦断面図を示す０図において１０１は半導体基板、１
Ｇ２は配線用アルミニウム膜と半導体基板１０１上の電
極膜を絶縁するための居間絶縁膜、１０３はアルミニウ
ム膜で形成したボンディングパッド、１０４は表面保護
用酸化膜、１０７はチタンを主成分とする中間金属膜、
１０９は金バンプ、１１Ｏはポリイミド樹脂である。An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1(C), which shows a vertical cross-sectional view of the bump structure formed according to this example, 101 is a semiconductor substrate;
G2 is a living room insulating film for insulating the aluminum film for wiring and the electrode film on the semiconductor substrate 101, 103 is a bonding pad formed of an aluminum film, 104 is an oxide film for surface protection, and 107 is an intermediate film mainly composed of titanium. metal film,
109 is a gold bump, and 11O is a polyimide resin.
次に製造方法を第１図（ａ）〜（ｄ）を参照して説明す
る。第１図（ａ）に示すように、半導体基板１０１上に
居間絶縁膜１０２を介してボンディングパッド１０３を
アルミニウムで０．５〜１、ＯＪＬ厚に形成する工程の
平面図である。ボンディングパッド１０３はおのおの隣
のボンディングパッドと結線膜１０Ｇで接続されるよう
にパターニングする。この結線［１１００は最後にレー
ザビームで溶断し易いように、その形状を定めておく。Next, the manufacturing method will be explained with reference to FIGS. 1(a) to 1(d). As shown in FIG. 1(a), this is a plan view of a step of forming a bonding pad 103 of aluminum with a thickness of 0.5 to 1 OJL on a semiconductor substrate 101 via a living room insulating film 102. Each bonding pad 103 is patterned so as to be connected to its neighboring bonding pad through a connecting film 10G. The shape of this connection [1100 is determined so that it can be easily fused with a laser beam at the end.
次に、第１図（ｂ）の縦断面図に示すように、表面保護
用酸化膜１０４を０．５〜１．０ ｇ厚に形成し、パタ
ーニングを行なって、ボンディングパッド１０３上を開
口する。さらに全面にポリイミド樹脂１１０を塗布して
ボンディングパッド１０３上のポリイミド樹脂をホトレ
ジス） １０８を用いて開口する。その後でチタンを主
成分とした中間金属［１０７をスパッタ法等により４０
００〜７０００Ａ厚に形成する。Next, as shown in the vertical cross-sectional view of FIG. 1(b), a surface protective oxide film 104 is formed to a thickness of 0.5 to 1.0 g, and patterned to form an opening on the bonding pad 103. . Further, a polyimide resin 110 is applied to the entire surface, and an opening is formed in the polyimide resin on the bonding pad 103 using a photoresist (108). Thereafter, the intermediate metal [107] containing titanium as the main component was processed by sputtering, etc. to give 40%
Formed to a thickness of 00 to 7000A.
この後、第１図（Ｃ）に示すように、中間金属膜１０７
の不要部分をホトレジスト膜によりリフトオフし、金バ
ンプ１０９をポリイミド樹脂１１０をマスクとしてボン
ディングパッド１０３上にめっき法により形成する。After this, as shown in FIG. 1(C), the intermediate metal film 107
Unnecessary portions of the bonding pads 103 are lifted off using a photoresist film, and gold bumps 109 are formed on the bonding pads 103 by plating using the polyimide resin 110 as a mask.
次に第１図（ｄ）に平面図で示すように、ボンディング
パッド１０３間を接続する結線ｇｔｏ。Next, as shown in a plan view in FIG. 1(d), a connection GTO is formed to connect the bonding pads 103.
をレーザビームを用いて溶断することにより半導体装置
が完成する。A semiconductor device is completed by cutting the semiconductor device using a laser beam.
上記実施例では、結線膜はボンディングパッドと同時に
アルミニウム膜で形成しているが、結線膜は、ボンディ
ングパッドを同電位とするものであれば、抵抗膜であっ
てもよい。第２実施例として抵抗膜である例につき説明
する。In the above embodiment, the wiring film is formed of an aluminum film at the same time as the bonding pad, but the wiring film may be a resistive film as long as the wiring film has the same potential as the bonding pad. As a second embodiment, an example of a resistive film will be explained.
ＭＯ３ＩＣでは入力保護のために、パッドと内部系との
間に抵抗・ＭＯＳ）ランジスタによる保護回路を設けて
いる。この抵抗は多結晶シリコン膜で形成するので、前
記保護回路形成時に、すべてのボンディングパッドを結
線するように多結晶シリコン膜を結線する。第３図がそ
の平面図である。後の工程は前記実施例と同一で最終的
に、結線！ｌ１００Ａをレーザビームで溶断する。MO3IC has a protection circuit using a resistor/MOS transistor between the pad and the internal system for input protection. Since this resistor is formed of a polycrystalline silicon film, the polycrystalline silicon film is wired so as to connect all the bonding pads when forming the protection circuit. FIG. 3 is a plan view thereof. The subsequent steps are the same as in the previous example, and the final step is wiring! Fuse the l100A with a laser beam.
以上説明したように、本発明はすべてのボンディングパ
ッドが同電位になるようにパッド間に結線膜を形成して
から１表面保護用酸化膜を形成し、バンプのめっきを行
なった後に結線膜の溶断を行なっている。従来のように
バンプ形成後に全面に被着された同電位化のためのアル
ミニウム膜を除去する工程が省けて、簡素化されるばか
りでなく、その際に表面保護用酸化膜にクラックがあっ
ても配線用アルミニウムに損傷を与えないという効果が
ある。As explained above, in the present invention, a connecting film is formed between pads so that all the bonding pads have the same potential, and then a surface protective oxide film is formed, and after bump plating, the connecting film is formed. Performing fusing. This not only simplifies the process by eliminating the conventional step of removing the aluminum film that is deposited on the entire surface after bump formation to equalize the potential, but also eliminates the possibility of cracks in the surface protective oxide film during the process. It also has the effect of not damaging the aluminum wiring.
レーザビームによる結線膜の溶断は、結線膜の形状・位
置を考慮することで、容易に溶断でき、しかも半導体装
置の信頼性を損傷しないようにできる。By taking the shape and position of the wiring film into consideration, the wiring film can be easily fused and cut out using a laser beam without damaging the reliability of the semiconductor device.
第１図は本発明の一実施例に係り、（ａ）（ｄ）は平面
図、（ｂ）（Ｃ）は縦断面図、第２図（ａ）〜（ｃ）は
従来例を示す縦断面図、第３図は別の実施例の平面図で
ある。
１００．１００Ａ・・・結！！膜、 ｔｏｉ・・・半導
体基板。
１０２・・・層間絶縁膜、
１０３・・・ボンディングパッド、
１０４・・・表面保護用酸化膜、
１０７・・・中間金属膜、 １０９・・・金バンプ、１
１０・・・ポリイミド樹脂。
特許出願人 日本電気株式会社
第１図ｔの１
ｒａ）
代理人 弁理士 内 原 晋＜ｄ＋Fig. 1 relates to an embodiment of the present invention, (a) and (d) are plan views, (b) and (C) are longitudinal cross-sectional views, and Fig. 2 (a) to (c) are longitudinal cross-sectional views showing a conventional example. FIG. 3 is a plan view of another embodiment. 100.100A...Conclusion! ! Film, toi...semiconductor substrate. 102... Interlayer insulating film, 103... Bonding pad, 104... Oxide film for surface protection, 107... Intermediate metal film, 109... Gold bump, 1
10...Polyimide resin. Patent applicant NEC Corporation Figure 1 t-1 ra) Agent Patent attorney Susumu Uchihara <d+
Claims (1)
る半導体装置の製造方法において、チップのボンディン
グパッドをすべて同電位とする結線膜を形成する工程と
、表面保護用酸化膜を被着後、前記ボンディングパッド
上部を開口する工程と、前記開口部にのみ中間金属膜を
形成し、その上にバンプをめっき法により形成する工程
と、前記結線導体膜を所定の位置において、レーザビー
ムにより溶断する工程とを含むことを特徴とする半導体
装置の製造方法。In a method of manufacturing a semiconductor device in which bumps are generated on bonding pads by plating, there are two steps: forming a connecting film that makes all the bonding pads of a chip have the same potential, and after depositing a surface protective oxide film, the upper part of the bonding pad is forming an intermediate metal film only in the opening and forming a bump thereon by plating; and cutting the wire-connecting conductor film at a predetermined position with a laser beam. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63321244A JP2734585B2 (en) | 1988-12-19 | 1988-12-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63321244A JP2734585B2 (en) | 1988-12-19 | 1988-12-19 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02164039A true JPH02164039A (en) | 1990-06-25 |
| JP2734585B2 JP2734585B2 (en) | 1998-03-30 |
Family
ID=18130418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63321244A Expired - Fee Related JP2734585B2 (en) | 1988-12-19 | 1988-12-19 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2734585B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000021132A1 (en) * | 1998-10-05 | 2000-04-13 | Intersil Corporation | Semiconductor integrated circuit with temporarily interconnected bond pads |
| JP2013105771A (en) * | 2011-11-10 | 2013-05-30 | Toppan Printing Co Ltd | Bump electrode formation method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5380161A (en) * | 1976-12-24 | 1978-07-15 | Matsushita Electric Ind Co Ltd | Electrode formation of semiconductor |
-
1988
- 1988-12-19 JP JP63321244A patent/JP2734585B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5380161A (en) * | 1976-12-24 | 1978-07-15 | Matsushita Electric Ind Co Ltd | Electrode formation of semiconductor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000021132A1 (en) * | 1998-10-05 | 2000-04-13 | Intersil Corporation | Semiconductor integrated circuit with temporarily interconnected bond pads |
| JP2013105771A (en) * | 2011-11-10 | 2013-05-30 | Toppan Printing Co Ltd | Bump electrode formation method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2734585B2 (en) | 1998-03-30 |
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