WO2000021132A1 - Semiconductor integrated circuit with temporarily interconnected bond pads - Google Patents

Semiconductor integrated circuit with temporarily interconnected bond pads Download PDF

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Publication number
WO2000021132A1
WO2000021132A1 PCT/US1999/023100 US9923100W WO0021132A1 WO 2000021132 A1 WO2000021132 A1 WO 2000021132A1 US 9923100 W US9923100 W US 9923100W WO 0021132 A1 WO0021132 A1 WO 0021132A1
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WO
WIPO (PCT)
Prior art keywords
bond pads
conductor elements
electrical conductor
integrated circuit
bond
Prior art date
Application number
PCT/US1999/023100
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French (fr)
Other versions
WO2000021132A9 (en
Inventor
William R. Wade
Ramon N. Sevilla
Jack H. Linn
Original Assignee
Intersil Corporation
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Filing date
Publication date
Application filed by Intersil Corporation filed Critical Intersil Corporation
Publication of WO2000021132A1 publication Critical patent/WO2000021132A1/en
Publication of WO2000021132A9 publication Critical patent/WO2000021132A9/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor integrated circuit has a plurality of bond pads, substantially all of which are interconnected by severable electrical conductor elements. Interconnection substantially reduces surface etch damage to the bond pads during wafer processing and/or storage. Severing the electrical conductor elements results in a functional integrated circuit whose bond pads are substantially free of surface etch damage. A process for preventing or substantially diminishing surface etch damage to the bond pads of an integrated circuit entails temporarily interconnecting substantially all of the bond pads of the circuit by severable electrical conductor elements, which results in the equalization of potential energy across the interconnected bond pads.

Description

SEMICONDUCTOR INTEGRATED CIRCUIT WITH TEMPORARILY INTERCONNECTED BOND PADS
The present invention relates to semiconductor devices containing bond pads and, in particularly, to integrated circuits having bond pad interconnects for equalizing potential energy across the bond pads during wafer processing and/ or wafer storage.
In a semiconductor integrated circuit, individual bond pads possess energies of different potentials. This situation, which arises as a result of the metallic bond pads being in contact with a variety of circuits, can result in deleterious etching of the bond pads. Such etch effects include discoloration, corrosion, and other damage to the bond pad surfaces. Temporarily interconnecting the bond pads by electrical conductor elements equalizes the potential energy across the pads, resulting in diminished etching of the pad surfaces.
In the specification of U.S. Patent No. 5,751,051, is disclosed the interconnection of bond pads to a common discharge line to prevent damage to a semiconductor device by high voltage caused by static electricity. The specification of U.S. Patent No. 5,436,197, describes a method of forming a test card having a plurality of bonding pads in each of a plurality of regions, wherein at least one bonding pad in one region is coupled to at least one bonding pad in another region. The stated use of the test card is to transmit electrical signals to and from a semiconductor device that is being tested. The specification of U.S. Patent No. 5,679,609, discloses a multisemiconductor structure having wire outs and connect assemblies that include contact pads and fuses. The connect assemblies, which are intended to facilitate burn-in stressing and electrical testing of the structure, can either be removed or left in place after testing.
The specification of U.S. Patent No. 5,719,087, discusses etch damage of bond pad surfaces and discloses the deposition of a protective cap of dielectric material on the bond pad surface prior to deposition of a passivation layer. The stated purpose of the dielectric cap is to prevent damage to bond pad surfaces during etching of contact holes.
The specification of U.S. Patent No. S,618,750, describes a method for forming a fuse made of a corrosive material in a semiconductor integrated circuit. The corrosive material of the fuse is separated from the circuitry by a barrier region of non-corrosive conductive material, which is said to prevent corrosion occurring in the fuse region from proceeding past the barrier region.
The present invention includes a semiconductor integrated circuit comprising a plurality of bond pads and severable electrical conductor elements temporarily interconnecting substantially all of said bond pads, so as to enable said electrical conductor elements equalize potential energy across said bond pads, thereby preventing or substantially reducing surface etch damage to said bond pads. The invention also includes a process for preventing or substantially diminishing surface etch damage to bond pads in a semiconductor integrated circuit comprising a plurality of bond pads, said process comprising: temporarily interconnecting substantially all of said bond pads by severable electrical conductor elements, so as to equalize potential energy across said temporarily interconnected bond pads. Conveniently, the present invention is directed to a semiconductor integrated circuit having a plurality of bond pads, substantially all of which are temporarily interconnected by severable electrical conductor elements. Interconnection prevents or substantially reduces surface etch damage to the bond pads during wafer processing. Severing the electrical conductor elements results in a functional integrated circuit whose bond pads are substantially free of surface etch damage.
Further in accordance with the present invention is a process for preventing or substantially diminishing surface etch damage to the bond pads of an integrated circuit. The process entails temporarily interconnect substantially all of the bond pads of the circuit by severable electrical conductor elements, which result the equalization of potential energy across the interconnected bond pads during wafer processing. Severing the conductor elements from the bond pads, thereby disrupting the interconnection of the bond pads, yields a functional integrated circuit having bond pads that are substantially free of surface etch damage.
The invention will now be described by way of example, with reference to the accompanying drawings in which:
FIG. 1A is a schematic representation of the bond pads and severable electrical conductor elements in an integrated circuit of the present invention.
FIG. IB is a schematic representation of the integrated circuit of FIG. 1A with the conductor elements severed. FIG. 2 is a schematic representation of the integrated circuit of the invention provided with an overlying passivation layer.
FIG. 3 is a schematic representation of an integrated circuit of the invention having a passivation layer and fuses as severable electric conductor elements.
The semiconductor integrated circuit of the present invention comprises a plurality of bond pads, substantially all of which are temporarily interconnected by severable electrical conductor elements. The conductor elements equalize potential energy across the bond pads, which prevents or substantially reduces surface etch damage to the bond pads. When the electrical conductor elements are severed, resulting in a disconnection of the bond pads from one another, a functional integrated circuit whose bond pads are substantially free of surface etch damage is produced.
FIG. 1A is a schematic representation of integrated circuit 10A of the present invention that depicts bond pads lla-f temporarily interconnected by electrical conductor elements 12a-f but does not show other components included in circuit 10A. The remaining FIGS. IB, 2, and 3 also show the bond pads and conductor elements but not other components included in the integrated circuits.
Preferably, both the bond pads lla-f and the electrical conductor elements 12a-f are formed of metal.
The metal layer forming bond pads lla-f can be deposited prior to that forming electrical conductor elements 12a-f, or vice-versa. Both bond pads lla-f and conductor elements 12a-f can be formed of the same or different materials. Bond pads lla-f are preferably formed from a metal selected from the group consisting of aluminurn, copper, gold, titanium, tungsten, and alloys thereof. Electrical conductor elements 12a-f can be formed from a metal selected from the group consisting of aluminum, copper, gold, chromium, nickel, molybdenum, titanium, tungsten, and alloys thereof. The electrical conductor elements can each comprise a fuse.
The integrated circuit of the present invention can be constructed in a variety of configurations. For example, each bond pad can be temporarily connected to only one electrical conductor element. Alternatively, at least one bond pad in the circuit can be connected to more than one conductor element. Conversely, at least one electrical conductor element can be connected to more than one bond pad. In the configuration represented by FIG. 1A, bond pad lid is connected to a single conductor element, 12d. Bond pad lie, however, is connected to two conductor elements, 12c and 12f, while bond pad lib is connected to conductor elements 12b, 12c, and 12e. In FIG. IB is schematically shown integrated circuit 10B, in which the severable conductor elements 12a-f of FIG. 1A have been severed to 13a-f, respectively, resulting in disconnection from one another of previously interconnected bond pads lla-f. As schematically depicted in FIG. 2, an integrated circuit 20 of the present invention can further comprise a passivation layer 21. Holes 22a-f and 23a-f formed in passivation layer provide access to, respectively, bond pads 24a-f and conductor elements 25a-f of integrated circuit 20. Holes 22a-f enable connection of bond pads 24a-f to other components (not shown) of circuit 20. Hoes 23a-f provide access to conductor elements 25a-f to allow them to be severed, thereby disconnecting bond pads 24a-f from one another. Further in accordance with the present invention is a process for preventing or substantially diminishing surface etch damage to bond pads in a semiconductor integrated circuit comprising a plurality of bond pads. The process entails temporarily interconnecting substantially all of the bond pads by severable electrical conductor elements, as shown in previously discussed FIG. IA. When, in accordance with the method of the invention, the interconnection of the bond pads is disrupted by severing the conductor elements, as shown in FIG. IB, the resulting integrated circuit is characterized by bond pads whose surfaces are substantially free of etch damage.
Severing of the electrical conductor elements, thereby disconnecting the bond pads from one another, can be accomplished in a variety of ways. One useful method is optical ablation, whereby material comprising the conductor elements is vaporized by a laser pulse. Another suitable method for severing the conductor elements makes use of physical milling of the conductor element material. Ion milling using argon, for example, is a common physical nulling technique.
Still another method for severing the electrical conductor elements makes use of sawing the conductor elements when they reside in the scribe street.
Still another method for severing the conductor elements makes use of a chemical etch procedure, for example, reactive ion etching or wet chemical etching, that is selective to the material comprising the conductor elements. For example, the bond pads can be formed of aluminurn or gold, while the conductor elements are made of titanium, titanium-tungsten alloy, or molybdenum. Hydrogen peroxide reacts with and removes these latter metals but does not etch the aluminum or gold bond pads.
If the integrated circuit includes an overlying passivation layer, as shown in the previously discussed FIG. 2, holes (23a-f) through the passivation layer (21) are required to provide access to the conductor elements (25a-f) for severing by laser ablation, ion milling, or reactive ion etching techniques. However, if the electrical conductor elements are fuses, disconnection can be achieved by application of voltage sufficient to blow the fuses, and access holes through the passivation layer are not required. This is schematically depicted in FIG. 3, where integrated circuit 30 includes passivation layer 31, bond pads 32a-f, and electrical conductor elements comprising fuses 33a-f . Holes 34a-f through passivation layer 31 enable connection of bond pads 32a-f to other components (not shown) of integrated circuit 30. However, because fuses 33a-f can be blown by application of a voltage, thereby disconnecting bond pads 32a-f from one another, no access holes through passivation layer 31 to fuses 33a-f are required. Interconnection of the bond pads by electrical conductor elements can be maintained during storage of the devices in wafer form. Proper storage conditions can decrease the likelihood of corrosion or other bond pad surface damage from electrical reactions involving moisture and potential differences across bond pads. Severing the electrical conductor elements to disconnect the bond pads as described above restores the electrical functioning of the integrated circuit.
A semiconductor integrated circuit has a plurality of bond pads, substantially all of which are interconnected by severable electrical conductor elements. Interconnection or substantially reduces surface etch damage to the bond pads during wafer processing and/ or storage. Severing the electrical conductor elements results in a functional integrated circuit whose bond pads are substantially free of surface etch damage. A process for preventing or substantially dinrinishing surface etch damage to the bond pads of an integrated circuit entails temporarily interconnecting substantially all of the bond pads of the circuit by severable electrical conductor elements, which results in the equalization of potential energy across the interconnected bond pads.

Claims

Claims:
1. A semiconductor integrated circuit comprising a plurality of bond pads and severable electrical conductor elements temporarily interconnecting substantially all of said bond pads, so as to enable said electrical conductor elements equalize potential energy across said bond pads, thereby preventing or substantially reducing surface etch damage to said bond pads.
2. A circuit as claimed in claim I wherein said electrical conductor elements are severed and said bond pads are substantially free of surface etch damage, in which said bond pads and said electrical conductor elements comprise a metal.
3. A circuit as claimed in claim 2 wherein said bond pads and said electrical conductor elements comprise the same metal or comprise a metal different from the metal included in said electrical conductor elements.
4. A circuit as claimed in claim 3 wherein said bond pads comprises a metal selected from the group consisting of aluminum, copper, gold, titanium, tungsten, and alloys thereof, and which said electiical conductor elements comprise a metal selected from the group consisting of alunrinum, copper, gold, chromium, nickel, molybdenum, titanium, tungsten, and alloys thereof, and said electrical conductor elements comprises a fuse, and said bond pad is connected to at least only one electrical conductor element.
5. A circuit as claimed in claim 4 wherein at least one conductor element is connected to more than one bond pad.
6. A circuit as claimed in claim 5 including a passivation layer overlying the bond pads and electrical conductor elements, said passivation layer including contact holes for providing access to said bond pads and said electrical conductor elements.
7. A process for preventing or substantially diminishing surface etch damage to bond pads in a semiconductor integrated circuit comprising a plurality of bond pads, said process comprising: temporarily interconnecting substantially all of said bond pads by severable electrical conductor elements, so as to equalize potential energy across said temporarily interconnected bond pads.
8. A process of claim 7 wherein each said bond pad is connected to only one electrical conductor element, or 7 at least one bond pad is connected to more than one electrical conductor element.
9. A process as claimed in claim 7 wherein at least one conductor element is connected to more than one bond pad, and including the step of severing said electrical conductor elements, so as to disrupt said interconnecting of said bond pads and forming a semiconductor integrated circuit having bond pads substantially free of surface etch damage.
10. The process as claimed in claim 7 wherein said bond pads and said electiical conductor elements comprise a metal, and said conductor elements comprise the same metal, and said bond pads comprise a metal different from the metal included in said electrical conductor elements.
11. A process as claimed in claim 7 wherein said disconnecting said electrical conductor elements comprises optically ablating said conductor elements, in which said disconnecting said electrical conductor elements comprises ion milling said electrical conductor elements, including said disconnecting said electrical conductor elements comprises sawing said electrical conductor elements, and also said electiical conductor elements comprises chemically etching said electrical conductor elements, and also said electiical conductor elements comprise fuses.
PCT/US1999/023100 1998-10-05 1999-10-05 Semiconductor integrated circuit with temporarily interconnected bond pads WO2000021132A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16641698A 1998-10-05 1998-10-05
US09/166,416 1998-10-05

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WO2000021132A1 true WO2000021132A1 (en) 2000-04-13
WO2000021132A9 WO2000021132A9 (en) 2000-08-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553061B1 (en) 2015-11-19 2017-01-24 Globalfoundries Inc. Wiring bond pad structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02164039A (en) * 1988-12-19 1990-06-25 Nec Corp Manufacture of semiconductor device
JPH0470108A (en) * 1990-07-11 1992-03-05 Hitachi Ltd Surface acoustic wave device, manufacture of the device and equipment using the same device
EP0589519A2 (en) * 1992-09-24 1994-03-30 Philips Electronics Uk Limited Electronic device manufacture
US5719087A (en) * 1996-03-07 1998-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Process for bonding pad protection from damage

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02164039A (en) * 1988-12-19 1990-06-25 Nec Corp Manufacture of semiconductor device
JPH0470108A (en) * 1990-07-11 1992-03-05 Hitachi Ltd Surface acoustic wave device, manufacture of the device and equipment using the same device
EP0589519A2 (en) * 1992-09-24 1994-03-30 Philips Electronics Uk Limited Electronic device manufacture
US5719087A (en) * 1996-03-07 1998-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Process for bonding pad protection from damage

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 014, no. 425 (E - 0977) 13 September 1990 (1990-09-13) *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 280 (E - 1221) 23 June 1992 (1992-06-23) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9553061B1 (en) 2015-11-19 2017-01-24 Globalfoundries Inc. Wiring bond pad structures

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