JPS63220549A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS63220549A JPS63220549A JP5460887A JP5460887A JPS63220549A JP S63220549 A JPS63220549 A JP S63220549A JP 5460887 A JP5460887 A JP 5460887A JP 5460887 A JP5460887 A JP 5460887A JP S63220549 A JPS63220549 A JP S63220549A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- bump
- film
- barrier metal
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 abstract description 20
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000007747 plating Methods 0.000 abstract description 9
- 239000000463 material Substances 0.000 abstract description 6
- 230000008878 coupling Effects 0.000 abstract 3
- 238000010168 coupling process Methods 0.000 abstract 3
- 238000005859 coupling reaction Methods 0.000 abstract 3
- 238000001259 photo etching Methods 0.000 abstract 3
- 238000000206 photolithography Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002788 crimping Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、集積回路とその製法に関し、特に、集積回路
が外部との電気的接続をとるだめの、ボンディングパッ
ド上の金属堆積膜（以下バンプと称する）の構造と製法
に関わる。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit and a method for manufacturing the same, and in particular to a metal deposited film (hereinafter referred to as "metal deposited film") on a bonding pad for making an electrical connection of an integrated circuit with the outside. It concerns the structure and manufacturing method of bumps (referred to as bumps).
従来、バンプの構造は、第３図Ａに示すように、配線金
属で形成されたボンディングパッド３１上で開口部をも
つ、パシベーション膜３２の上にバリアメタル３３とメ
ッキ付着のだめの結合メタル３４が配置されていた。ま
た、製法に於いては、バリアメタルと結合メタル成膜後
、フォトリソグラフ工程により、パシベーション膜開口
部をその中に含む所望の領域で、フォトレジスト膜３５
を開口し、このフォトレジス）Ｍをマスクとして、バン
プメタル３６を電解メンキして、開口部の上にバンプを
形成している。次に第３図Ｂに示すように、フォトレジ
スト膜を除去した後、今度は、バンプメタルをマスクに
結合メタルとバリアメタルの不要部分をエツチングで除
去していた。Conventionally, the structure of a bump is as shown in FIG. 3A, in which a barrier metal 33 and a bonding metal 34 for plating are placed on a passivation film 32, which has an opening above a bonding pad 31 made of wiring metal. It was placed. In addition, in the manufacturing method, after forming barrier metal and bonding metal films, a photoresist film 35 is formed in a desired area including the passivation film opening by a photolithography process.
An opening is opened, and using this photoresist (M) as a mask, the bump metal 36 is electrolytically polished to form a bump above the opening. Next, as shown in FIG. 3B, after the photoresist film was removed, unnecessary portions of the bond metal and barrier metal were removed by etching using the bump metal as a mask.
上述した従来の技術は、バリアメタルと結合メタルを、
パシベーション膜の上に配置する構造となっているため
、バンプ形成領域を、パシベーション膜開口部とは別に
位置決めしなければならない。そのだめ、写真食刻工程
を付加しなければならず、ウェーハ製造工程が長くなシ
、ウェーハコストが上昇するという欠点がある。また、
バンプメタルのメッキマスクに用いるフォトレジスト膜
を、メッキ終了後除去することから、バンプ周辺部にオ
ーバーハング形状が不可避的に形成される、この、。下
に支えの無い構造″のため、後のリード圧着工程で、そ
の圧力により、バンプが破壊することがあるという信頼
性上の欠点がある。こめ欠点を袖９ｆｃめに、有機ポリ
マーでオーバーハング形状を充填する方法がめるが、そ
うすると、バンプ主表面上の不要な有機ポリマーを写真
食刻工程で除去するたゆに、更に工程が長くなるという
欠点がある。In the conventional technology described above, the barrier metal and the bonding metal are
Since the bump formation region is arranged on the passivation film, it is necessary to position the bump formation region separately from the passivation film opening. However, a photolithography process must be added, which lengthens the wafer manufacturing process and increases wafer cost. Also,
Since the photoresist film used as a bump metal plating mask is removed after plating is completed, an overhang shape is inevitably formed around the bump. Because of the structure with no support underneath, there is a reliability disadvantage in that the bump may be destroyed by the pressure during the lead crimping process later.The bump is overhanged with organic polymer at 9 fc of the sleeve. A method of filling the shape is considered, but this method has the disadvantage that the process becomes longer because unnecessary organic polymer on the main surface of the bump is removed by a photolithography process.
１、本発明の集積回路装置は、パシベーション膜の下で
、配線主材料金属の上に配置されたバリアメタルと結合
メタルを持つバンプ構造を有している。1. The integrated circuit device of the present invention has a bump structure having a barrier metal and a bonding metal disposed under a passivation film and on a metal as a main wiring material.
２、本発明の集積回路装−：＃法は、配線主材料金属膜
の上に、引き続いてバリアメタルと結合メタルを相次い
で成膜し、これらを１回の写真食刻工程によシバターニ
ングして配線及びボンディングパッドとなす工程および
、パシベーション膜開口後、バンプメタルを、この開口
部に対して自己整合メッキするという工程を、製造工程
の一部に有している。2. The integrated circuit device of the present invention: # method is to sequentially form a barrier metal and a bonding metal on a metal film, which is the main material for wiring, and then pattern them in a single photolithography process. A part of the manufacturing process includes a step of forming wiring and bonding pads, and a step of self-aligning plating of bump metal to the opening after opening the passivation film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図Ａから第１図Ｂまでは、本発明の第１実施例の縦
断面図である。まず第１図Ａに示す如く、シリコン基板
１上の絶縁膜２の上に、厚さ０．６μｍのアルミニウム
膜３、厚さ０．２μｍのチタン膜４と銅膜５を順次スパ
ッタ成膜した後、写真食刻工程によシ、この３層膜をパ
ターニングして、ボンディングパッドを形成する。この
時、同時に金属配線も形成される。FIGS. 1A to 1B are longitudinal sectional views of a first embodiment of the present invention. First, as shown in FIG. 1A, on an insulating film 2 on a silicon substrate 1, an aluminum film 3 with a thickness of 0.6 μm, a titanium film 4 with a thickness of 0.2 μm, and a copper film 5 were sequentially formed by sputtering. Thereafter, this three-layer film is patterned using a photolithography process to form bonding pads. At this time, metal wiring is also formed at the same time.
次に第１図Ｂに示す如く、厚さ０．６μｍのプラズマシ
リコン窒化膜６を成膜した後、ボンディングパッド上に
開口し、無電解メッキによシ、厚さ２０μｍの銅膜７を
成膜する。この時、銅が成膜されるのは、パシベーショ
ン膜開口上と、その周囲２０μｍぐらいの領域に自動的
に限定される。Next, as shown in FIG. 1B, after forming a plasma silicon nitride film 6 with a thickness of 0.6 μm, an opening is formed on the bonding pad, and a copper film 7 with a thickness of 20 μm is formed by electroless plating. To form a film. At this time, the copper film is automatically limited to the area above the passivation film opening and a region of about 20 μm around the passivation film opening.
なお、バンプに要求される厚さは、後のリード圧着工程
での圧力と機械的精度で決まる。′ｎ１度が良いほど、
また圧力が小さいほどバンプ厚は小さくて良い。リード
圧着工程での環境、条件によるが、要求されるバンプの
厚さは５〜４０μｍの範囲内である。Note that the thickness required for the bump is determined by the pressure and mechanical precision in the subsequent lead crimping process. 'n1 degree is better,
Furthermore, the smaller the pressure, the smaller the bump thickness. Depending on the environment and conditions in the lead compression process, the required thickness of the bump is within the range of 5 to 40 μm.
〔実施例２〕 第２図は本発明の第２の実施例の断面図である。[Example 2] FIG. 2 is a sectional view of a second embodiment of the invention.
バリアメタルとしてタングステンシリサイド膜４を用い
た。銅バンプ８の表面には、厚さ０．３μｍのニッケル
膜８と金膜９を無電界メッキした。A tungsten silicide film 4 was used as a barrier metal. The surface of the copper bump 8 was electrolessly plated with a nickel film 8 and a gold film 9 with a thickness of 0.3 μm.
以上説明したように本発明は、バリアメタルと結合メタ
ルをパシベーション膜の下に配置することにより、パシ
ベーション膜開口部が自動的にバンプメッキ領域を決定
するので、バンプメッキ領域決定のだめの写真食刻工程
が不要となシ、ウェーハ製造工程が短縮され、コストダ
ウンできる効果がある。As explained above, in the present invention, by placing the barrier metal and the bonding metal under the passivation film, the passivation film opening automatically determines the bump plating area. Since no process is required, the wafer manufacturing process is shortened and costs can be reduced.
次に上記効果と関連して、本発明は、パシベーション膜
開口部をバンプメッキ領域とすることにより、パシベー
ション膜自身がメッキマスク膜となシ、メッキ終了後マ
スク膜を除去する必要が無いため、バンプ周辺部にオー
バーハング形状が生ぜず、信頼度の高いバンプを形成で
きる効果がある。Next, in relation to the above effects, the present invention makes the passivation film opening part a bump plating area, so that the passivation film itself does not act as a plating mask film, and there is no need to remove the mask film after plating is completed. There is an effect that an overhang shape does not occur around the bump, and a highly reliable bump can be formed.
次に、本発明は、配線主材料金属膜、バリアメタルと結
合メタルを相次いで成膜し、１回の写真食刻工程でパタ
ーニングすることにより、バリアメタルと結合メタルを
パシベーション膜の下に備えながらも、金属配線形成工
程の長さを従来と同じに保てるという利点がある。更に
、バンプ形成との関連は薄れるが、金属配線をこのよう
な層状構造とすることにより、Ｈｉｌｌｏｃｋ の発生
や、エレクトロンマイグレーションによる断線の発生を
防止し、高信頼度の金属配線を得るという効果がある。Next, in the present invention, a metal film as a main wiring material, a barrier metal, and a bonding metal are formed one after another, and patterned in one photolithography process, thereby providing a barrier metal and a bonding metal under the passivation film. However, it has the advantage that the length of the metal wiring forming process can be kept the same as before. Furthermore, although the relationship with bump formation is weakened, by forming the metal wiring into such a layered structure, it is possible to prevent the occurrence of hillocks and disconnections due to electron migration, and to obtain highly reliable metal wiring. be.
第１図Ａと第１図Ｂは、本発明の第１の実施例の製造工
程縦断面図であり、そのうち第１図Ｂは第１実施例の構
造断面図を兼ねる。第２図は、本発明の第２の実施例の
縦断面図である。第３図Ａと第３図Ｂは、従来のバンプ
の製造程断面図であり、そのうち第３図Ｂは構造断面図
を兼ねる。
１・・・・・・シリコン基板、２・・・・・・絶縁膜、
３・・・・・・ボンディングパッド主材料金属、４・・
・・・・バリアメタル、５・・・・・・結合メタル、６
・・・・・・パシベーション膜、７・・・・・・バンプ
メタル、８・・・・・・ニッケル膜、９・・・・・・金
ｊＱ、３１・・・・・・ボンディングパッド、３２・・
・・・・パシベーションｉ、３３・・・・・・バリアメ
タル、３４・・・・・・結合メタル、３５・・・・・・
フォトレジスト膜、３６・・・・・・バンプメタル。
、！５５
茶ｊ1A and 1B are longitudinal sectional views of the manufacturing process of the first embodiment of the present invention, of which FIG. 1B also serves as a structural sectional view of the first embodiment. FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. 3A and 3B are cross-sectional views of the manufacturing process of a conventional bump, of which FIG. 3B also serves as a structural cross-sectional view. 1... Silicon substrate, 2... Insulating film,
3... Bonding pad main material metal, 4...
... Barrier metal, 5 ... Bonding metal, 6
...Passivation film, 7 ... Bump metal, 8 ... Nickel film, 9 ... Gold jQ, 31 ... Bonding pad, 32・・・
...Passivation i, 33...Barrier metal, 34...Binding metal, 35...
Photoresist film, 36... bump metal. ,! 55 Tea j
Claims (1)
ルが配置され、更にその上にパシベーション膜が配置さ
れ、かつパシベーション膜開口部で露出された上記メタ
ル層の上に、厚さ５μｍ〜４０μｍのバンプメタルが配
置された構造を有する集積回路装置。A barrier metal and a bonding metal are placed on the surface of the bonding pad, a passivation film is placed on top of the barrier metal, and a bump metal with a thickness of 5 μm to 40 μm is placed on the metal layer exposed through the passivation film opening. An integrated circuit device having an arranged structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5460887A JPS63220549A (en) | 1987-03-09 | 1987-03-09 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5460887A JPS63220549A (en) | 1987-03-09 | 1987-03-09 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63220549A true JPS63220549A (en) | 1988-09-13 |
Family
ID=12975450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5460887A Pending JPS63220549A (en) | 1987-03-09 | 1987-03-09 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63220549A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5014111A (en) * | 1987-12-08 | 1991-05-07 | Matsushita Electric Industrial Co., Ltd. | Electrical contact bump and a package provided with the same |
| JPH03209725A (en) * | 1990-01-11 | 1991-09-12 | Matsushita Electric Ind Co Ltd | Method for forming bump of semiconductor device |
| US5149671A (en) * | 1990-12-03 | 1992-09-22 | Grumman Aerospace Corporation | Method for forming multilayer indium bump contact |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4932150A (en) * | 1972-07-27 | 1974-03-23 |
-
1987
- 1987-03-09 JP JP5460887A patent/JPS63220549A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4932150A (en) * | 1972-07-27 | 1974-03-23 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5014111A (en) * | 1987-12-08 | 1991-05-07 | Matsushita Electric Industrial Co., Ltd. | Electrical contact bump and a package provided with the same |
| US5090119A (en) * | 1987-12-08 | 1992-02-25 | Matsushita Electric Industrial Co., Ltd. | Method of forming an electrical contact bump |
| JPH03209725A (en) * | 1990-01-11 | 1991-09-12 | Matsushita Electric Ind Co Ltd | Method for forming bump of semiconductor device |
| US5149671A (en) * | 1990-12-03 | 1992-09-22 | Grumman Aerospace Corporation | Method for forming multilayer indium bump contact |
| US5393696A (en) * | 1990-12-03 | 1995-02-28 | Grumman Aerosace Corp. | Method for forming multilayer indium bump contacts |
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