JPS60160645A - Laminated semiconductor integrated circuit device - Google Patents

Laminated semiconductor integrated circuit device

Info

Publication number
JPS60160645A
JPS60160645A JP59015191A JP1519184A JPS60160645A JP S60160645 A JPS60160645 A JP S60160645A JP 59015191 A JP59015191 A JP 59015191A JP 1519184 A JP1519184 A JP 1519184A JP S60160645 A JPS60160645 A JP S60160645A
Authority
JP
Japan
Prior art keywords
hole
covered
internal
conductive layer
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59015191A
Other languages
Japanese (ja)
Inventor
Mitsunori Ketsusako
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59015191A priority Critical patent/JPS60160645A/en
Publication of JPS60160645A publication Critical patent/JPS60160645A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To obtain a through-hole construction which can expect a stable and high process yield by making a construction wherein a through-hole is provided in a semiconductor substrate, the aperture of the hole on one main surface is larger than the aperture of the hole on the other main surface, the internal wall of the hole is covered with an insulation film and at least a part of the insulation film covering the internal wall is covered with a conductor. CONSTITUTION:On the surface of a semiconductor substrate 40, a group of elements has been formed by selective doping, etc. A through-hole is provided in a part of the substrate and the through-hole consists of a smaller hole 41 and a larger hole 42. The internal surface of the through-hole is covered with a comparatively thick insulation film 43 such as an oxidized film, a conductive layer 44 formed in the through-hole and the semiconductor substrate 40 are electrically insulated and simultaneously, the parasitic capacity is reduced. The conductive layer in the through-hole is extended at the boundary of the smaller hole 41 and the larger hole 42, is formed a bonding pad 45 for the bottom surface of a chip and on it, a downward solder bump 46 is formed. The conductive layer 44 in the through-hole is connected to a bonding pad 48 against the upper surface of pitch through a multilayer wiring layer 47 at the side of the surface where the group of element is formed.
JP59015191A 1984-02-01 1984-02-01 Laminated semiconductor integrated circuit device Pending JPS60160645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59015191A JPS60160645A (en) 1984-02-01 1984-02-01 Laminated semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59015191A JPS60160645A (en) 1984-02-01 1984-02-01 Laminated semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS60160645A true JPS60160645A (en) 1985-08-22

Family

ID=11881954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59015191A Pending JPS60160645A (en) 1984-02-01 1984-02-01 Laminated semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60160645A (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0198253A (en) * 1987-10-09 1989-04-17 Sharp Corp Manufacture of solid type semiconductor device
JPH01140753A (en) * 1987-11-27 1989-06-01 Sharp Corp Three-dimensional semiconductor device
JPH0442957A (en) * 1990-06-06 1992-02-13 Matsushita Electron Corp Manufacture of semiconductor integrated circuit device
WO1999033107A1 (en) * 1997-12-18 1999-07-01 Daimlerchrysler Aktiengesellschaft Semiconductor wafer with integrated individual components, method and device for the production of said semiconductor wafer
US6087719A (en) * 1997-04-25 2000-07-11 Kabushiki Kaisha Toshiba Chip for multi-chip semiconductor device and method of manufacturing the same
JP2000277689A (en) * 1999-03-29 2000-10-06 Sony Corp Semiconductor device and manufacture thereof
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP2005210048A (en) * 2003-12-22 2005-08-04 Seiko Epson Corp Manufacturing method of semiconductor device, semiconductor device, circuit board, and electronic apparatus
EP1573799A1 (en) * 2002-12-20 2005-09-14 International Business Machines Corporation Three-dimensional device fabrication method
JP2006005343A (en) * 2004-06-15 2006-01-05 Samsung Electronics Co Ltd Wafer-level chip scale package manufacturing method
US7005324B2 (en) * 2002-09-24 2006-02-28 Seiko Epson Corporation Method of fabricating stacked semiconductor chips
JP2007506278A (en) * 2003-09-15 2007-03-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｓｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Integrated electronic chip and interconnect device, and method for manufacturing the same
FR2901635A1 (en) * 2006-06-09 2007-11-30 Commissariat Energie Atomique Front and rear surfaces three dimensional electrical connection forming method for e.g. silicon substrate, involves engraving lines and trenches, and realising metallization of walls of lines and base of trenches on surfaces by layers
WO2008108970A3 (en) * 2007-03-05 2008-12-24 Tessera Inc Chips having rear contacts connected by through vias to front contacts
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
JP2010204112A (en) * 2010-04-26 2010-09-16 Hamamatsu Photonics Kk Sensor and method for manufacturing the same
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8022527B2 (en) 2006-10-10 2011-09-20 Tessera, Inc. Edge connect wafer level stacking
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

Cited By (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0198253A (en) * 1987-10-09 1989-04-17 Sharp Corp Manufacture of solid type semiconductor device
JPH01140753A (en) * 1987-11-27 1989-06-01 Sharp Corp Three-dimensional semiconductor device
JPH0442957A (en) * 1990-06-06 1992-02-13 Matsushita Electron Corp Manufacture of semiconductor integrated circuit device
US8283755B2 (en) 1996-12-02 2012-10-09 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US8174093B2 (en) 1996-12-02 2012-05-08 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US7829975B2 (en) 1996-12-02 2010-11-09 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US7335517B2 (en) 1996-12-02 2008-02-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6087719A (en) * 1997-04-25 2000-07-11 Kabushiki Kaisha Toshiba Chip for multi-chip semiconductor device and method of manufacturing the same
US6383837B1 (en) 1997-04-25 2002-05-07 Kabushiki Kaisha Toshiba Method of manufacturing a multi-chip semiconductor device effective to improve alignment
WO1999033107A1 (en) * 1997-12-18 1999-07-01 Daimlerchrysler Aktiengesellschaft Semiconductor wafer with integrated individual components, method and device for the production of said semiconductor wafer
JP2000277689A (en) * 1999-03-29 2000-10-06 Sony Corp Semiconductor device and manufacture thereof
US7180168B2 (en) 2002-09-24 2007-02-20 Seiko Epson Corporation Stacked semiconductor chips
US7005324B2 (en) * 2002-09-24 2006-02-28 Seiko Epson Corporation Method of fabricating stacked semiconductor chips
EP1573799A4 (en) * 2002-12-20 2009-02-25 Ibm Three-dimensional device fabrication method
EP1573799A1 (en) * 2002-12-20 2005-09-14 International Business Machines Corporation Three-dimensional device fabrication method
JP2007506278A (en) * 2003-09-15 2007-03-15 インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｓｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ Integrated electronic chip and interconnect device, and method for manufacturing the same
JP2005210048A (en) * 2003-12-22 2005-08-04 Seiko Epson Corp Manufacturing method of semiconductor device, semiconductor device, circuit board, and electronic apparatus
JP4706180B2 (en) * 2003-12-22 2011-06-22 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP2006005343A (en) * 2004-06-15 2006-01-05 Samsung Electronics Co Ltd Wafer-level chip scale package manufacturing method
US7675153B2 (en) 2005-02-02 2010-03-09 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
US7892890B2 (en) 2005-02-02 2011-02-22 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor chips stacked and mounted thereon and manufacturing method thereof
FR2901635A1 (en) * 2006-06-09 2007-11-30 Commissariat Energie Atomique Front and rear surfaces three dimensional electrical connection forming method for e.g. silicon substrate, involves engraving lines and trenches, and realising metallization of walls of lines and base of trenches on surfaces by layers
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8022527B2 (en) 2006-10-10 2011-09-20 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8076788B2 (en) 2006-10-10 2011-12-13 Tessera, Inc. Off-chip vias in stacked chips
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
WO2008108970A3 (en) * 2007-03-05 2008-12-24 Tessera Inc Chips having rear contacts connected by through vias to front contacts
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
JP2010204112A (en) * 2010-04-26 2010-09-16 Hamamatsu Photonics Kk Sensor and method for manufacturing the same
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips

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