JPH0442957A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH0442957A JPH0442957A JP2147845A JP14784590A JPH0442957A JP H0442957 A JPH0442957 A JP H0442957A JP 2147845 A JP2147845 A JP 2147845A JP 14784590 A JP14784590 A JP 14784590A JP H0442957 A JPH0442957 A JP H0442957A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- semiconductor
- integrated circuit
- deposited
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000000034 method Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 16
- 239000002184 metal Substances 0.000 abstract description 16
- 239000011229 interlayer Substances 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 4
- 230000002950 deficient Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 239000010410 layer Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 4
- 238000003491 array Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005219 brazing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、高密度多層配線を有する半導体集積回路装置
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device having high-density multilayer wiring.
従来の技術
半導体集積回路装置を高密度化、高集積化するため、半
導体や周辺を微細化するとともに、配線の高密度化、多
層配線化が進められている。とくに、高密度、多層配線
の集積回路装置を実現するために、配線層の加工精度の
向上、配線のパターン欠陥の減少、製造のリードタイム
（ターンアラウンド時間）の短縮が大ぎな課題になって
いる。2. Description of the Related Art In order to increase the density and integration of semiconductor integrated circuit devices, semiconductors and their surroundings have been miniaturized, and interconnections have been increased in density and multilayered. In particular, in order to realize integrated circuit devices with high-density, multilayer wiring, improving the processing accuracy of wiring layers, reducing wiring pattern defects, and shortening manufacturing lead time (turnaround time) have become major issues. There is.
従来この種の半導体装置は第３図に示すような構成であ
った。第３図は従来の３層メタル配線を有するゲートア
レイのメタル配線部分のみを模式的に示している。第３
図では、ＭＯ３型トランジスタ、容量素子などの半導体
基板に搭載される素子を省略したが、実際の半導体集積
回路装置では、種々の素子を搭載することにより表面に
凹凸が生じ、複雑な表面形状を形成している。この複雑
な形状の表面上に多層メタル配線を形成することになる
。第３図に示すようにシリコン基板４１にＭＯ３型トラ
ンジスタ、容量素子などの素子（図示せず）を形成し、
この」−に第１の層間絶縁膜４２を堆積し、この層間絶
縁膜４２に、それぞれのコンタク！・ホール（図示せず
）を形成し、第１のメタル電極配線４３を形成する。つ
ぎに、第２の層間絶縁膜４４を堆積し、第１メタル配線
４３からの接続部分にバイアスホール５１を開孔した後
、第２のメタル配線４５を形成する。ふたたび、第３の
肩−間絶縁膜４６を堆積し、第２のメタル配線４５から
の接続部分にバイアスホール５２を開孔し、第３のメタ
ル配線４７を形成する。つぎに、表面保護膜４８を堆積
する。以上のように、ゲトアレイなどの半導体集積回路
装置では、装置の高密度化、高集積化を実現するために
は、配線の多層化が必須になってきている。Conventionally, this type of semiconductor device has had a configuration as shown in FIG. FIG. 3 schematically shows only the metal wiring portion of a gate array having conventional three-layer metal wiring. Third
In the figure, elements mounted on the semiconductor substrate, such as MO3 type transistors and capacitive elements, are omitted, but in actual semiconductor integrated circuit devices, mounting various elements causes unevenness on the surface and complex surface shapes. is forming. Multilayer metal wiring is formed on the surface of this complex shape. As shown in FIG. 3, elements (not shown) such as MO3 type transistors and capacitive elements are formed on a silicon substrate 41,
A first interlayer insulating film 42 is deposited on this layer, and each contact is deposited on this interlayer insulating film 42. - Form a hole (not shown) and form the first metal electrode wiring 43. Next, a second interlayer insulating film 44 is deposited, a bias hole 51 is opened at a connection portion from the first metal wiring 43, and then a second metal wiring 45 is formed. A third shoulder-to-shoulder insulating film 46 is deposited again, and a bias hole 52 is opened at a connection portion from the second metal wiring 45 to form a third metal wiring 47. Next, a surface protection film 48 is deposited. As described above, in semiconductor integrated circuit devices such as gate arrays, multilayer wiring has become essential in order to achieve higher density and higher integration of the device.
発明が解決しようとする課題
従来の方法では、次のような問題点がある。ゲートアレ
イ、スタンダードセルなどのＡＳＩＧにおいては、集積
度を向上するため、全面敷き詰め型ゲートアレイが実用
化され、２〜３層以上のメタル配線が必須になっている
。そのため、微細化と、多層化が同時に進行し、加工技
術から見ると、高密度配線を多層化することになり、製
造工程数が増加して製造加工歩留りや、良品率の低下、
加工装置の長期にわたる信頼性を保持することの困難性
などの多くの課題がある。とくに、下地の段差形状が急
峻になり、この下地の上に２〜３層のメタル配線を行う
には、半導体装置表面の平坦化技術の確立など多（の技
術課題もある。Problems to be Solved by the Invention The conventional methods have the following problems. In ASIGs such as gate arrays and standard cells, in order to improve the degree of integration, full-coverage gate arrays have been put into practical use, and metal wiring of two to three or more layers has become essential. Therefore, miniaturization and multilayering are progressing simultaneously, and from the perspective of processing technology, high-density wiring is multilayered, the number of manufacturing steps increases, and the manufacturing processing yield and non-defective rate decrease.
There are many challenges, including the difficulty of maintaining long-term reliability of processing equipment. In particular, the step shape of the base becomes steep, and in order to form two to three layers of metal wiring on this base, there are many technical challenges, such as establishing a technique for flattening the surface of the semiconductor device.
第２の問題点として、半導体集積回路装置を製造すると
きのリードタイムの増加がある。この製造リードタイム
の増加は将来開発される複雑な大規模集積回路装置の実
現に要する開発期間を長くするので、半導体装置製造上
だけでなく開発についても大きな課題である。A second problem is an increase in lead time when manufacturing semiconductor integrated circuit devices. This increase in manufacturing lead time lengthens the development period required to realize complex large-scale integrated circuit devices that will be developed in the future, and is therefore a major issue not only in semiconductor device manufacturing but also in development.
本発明はこのような課題を解決するもので、高密度、多
層配線に伴う歩留りや良品率の低下を起さず、製造のリ
ードタイムを短縮し、開発期間を短縮する半導体集積回
路を提供することを目的とするものである。The present invention solves these problems, and provides a semiconductor integrated circuit that does not reduce yield and non-defective product rate due to high-density, multilayer wiring, shortens manufacturing lead time, and shortens development period. The purpose is to
課題を解決するための手段
この課題を解決するために本発明は、第１の半導体基板
に搭載された半導体装置の電極または配線接続の一部を
第２の半導体基板上に形成し、前記第１の半導体基板上
の半導体装置と前記第２の半導体基板上に形成された電
極または配線のそれぞれに電極パッドを設け、前記電極
パッドを相互に接続するようにしたものである。さらに
、この二つの半導体基板が対向して重ねあわされ、それ
ぞれの電極がバンプを介して接続するようにしたもので
ある。Means for Solving the Problems In order to solve this problem, the present invention forms part of the electrodes or wiring connections of the semiconductor device mounted on the first semiconductor substrate on the second semiconductor substrate, and Electrode pads are provided on each of the semiconductor device on the first semiconductor substrate and the electrodes or wiring formed on the second semiconductor substrate, and the electrode pads are connected to each other. Furthermore, these two semiconductor substrates are stacked facing each other, and their respective electrodes are connected via bumps.
作用
この構成により複雑な高密度、多層配線構造を有する半
導体集積回路装置の製造において、配線の一部を別の半
導体基板に形成し、製作した後、２つの半導体基板を接
続することにより積層数を減少させ、積層に伴う下地の
厳しい複雑な凹凸による影響をさけ、かつ、別の半導体
基板で半導体装置を造ることにより、製造歩留りを向上
させ、製造期間を大幅に短縮することとなる。Effect: When manufacturing a semiconductor integrated circuit device having a complicated, high-density, multilayer wiring structure, this configuration can be used to reduce the number of laminated layers by forming a part of the wiring on another semiconductor substrate and then connecting the two semiconductor substrates. By reducing this, avoiding the effects of severe and complex unevenness of the underlying layer due to lamination, and manufacturing semiconductor devices using separate semiconductor substrates, manufacturing yields can be improved and manufacturing periods can be significantly shortened.
実施例
本発明の半導体集積回路装置の一実施例を第１図に示す
。第１図は、本発明の半導体集積回路装置をプラスチッ
ク封止したＤＩＬ（ＤＵＡＬ ＩＮＬＩＮＥ型）パッ
ケージの要部構造を模式的に示したものである。半導体
素子を搭載した第１の半導体基板１には、電極パッドＡ
３が設けられ、この上に保護膜５が堆積され、電極部分
３のみ開孔されている。第１の半導体基板１はろう材に
よりダイパッド７に接着され、一部の電極パッド１２は
、ワイヤ９によりリード１０に接続されている。Embodiment An embodiment of the semiconductor integrated circuit device of the present invention is shown in FIG. FIG. 1 schematically shows the main structure of a DIL (Dual INLINE type) package in which a semiconductor integrated circuit device of the present invention is sealed in plastic. The first semiconductor substrate 1 on which a semiconductor element is mounted has an electrode pad A.
3 is provided, a protective film 5 is deposited thereon, and only the electrode portion 3 is opened. The first semiconductor substrate 1 is bonded to the die pad 7 using a brazing material, and some of the electrode pads 12 are connected to leads 10 by wires 9.
第２の半導体基板２には、アルミ配線のみ１〜２層形成
され、それぞれに電極パッド４が設けられている。本実
施例では、第１の半導体基板にバンプが形成され、第１
の半導体基板および第２の半導体基板は熱圧着されて１
つの半導体集積回路装置が形成される。その後このチッ
プは樹脂封止される。On the second semiconductor substrate 2, only one or two layers of aluminum wiring are formed, and an electrode pad 4 is provided on each layer. In this example, bumps are formed on the first semiconductor substrate, and the bumps are formed on the first semiconductor substrate.
The semiconductor substrate and the second semiconductor substrate are thermocompression bonded to form a
One semiconductor integrated circuit device is formed. This chip is then sealed with resin.
上記工程の詳細について、第２図（ａ）〜第２図（ｄ）
により半導体基板の製造工程を説明する。第２図（ａ）
は、第１の半導体基板の製造工程を示しており、シリコ
ン基板２１上にＭＯ８型トランジスタ、容量素子、抵抗
体などの素子を形成しく図示せず）、この上に層間絶縁
膜２２を堆積し、この層間絶縁膜２２に、それぞれの電
極を取り出すためのコンタクトホールを開孔しく図示せ
ず）、第１のアルミ配線２３を形成する。この第１のア
ルミ配線２３は、半導体集積回路装置のブロック毎に電
極を形成される。つぎに、表面保護膜２４を堆積し、電
極パッド用の窓を開孔する。つぎに。For details of the above process, see Figures 2(a) to 2(d).
The manufacturing process of the semiconductor substrate will be explained below. Figure 2(a)
1 shows the manufacturing process of the first semiconductor substrate, in which elements such as an MO8 type transistor, a capacitive element, and a resistor are formed on a silicon substrate 21 (not shown), and an interlayer insulating film 22 is deposited on this. In this interlayer insulating film 22, contact holes are opened to take out the respective electrodes (not shown), and a first aluminum wiring 23 is formed. This first aluminum wiring 23 is formed as an electrode for each block of the semiconductor integrated circuit device. Next, a surface protective film 24 is deposited and a window for an electrode pad is opened. next.
第２図（ｂ）に示すように電極パッド２３上に、例えば
、チタンタングステンからなるバリアメタル２５、金バ
ンプ２６を堆積する。As shown in FIG. 2(b), a barrier metal 25 made of titanium tungsten and gold bumps 26 are deposited on the electrode pad 23, for example.
第２図（Ｃ）に第１の半導体基板の断面構造を示す。FIG. 2(C) shows a cross-sectional structure of the first semiconductor substrate.
第２図（ａ）に示した第２の半導体基板と同じく、シリ
コン基板２１に絶縁膜２７を堆積し、この絶線膜２７に
、第２のアルミ配線２９を形成する。この上に層間絶縁
膜２８を堆積し、この層間絶縁膜２８に、バイアホール
を開孔する。つぎに、第３のアルミ配線３０を形成する
。つぎに、表面保護膜２４を堆積し、電極パッド用の窓
を開孔する。Similar to the second semiconductor substrate shown in FIG. 2(a), an insulating film 27 is deposited on a silicon substrate 21, and a second aluminum wiring 29 is formed on this insulating film 27. An interlayer insulating film 28 is deposited on this, and a via hole is opened in this interlayer insulating film 28. Next, a third aluminum wiring 30 is formed. Next, a surface protective film 24 is deposited and a window for an electrode pad is opened.
電極パッドには、第１の半導体基板と同じ（、バリアメ
タル２５をアルミ膜−Ｊ二に形成する。On the electrode pad, a barrier metal 25 is formed on the aluminum film-J2, which is the same as the first semiconductor substrate.
つぎに、ウェハ状態で作製した前記半導体基板を、半導
体装置毎に切断して第１図に示したように、ダイパッド
７に第１の半導体基板１を接着する。この後、同様に切
断された第２の半導体基板２を第２図（ｄ）に示すよう
に、第１の半導体基板１に重ね合わせ、それぞれの電極
パッド位置を合わぜ、熱圧着し、バンプ３］を合金化し
、半導体基板を接続する。このようにして２つ以上の半
導体基板から１つの半導体集積回路装置が形成される。Next, the semiconductor substrate produced in the form of a wafer is cut into semiconductor devices, and the first semiconductor substrate 1 is bonded to the die pad 7 as shown in FIG. Thereafter, as shown in FIG. 2(d), the second semiconductor substrate 2 cut in the same manner is superimposed on the first semiconductor substrate 1, the positions of the respective electrode pads are aligned, and the bumps are bonded by thermocompression. 3] is alloyed and the semiconductor substrate is connected. In this way, one semiconductor integrated circuit device is formed from two or more semiconductor substrates.
なお、本実施例では、シリコン基板の例を示したが、化
合物半導体基板でも同様に適用可能である。また、本実
施例では、金バンプにより、接続を行っているが、より
微細な電極パッドを形成し、このパッド上にピラー（柱
状突起）を形成し、これに対向する電極を合金化し、接
続することも可能であり、電極パッドの形状や、面積に
よりい（つかの接続方式がある。In this embodiment, a silicon substrate is used as an example, but a compound semiconductor substrate is also applicable. In addition, in this example, the connection is made using gold bumps, but a finer electrode pad is formed, a pillar is formed on this pad, and the electrode facing this is alloyed, and the connection is made. There are several connection methods depending on the shape and area of the electrode pad.
発明の効果
以上の実施例の説明からも明らかなように本発明の半導
体集積回路装置によれば、多層メタル配線の一部、また
は大部分を別半導体基板」二に形成できるため、複雑な
多層配線であっても、下地に形成された素子による凹凸
の影響を受けず、平坦な基板上で第２．第３のメタル配
線を形成でき、製造工程がかなり容易になる。さらに、
配線を別半導体基板で形成することが可能なため、マス
クスライス方式で、第１の半導体基板を作製し、ダイパ
ッドに接着しておけば、同時に平行して第２の半導体基
板を製作することができ、半導体集積回路装置の製造の
リードタイムを著しく短縮できる。また、半導体装置Ａ
およびＢをそれぞれ個別にデストしたのち接着すわ、ば
、良品率が向上するという効果が得られる。Effects of the Invention As is clear from the description of the embodiments above, according to the semiconductor integrated circuit device of the present invention, a part or most of the multilayer metal wiring can be formed on a separate semiconductor substrate. Even if it is a wiring, the second. A third metal wiring can be formed, and the manufacturing process is considerably simplified. moreover,
Since wiring can be formed on a separate semiconductor substrate, if a first semiconductor substrate is manufactured using a mask slicing method and bonded to a die pad, a second semiconductor substrate can be manufactured in parallel at the same time. Therefore, the lead time for manufacturing semiconductor integrated circuit devices can be significantly shortened. In addition, semiconductor device A
If B and B are bonded after being individually destasted, an effect of improving the quality of products can be obtained.
【図面の簡単な説明】
第１図は本発明の一実施例の半導体集積回路装置の断面
図、第２図（ａ）〜第２図（ｄ）は同半導体集積回路装
置の半導体基板部分の製造工程を示す断面図、第３図は
従来の半導体集積回路装置の断面図である。
１・・・・・・第１の半導体基板、２・・・・・・第２
の半導体基板、３・・・・・・電極パッドＡ、４・・・
・・・電極パットＢ、６・・・・・・バンプ、２１・・
・・・・シリコン基板、２２・・・・・・層間絶縁膜、
２３・・・・・・第１のアルミ配線、２４・・・・・・
表面保護膜、２５・・・・・・バリアメタル、２６・・
・・・・金バンプ、２７・・・・・・絶縁膜、２８・〜
・・・・層間絶縁膜、２９・・・・・・第２のアルミ配
線、３０・・・・・・第３のアルミ配線、３１・・・・
・・金バンプ。
代理人の氏名 弁理士 粟野重孝 ばか１名第
図
弔
図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2(a) to 2(d) are views of a semiconductor substrate portion of the semiconductor integrated circuit device. FIG. 3 is a cross-sectional view showing the manufacturing process, and is a cross-sectional view of a conventional semiconductor integrated circuit device. 1...First semiconductor substrate, 2...Second
semiconductor substrate, 3...electrode pad A, 4...
...Electrode pad B, 6...Bump, 21...
... Silicon substrate, 22 ... Interlayer insulating film,
23...First aluminum wiring, 24...
Surface protective film, 25... Barrier metal, 26...
...Gold bump, 27...Insulating film, 28...
...Interlayer insulating film, 29...Second aluminum wiring, 30...Third aluminum wiring, 31...
...Gold bump. Name of agent: Patent attorney Shigetaka Awano Funeral map for one idiot
Claims (1)
ぞれ半導体素子、配線および電極パッドを設け、両半導
体基板上の対応する電極パッドがバンプを介して接続さ
れるように、両半導体基板を重ね固定する半導体集積回
路装置の製造方法。Semiconductor elements, wiring, and electrode pads are provided on the first semiconductor substrate and the second semiconductor substrate, respectively, and the two semiconductor substrates are overlapped so that the corresponding electrode pads on both semiconductor substrates are connected via bumps. A method for manufacturing a fixed semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2147845A JPH0442957A (en) | 1990-06-06 | 1990-06-06 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2147845A JPH0442957A (en) | 1990-06-06 | 1990-06-06 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0442957A true JPH0442957A (en) | 1992-02-13 |
Family
ID=15439557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2147845A Pending JPH0442957A (en) | 1990-06-06 | 1990-06-06 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0442957A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109977A (en) * | 1991-10-18 | 1993-04-30 | Mitsubishi Electric Corp | Semiconductor device |
| JPH06112402A (en) * | 1992-09-29 | 1994-04-22 | Rohm Co Ltd | Semiconductor device |
| JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
| JP2002516033A (en) * | 1997-04-04 | 2002-05-28 | グレン ジェイ リーディ | 3D structure memory |
| US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
| KR100583948B1 (en) * | 2000-02-28 | 2006-05-26 | 삼성전자주식회사 | Semconductor device and method thereof |
| JP2009010436A (en) * | 1997-03-10 | 2009-01-15 | Seiko Epson Corp | Electronic component and semiconductor device, and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988864A (en) * | 1982-11-12 | 1984-05-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60160645A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Laminated semiconductor integrated circuit device |
| JPS6130059A (en) * | 1984-07-20 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6189657A (en) * | 1984-10-08 | 1986-05-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6290937A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacturing semiconductor device |
| JPS6461057A (en) * | 1987-09-01 | 1989-03-08 | Fujitsu Ltd | Semiconductor device |
-
1990
- 1990-06-06 JP JP2147845A patent/JPH0442957A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5988864A (en) * | 1982-11-12 | 1984-05-22 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS60160645A (en) * | 1984-02-01 | 1985-08-22 | Hitachi Ltd | Laminated semiconductor integrated circuit device |
| JPS6130059A (en) * | 1984-07-20 | 1986-02-12 | Nec Corp | Manufacture of semiconductor device |
| JPS6189657A (en) * | 1984-10-08 | 1986-05-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6290937A (en) * | 1985-10-17 | 1987-04-25 | Matsushita Electric Ind Co Ltd | Manufacturing semiconductor device |
| JPS6461057A (en) * | 1987-09-01 | 1989-03-08 | Fujitsu Ltd | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05109977A (en) * | 1991-10-18 | 1993-04-30 | Mitsubishi Electric Corp | Semiconductor device |
| JPH06112402A (en) * | 1992-09-29 | 1994-04-22 | Rohm Co Ltd | Semiconductor device |
| JP2009010436A (en) * | 1997-03-10 | 2009-01-15 | Seiko Epson Corp | Electronic component and semiconductor device, and manufacturing method thereof |
| JP2002516033A (en) * | 1997-04-04 | 2002-05-28 | グレン ジェイ リーディ | 3D structure memory |
| JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
| US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
| KR100583948B1 (en) * | 2000-02-28 | 2006-05-26 | 삼성전자주식회사 | Semconductor device and method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5226232A (en) | Method for forming a conductive pattern on an integrated circuit | |
| US6022758A (en) | Process for manufacturing solder leads on a semiconductor device package | |
| US6424030B2 (en) | Semiconductor memory module having double-sided stacked memory chip layout | |
| JPS6355213B2 (en) | ||
| US6570243B1 (en) | Dummy interconnects for suppressing thermally generated stress cracks | |
| JP2000232104A (en) | Chip size package | |
| JP3651346B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR100345166B1 (en) | Wafer level stack package and method of fabricating the same | |
| US20090127705A1 (en) | Semiconductor chip, method of manufacturing semiconductor chip, and semiconductor device | |
| JPH0442957A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2871636B2 (en) | LSI module and manufacturing method thereof | |
| JPH0338043A (en) | Semiconductor integrated circuit device | |
| JP2695175B2 (en) | Method for manufacturing semiconductor device | |
| JP4009380B2 (en) | Manufacturing method of semiconductor chip | |
| JP2697592B2 (en) | Pad structure of semiconductor device | |
| JPH08255810A (en) | Semiconductor device and manufacture thereof | |
| JP2006210802A (en) | Semiconductor device | |
| JP2559461B2 (en) | Method for manufacturing semiconductor device | |
| JPH0685010A (en) | Multi-chip module | |
| JPS6450543A (en) | Manufacture of semiconductor device | |
| JP2000228485A (en) | Semiconductor device of chip-on-chip structure and semiconductor chip | |
| JPH0786281A (en) | Semiconductor device and manufacture of semiconductor device | |
| JPH07153756A (en) | Semiconductor integrated circuit device | |
| JPH0661288A (en) | Wiring method for semiconductor integrated circuit | |
| JPS6091660A (en) | Manufacture of semiconductor device |