JPH08255810A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH08255810A JPH08255810A JP7056064A JP5606495A JPH08255810A JP H08255810 A JPH08255810 A JP H08255810A JP 7056064 A JP7056064 A JP 7056064A JP 5606495 A JP5606495 A JP 5606495A JP H08255810 A JPH08255810 A JP H08255810A
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- Prior art keywords
- chip
- bonding pad
- bonding
- semiconductor device
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に係り、詳しくは、半導体装置（チップ）と、半導
体装置外部とを接続するためのパッドに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a pad for connecting a semiconductor device (chip) to the outside of the semiconductor device.
【０００２】[0002]
【従来の技術】図１１は、一般的な半導体装置のチップ
５１の一部断面図である。チップ５１のおもて面側に
は、ボンディングパッド５２が形成されている。そのボ
ンディングパッド５２は、配線パターン５３を介して半
導体装置の内部回路に接続されている。2. Description of the Related Art FIG. 11 is a partial sectional view of a chip 51 of a general semiconductor device. A bonding pad 52 is formed on the front surface side of the chip 51. The bonding pad 52 is connected to the internal circuit of the semiconductor device via the wiring pattern 53.
【０００３】ボンディングパッド５２には、ボンディン
グワイヤ５４が接続されている。ボンディングワイヤ５
４は、パッケージのリードフレームや別の基板上に形成
された端子等（いずれも図示せず）に接続されている。A bonding wire 54 is connected to the bonding pad 52. Bonding wire 5
Reference numeral 4 is connected to a lead frame of the package, terminals formed on another substrate, and the like (none of which are shown).
【０００４】また、近年では、高密度実装が可能な方法
として、ＴＡＢ（Tape Automated Bonding）法や、プリ
ント配線板等の基板にチップを直接接続するフリップチ
ップボンディング法が用いられているが、これらの方法
においても、チップのおもて面にパッドが形成されてい
る。チップは、パッドを介してテープや基板に接続され
ている。In recent years, TAB (Tape Automated Bonding) method and flip chip bonding method for directly connecting a chip to a substrate such as a printed wiring board have been used as a method capable of high-density mounting. Also in this method, a pad is formed on the front surface of the chip. The chip is connected to the tape or the substrate via the pad.
【０００５】[0005]
【発明が解決しようとする課題】ところで、ボンディン
グパッド５２にボンディングワイヤ５４を接続する場
合、超音波（ＵＳ）法、熱圧着（ＴＣ）法、超音波＋熱
圧着法（ＵＴ，ＴＳ）法のいずれを用いた場合でも、基
板５５に圧力が加わる。すると、ボンディングパッド５
２の下に配線やトランジスタ等の素子を形成した場合、
ボンディング時の荷重により、配線の断線，素子の破損
などの障害が発生するおそれがある。そのため、ボンデ
ィングパッド５２を形成するパッド領域と、素子等を形
成するアクティブ領域とを分けて設計する必要がある。By the way, when connecting the bonding wire 54 to the bonding pad 52, one of the ultrasonic (US) method, the thermocompression bonding (TC) method, and the ultrasonic + thermocompression bonding method (UT, TS) method is used. Whichever is used, pressure is applied to the substrate 55. Then, the bonding pad 5
When elements such as wiring and transistors are formed under 2,
Due to the load during bonding, there is a possibility that failures such as wire breakage and element damage may occur. Therefore, it is necessary to separately design the pad area where the bonding pad 52 is formed and the active area where the element or the like is formed.
【０００６】また、ボンディングパッド５２の近傍に形
成した素子は、ボンディング時にやはり障害が発生する
おそれがある。そのため、ボンディングパッド２５とア
クティブ領域とをある程度離す必要がある。従って、チ
ップ５１おもて面におけるパッド領域が占める面積が大
きくなる。また、ボンディング時のずれを考慮すると、
ボンディングパッド５２を大きく形成する必要がある。
そのため、チップ５１おもて面におけるパッド領域の占
有面積は、更に大きくなる。Further, the element formed in the vicinity of the bonding pad 52 may still have a failure during bonding. Therefore, it is necessary to separate the bonding pad 25 and the active region to some extent. Therefore, the area occupied by the pad region on the front surface of the chip 51 becomes large. Also, considering the deviation during bonding,
It is necessary to form the bonding pad 52 large.
Therefore, the area occupied by the pad region on the front surface of the chip 51 is further increased.
【０００７】更に、半導体装置の高集積化が進むと、ア
クティブ領域に形成する素子の数が増加するとともに、
ボンディングパッド５２の数も増加する。そのため、チ
ップ５１の面積を広くする必要がある。しかしながら、
チップ５１の面積を広くすると、一枚のウェハからとれ
るチップ数が減少するので、チップ５１のコストアップ
を招くという問題がある。一方、チップの面積はそのま
までデザインルールを縮小化して素子を形成し、高集積
化に対応する方法がある。この場合には、一枚のウェハ
に形成可能なチップ数はかわらないものの、デザインル
ールを縮小化したことにより新規設備による製造コスト
の増加の他、チップ５１の歩留りが悪くなり、やはりチ
ップ５１のコストアップを招くという問題がある。Furthermore, as the degree of integration of semiconductor devices increases, the number of elements formed in the active region increases, and
The number of bonding pads 52 also increases. Therefore, it is necessary to increase the area of the chip 51. However,
When the area of the chip 51 is widened, the number of chips taken from one wafer is reduced, which causes a problem of increasing the cost of the chip 51. On the other hand, there is a method of forming a device by reducing the design rule while keeping the area of the chip as it is to cope with high integration. In this case, although the number of chips that can be formed on a single wafer does not change, the design rule is reduced, so that the manufacturing cost of the new equipment is increased and the yield of the chips 51 is deteriorated. There is a problem of increasing costs.
【０００８】このため、特開昭６２−１０４１２９号公
報に開示された半導体装置がある。この半導体装置は、
半導体チップの表裏に貫通する透孔を形成し、その透孔
を含むウェハー上に配線材料を蒸着して配線をパターニ
ングすることにより、表裏両面にパッドを形成し、両面
のパッドに対して半導体チップの両面からワイヤボンデ
ィングして形成されている。Therefore, there is a semiconductor device disclosed in Japanese Patent Laid-Open No. 62-104129. This semiconductor device
By forming through holes on the front and back of the semiconductor chip, depositing wiring material on the wafer containing the through holes and patterning the wiring, pads are formed on both the front and back sides. Is formed by wire bonding from both sides.
【０００９】しかしながら、この方法では、半導体チッ
プに貫通する透孔を形成することが困難である。また、
半導体チップ両面のパッドを透孔を介して接続している
ので、透孔を形成する際に素子等に影響を与えるおそれ
があり、透孔を形成する領域をアクティブ領域から離す
必要がある。更に、透孔と、パターニングして形成した
パッドとの位置合わせずれによるマージンを考慮しなけ
ればならないので、実際のパッドの占有面積が大きくな
り、アクティブ領域が小さくなる。従って、高集積化を
図ることが難しいという問題がある。また、透孔を形成
する必要があるので、形成が面倒である上、工程が複雑
になり、半導体装置のコストアップを招くという問題が
ある。However, according to this method, it is difficult to form a through hole penetrating the semiconductor chip. Also,
Since the pads on both sides of the semiconductor chip are connected through the through holes, the elements may be affected when forming the through holes, and the region where the through holes are formed needs to be separated from the active region. Furthermore, since the margin due to misalignment between the through hole and the pad formed by patterning must be taken into consideration, the actual area occupied by the pad becomes large and the active area becomes small. Therefore, there is a problem that it is difficult to achieve high integration. Further, since it is necessary to form the through holes, there is a problem that the formation is troublesome and the process becomes complicated, resulting in an increase in cost of the semiconductor device.
【００１０】また、実開昭６３−１４９５３０号公報に
開示された集積回路装置（図１２参照）がある。この集
積回路装置６１は、半導体結晶基板６２のおもて面側に
形成されたデバイス層６３から基板６２をとおして電極
部６４を基板６２裏面に延設するとともに、その電極部
６４の露出側端面がボンディングパッド６５に形成され
ている。しかしながら、この方法では、基板６３を貫通
した電極部６４を形成する必要があるので、やはり形成
が面倒である上、工程が複雑になり、集積回路装置６１
のコストアップを招くという問題がある。また、電極部
６４を形成するために、そのおもて面には実際に素子を
形成することができないという問題がある。There is also an integrated circuit device (see FIG. 12) disclosed in Japanese Utility Model Laid-Open No. 63-149530. In this integrated circuit device 61, an electrode portion 64 is extended from the device layer 63 formed on the front surface side of the semiconductor crystal substrate 62 through the substrate 62 to the back surface of the substrate 62, and the exposed side of the electrode portion 64 is exposed. The end face is formed on the bonding pad 65. However, in this method, since it is necessary to form the electrode portion 64 penetrating the substrate 63, the formation is complicated, and the process becomes complicated, so that the integrated circuit device 61 is formed.
However, there is a problem in that the cost increases. Further, since the electrode portion 64 is formed, there is a problem that an element cannot be actually formed on the front surface of the electrode portion 64.
【００１１】本発明は上記問題点を解決するためになさ
れたものであって、簡単な構成で高集積化を図ることが
できる半導体装置を提供することを目的とする。また、
そのような半導体装置の簡単な製造方法を提供すること
を目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of achieving high integration with a simple structure. Also,
It is an object of the present invention to provide a simple manufacturing method for such a semiconductor device.
【００１２】[0012]
【課題を解決するための手段】請求項１に記載の発明
は、チップのおもて面側から、そのチップの側面を通っ
て裏面へ延設した導電層を備えたことを要旨とする。The invention according to claim 1 is characterized in that a conductive layer is provided extending from the front surface side of the chip to the back surface through the side surface of the chip.
【００１３】請求項２に記載の発明は、チップのおもて
面側から、そのチップの側面を通って裏面まで延設され
た導電層よりなるボンディングパッドを備えたことを要
旨とする。A second aspect of the present invention is characterized in that a bonding pad made of a conductive layer is provided extending from the front surface side of the chip to the back surface through the side surface of the chip.
【００１４】請求項３に記載の発明は、チップのおもて
面側から、そのチップの側面を通って裏面まで延設され
た導電層よりなるボンディングパッドを備え、前記ボン
ディングパッドのうち、チップの裏面に形成された部分
には、チップの裏面からボンディングワイヤが接続さ
れ、チップ側面に形成された部分には、チップの側面か
らボンディングワイヤが接続されることを要旨とする。According to a third aspect of the present invention, there is provided a bonding pad made of a conductive layer extending from the front surface side of the chip to the back surface through the side surface of the chip. The gist is that the bonding wire is connected to the portion formed on the back surface of the chip from the back surface of the chip, and the bonding wire is connected to the portion formed on the side surface of the chip from the side surface of the chip.
【００１５】請求項４に記載の発明は、請求項１〜３の
うちのいずれか１項に記載の半導体装置において、前記
チップのおもて面側に形成された導電層の下に素子を形
成したことを要旨とする。According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, an element is provided under the conductive layer formed on the front surface side of the chip. The point is that it was formed.
【００１６】請求項５に記載の発明は、チップ表面のう
ち、ボンディングパッドが形成される領域に絶縁膜を形
成する工程と、前記絶縁膜表面に導電層を形成する工程
と、その導電層をパターニングすることでボンディング
パッドを形成する工程とを備えたことを要旨とする。According to a fifth aspect of the present invention, a step of forming an insulating film on a region of the chip surface where a bonding pad is formed, a step of forming a conductive layer on the surface of the insulating film, and the conductive layer are formed. And a step of forming a bonding pad by patterning.
【００１７】請求項６に記載の発明は、チップ表面のう
ち、ボンディングパッドが形成される領域に絶縁膜を形
成する工程と、前記絶縁膜表面に導電層を形成する工程
と、その導電層をパターニングすることで、チップのお
もて面側から、そのチップの側面を通って裏面まで延設
されたボンディングパッドを形成する工程とを備えたこ
とを要旨とする。According to a sixth aspect of the present invention, a step of forming an insulating film on a region of the chip surface where a bonding pad is formed, a step of forming a conductive layer on the surface of the insulating film, and the conductive layer are formed. By patterning, the step of forming a bonding pad extending from the front surface side of the chip to the back surface through the side surface of the chip is summarized.
【００１８】請求項７に記載の発明は、請求項６に記載
の半導体装置の製造方法において、前記ボンディングパ
ッドにおけるチップの裏面に形成された部分に対して、
チップの裏面からボンディングワイヤを接続する工程を
備えたことを要旨とする。According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, a portion of the bonding pad formed on the back surface of the chip is
The gist is that a step of connecting the bonding wire from the back surface of the chip is provided.
【００１９】請求項８に記載の発明は、請求項６に記載
の半導体装置の製造方法において、前記ボンディングパ
ッドにおけるチップの側面に形成された部分に対して、
チップの側面からボンディングワイヤを接続する工程を
備えたことを要旨とする。According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, a portion of the bonding pad formed on the side surface of the chip is formed.
The gist is that a step of connecting the bonding wire from the side surface of the chip is provided.
【００２０】[0020]
【作用】請求項１に記載の発明によれば、導電層は、チ
ップのおもて面側から側面を通って裏面へ延設されるの
で、容易に形成することができる。請求項２に記載の発
明によれば、導電層よりなるボンディングパッドは、チ
ップのおもて面側から側面を通って裏面まで延設される
ので、容易に形成することができる。According to the first aspect of the invention, the conductive layer can be easily formed because it extends from the front surface side of the chip to the back surface through the side surface. According to the second aspect of the present invention, the bonding pad made of the conductive layer can be easily formed since it extends from the front surface side of the chip to the back surface through the side surface.
【００２１】請求項３に記載の発明によれば、ボンディ
ングパッドは導電層よりなり、チップのおもて面側から
側面を通って裏面まで延設される。そのボンディングパ
ッドのうち、チップの裏面に形成された部分にはチップ
の裏面からボンディングワイヤが接続され、チップ側面
に形成された部分には、チップの側面からボンディング
ワイヤが接続される。そのため、チップのおもて面に
は、ボンディング時の荷重がかからない。According to the third aspect of the invention, the bonding pad is made of a conductive layer and extends from the front surface side of the chip to the back surface through the side surface. Bonding wires are connected to the portions of the bonding pad formed on the back surface of the chip from the back surface of the chip, and bonding portions of the bonding pads are connected to the side surface of the chip from the side surface of the chip. Therefore, no load is applied to the front surface of the chip during bonding.
【００２２】請求項４に記載の発明によれば、チップの
おもて面側に形成された導電層の下には素子が形成され
る。その素子にはボンディング時の荷重がかからないの
で、破損を防ぐことができる。According to the fourth aspect of the invention, the element is formed under the conductive layer formed on the front surface side of the chip. Since no load is applied to the element during bonding, damage can be prevented.
【００２３】請求項５に記載の発明によれば、チップ表
面のうち、ボンディングパッドが形成される領域には、
絶縁膜が形成される。その絶縁膜表面には、導電層が形
成される。その導電層をパターニングすることで、ボン
ディングパッドを容易に形成することができる。According to the fifth aspect of the invention, in the area where the bonding pad is formed on the chip surface,
An insulating film is formed. A conductive layer is formed on the surface of the insulating film. The bonding pad can be easily formed by patterning the conductive layer.
【００２４】請求項６に記載の発明によれば、チップ表
面のうち、ボンディングパッドが形成される領域には、
絶縁膜が形成される。その絶縁膜表面には導電層が形成
される。そして、導電層をパターニングすることで、チ
ップのおもて面側から、そのチップの側面を通って裏面
まで延設された導電層よりなるボンディングパッドを容
易に形成することができる。According to the invention described in claim 6, in the area where the bonding pad is formed on the chip surface,
An insulating film is formed. A conductive layer is formed on the surface of the insulating film. Then, by patterning the conductive layer, it is possible to easily form the bonding pad made of the conductive layer extending from the front surface side of the chip to the back surface through the side surface of the chip.
【００２５】請求項７又は８に記載の発明によれば、ボ
ンディングワイヤを容易に接続することができる。According to the invention of claim 7 or 8, the bonding wire can be easily connected.
【００２６】[0026]
【実施例】以下、本発明を具体化した一実施例を図面に
従って説明する。図１に、本実施例のチップ１の断面図
を示す。単結晶シリコン基板２上には下層の配線層３が
形成されている。下層の配線層３は、チップ１に形成さ
れた素子を構成する電極（例えばＭＯＳトランジスタの
ゲート電極）や、各素子を接続するための配線などであ
る。その配線層３の上には層間絶縁膜４が形成されてい
る。層間絶縁膜４の上には、上層の配線層５が形成され
ている。層間絶縁膜４には図示しないコンタクトホール
が開口され、そのコンタクトホールを介して上層の配線
層５と基板２又は下層の配線層３とが接続されている。
上層の配線層５の上には、層間絶縁膜６が形成されてい
る。その層間絶縁膜６には、上層の配線層５を露出する
ための開口部７が形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional view of the chip 1 of this embodiment. A lower wiring layer 3 is formed on the single crystal silicon substrate 2. The lower wiring layer 3 is an electrode (for example, a gate electrode of a MOS transistor) forming an element formed on the chip 1, wiring for connecting each element, and the like. An interlayer insulating film 4 is formed on the wiring layer 3. An upper wiring layer 5 is formed on the interlayer insulating film 4. A contact hole (not shown) is opened in the interlayer insulating film 4, and the upper wiring layer 5 and the substrate 2 or the lower wiring layer 3 are connected through the contact hole.
An interlayer insulating film 6 is formed on the upper wiring layer 5. An opening 7 for exposing the upper wiring layer 5 is formed in the interlayer insulating film 6.
【００２７】層間絶縁膜６の上には、絶縁膜８が形成さ
れている。絶縁膜８は、表裏面及び側面を含むチップ１
全体を覆うように形成されている。絶縁膜８には、上層
の配線層５とコンタクトをとるためのコンタクトホール
９が開口されている。絶縁膜８の表面には、ボンディン
グパッド１０が形成されている。そのボンディングパッ
ド１０は、コンタクトホール９を介して上層の配線層５
と接続されている。An insulating film 8 is formed on the interlayer insulating film 6. The insulating film 8 includes the chip 1 including front and back surfaces and side surfaces.
It is formed so as to cover the whole. A contact hole 9 for making contact with the upper wiring layer 5 is opened in the insulating film 8. A bonding pad 10 is formed on the surface of the insulating film 8. The bonding pad 10 is connected to the upper wiring layer 5 through the contact hole 9.
Connected with.
【００２８】図２に示すように、ボンディングパッド１
０は、チップ１のおもて面から側面を通って裏面まで延
設されている。そのボンディングパッド１０のうち、チ
ップ１の裏面に形成されている部分が裏面のボンディン
グパッド１１となり、チップ１の側面に形成されている
部分が側面のボンディングパッド１２となる。そして、
図１に示すように、裏面のボンディングパッド１１にボ
ンディングワイヤ１３を接続する。または、図１の一点
鎖線で示すように、側面のボンディングパッド１２にボ
ンディングワイヤ１４を接続する。As shown in FIG. 2, the bonding pad 1
0 extends from the front surface of the chip 1 through the side surface to the back surface. Of the bonding pad 10, the portion formed on the back surface of the chip 1 serves as the bonding pad 11 on the back surface, and the portion formed on the side surface of the chip 1 serves as the bonding pad 12 on the side surface. And
As shown in FIG. 1, the bonding wire 13 is connected to the bonding pad 11 on the back surface. Alternatively, as shown by the alternate long and short dash line in FIG. 1, the bonding wire 14 is connected to the bonding pad 12 on the side surface.
【００２９】図３及び図４に、上記のように構成したチ
ップ１を封止したパッケージ２０を示す。チップ１は、
その裏面がリードフレームのタブ２１に図示しないダイ
ボンド材により接着されている。そして、裏面に形成さ
れたボンディングパッド１１は、ボンディングワイヤ１
３によりリード２２と接続され、側面に形成されたボン
ディングパッド１２はボンディングワイヤ１４によりリ
ード２２と接続されている。そして、チップ１、タブ２
１、リード２２及びボンディングワイヤ１３が樹脂２３
により封止されてパッケージ２０が形成されている。3 and 4 show a package 20 in which the chip 1 constructed as described above is sealed. Chip 1
The back surface is adhered to the tab 21 of the lead frame by a die bond material (not shown). The bonding pad 11 formed on the back surface is the bonding wire 1
3 is connected to the lead 22, and the bonding pad 12 formed on the side surface is connected to the lead 22 by the bonding wire 14. And tip 1, tab 2
1, the lead 22 and the bonding wire 13 are resin 23
And the package 20 is formed.
【００３０】ボンディングパッド１１（ボンディングパ
ッド１０におけるチップ１の裏面に形成された部分）に
は、チップ１の裏面からボンディングワイヤ１３が接続
される。また、ボンディングパッド１２（ボンディング
パッド１０におけるチップ１の側面に形成された部分）
には、チップ１の側面からボンディングワイヤ１４が接
続される。そして、ボンディングパッド１０のうち、チ
ップ１のおもて面に形成されている部分には、ボンディ
ングワイヤ１３，１４は接続されていない。A bonding wire 13 is connected to the bonding pad 11 (a portion of the bonding pad 10 formed on the back surface of the chip 1) from the back surface of the chip 1. Further, the bonding pad 12 (a portion of the bonding pad 10 formed on the side surface of the chip 1)
The bonding wire 14 is connected to the chip 1 from the side surface of the chip 1. The bonding wires 13 and 14 are not connected to the portion of the bonding pad 10 formed on the front surface of the chip 1.
【００３１】即ち、チップ１のおもて面には、ボンディ
ングワイヤ１３，１４を接続する際の荷重が加わらな
い。従って、チップ１のおもて面全体が、素子（トラン
ジスタ，抵抗，コンデンサ等）や配線層３，５を形成す
ることができるアクティブ領域となる。その結果、チッ
プ１の面積を同じにした場合、従来より多くの素子を形
成することができるので、高集積化が可能となる。逆に
言えば、アクティブ領域を大きくすることができるの
で、デザインルールを緩和することにより、従来の設備
が使用可能となって、コストアップを抑えることができ
る。That is, no load is applied to the front surface of the chip 1 when connecting the bonding wires 13 and 14. Therefore, the entire front surface of the chip 1 becomes an active region where elements (transistors, resistors, capacitors, etc.) and wiring layers 3 and 5 can be formed. As a result, when the areas of the chips 1 are the same, more elements can be formed than in the conventional case, and high integration is possible. Conversely, since the active area can be enlarged, the conventional equipment can be used by relaxing the design rule, and the cost increase can be suppressed.
【００３２】また、ボンディングパッド１０のうち、チ
ップ１のおもて面に形成されている部分には、ボンディ
ングワイヤ１３，１４を接続する際の荷重が加わらな
い。従って、チップ１の周縁部のみならず、チップ１の
おもて面の任意の場所において、絶縁膜８にコンタクト
ホール９を形成して上層の配線層５とボンディングパッ
ド１０とを接続する。そして、そのボンディングパッド
１０を側面を通って裏面まで延設してボンディングパッ
ド１１，１２を形成し、そのボンディングパッド１１，
１２を介してチップ１の外部と接続することができる。
その結果、チップ１の周縁部まで配線層３，５を形成す
る必要がないので、チップ１の設計が容易になる。Further, no load is applied to the portion of the bonding pad 10 formed on the front surface of the chip 1 when connecting the bonding wires 13 and 14. Therefore, the contact hole 9 is formed in the insulating film 8 not only at the peripheral portion of the chip 1 but also at an arbitrary position on the front surface of the chip 1 to connect the wiring layer 5 of the upper layer and the bonding pad 10. Then, the bonding pad 10 is extended to the back surface through the side surface to form the bonding pads 11 and 12, and the bonding pad 11 and
It can be connected to the outside of the chip 1 via 12.
As a result, it is not necessary to form the wiring layers 3 and 5 up to the peripheral portion of the chip 1, so that the chip 1 can be easily designed.
【００３３】一方、チップ１の裏面又は側面からボンデ
ィングワイヤ１３，１４を接続する際の荷重は、チップ
１のおもて面には直接加わらない。従って、チップ１の
裏面及び側面全体からボンディングワイヤ１３，１４を
接続することができる。即ち、チップ１の裏面及び側面
全体にボンディングパッド１１，１２を形成することが
できる。そのため、半導体装置の高集積化が進んでボン
ディングパッド１１，１２の数が増加しても、チップ１
の裏面及び側面全体にボンディングパッド１１，１２を
形成することができるので、チップ１の面積を広くする
必要はない。従って、一枚のウェハからとれるチップ数
はかわらないので、チップ１のコストアップを抑えるこ
とができる。On the other hand, the load when connecting the bonding wires 13 and 14 from the back surface or the side surface of the chip 1 is not directly applied to the front surface of the chip 1. Therefore, the bonding wires 13 and 14 can be connected from the entire back surface and side surfaces of the chip 1. That is, the bonding pads 11 and 12 can be formed on the entire back surface and side surfaces of the chip 1. Therefore, even if the number of bonding pads 11 and 12 increases as the integration of semiconductor devices increases, the chip 1
Since the bonding pads 11 and 12 can be formed on the entire back and side surfaces of the chip 1, it is not necessary to increase the area of the chip 1. Therefore, the number of chips that can be obtained from one wafer does not change, and the cost increase of the chip 1 can be suppressed.
【００３４】また、従来の半導体装置（特開昭６２−１
０４１２９号公報）のように、半導体チップに透孔を形
成する必要がない。そのため、素子に影響を与えること
なくボンディングパッド１１，１２を容易に形成でき、
チップ１のコストアップを抑えることができる。また、
透孔を形成する必要がないので、素子とボンディングパ
ッド１０とを離す必要がない。チップ１裏面及び側面の
任意の場所（例えばチップ１のおもて面に形成した素子
の部分に対応したチップ１の裏面の部分）にもボンディ
ングパッド１１，１２を形成することができる。更に、
透孔を形成しないので、位置合わせずれを考慮する必要
がなく、ボンディングパッド１０の占める面積を小さく
することができる。Further, a conventional semiconductor device (Japanese Patent Laid-Open No. 62-1 / 1987)
It is not necessary to form a through hole in the semiconductor chip as in Japanese Patent No. 04129). Therefore, the bonding pads 11 and 12 can be easily formed without affecting the element,
The cost increase of the chip 1 can be suppressed. Also,
Since it is not necessary to form a through hole, it is not necessary to separate the element from the bonding pad 10. Bonding pads 11 and 12 can be formed on arbitrary locations on the back surface and side surfaces of the chip 1 (for example, the back surface portion of the chip 1 corresponding to the element portion formed on the front surface of the chip 1). Furthermore,
Since the through hole is not formed, it is not necessary to consider the positional deviation, and the area occupied by the bonding pad 10 can be reduced.
【００３５】更に、従来の集積回路装置６１（実開昭６
３−１４９５３０号公報、図１２参照）のように、半導
体結晶基板６２を貫通する電極部６４を形成する必要が
ない。そのため、ボンディングパッド１１，１２を容易
に形成できる。Further, the conventional integrated circuit device 61 (Shokaisho 6)
It is not necessary to form the electrode portion 64 penetrating the semiconductor crystal substrate 62 as in Japanese Patent Laid-Open No. 3-149530, FIG. Therefore, the bonding pads 11 and 12 can be easily formed.
【００３６】尚、下層の配線層３は、例えば、ポリシリ
コンにより形成されたＭＯＳトランジスタのゲート電極
や、金属やポリシリコン等の配線層であって、材質・形
状はどのようなものでもよい。また、層間絶縁膜４，６
は、シリコン酸化膜、シリコン窒化膜、シリケートガラ
ス（ＰＳＧ，ＢＰＳＧ，ＮＳＧなど）等であって、材質
はどのようなものでもよい。更には、上層の配線層５
は、単一の金属配線層、またはＴｉ膜，ＴｉＮ膜等の複
数の層からなる金属配線層等であって、材質・構成・形
状はどのようなものでもよい。The lower wiring layer 3 is, for example, a gate electrode of a MOS transistor formed of polysilicon, a wiring layer of metal, polysilicon or the like, and may be of any material and shape. In addition, the interlayer insulating films 4 and 6
Is a silicon oxide film, a silicon nitride film, silicate glass (PSG, BPSG, NSG, etc.) or the like, and may be made of any material. Furthermore, the upper wiring layer 5
Is a single metal wiring layer or a metal wiring layer composed of a plurality of layers such as a Ti film and a TiN film, and may be of any material, structure and shape.
【００３７】また、ボンディングワイヤ１３，１４の接
続方法は、超音波（ＵＳ）法、熱圧着（ＴＣ）法、熱圧
着＋超音波（ＵＴ，ＴＳ）法等のいずれの方法を用いて
もよい。また、そのワイヤ１３，１４の先端は、ウェッ
ジボンディング，ネイルヘッドボンディング等のいずれ
の方法を用いて形成してもよい。The bonding wires 13 and 14 may be connected by any of ultrasonic wave (US) method, thermocompression bonding (TC) method, thermocompression bonding + ultrasonic (UT, TS) method and the like. . The tips of the wires 13 and 14 may be formed by any method such as wedge bonding or nail head bonding.
【００３８】次に、本実施例の製造方法を図面に従って
順次説明する。 工程１（図５参照）；ウェハ（図示せず）上に、下層の
配線層３，層間絶縁膜４，上層の配線層５，層間絶縁膜
６を順次形成し、そのウェハに対してバックグラインド
及びダイシング工程を行って、チップ１を形成する。そ
のチップ１の表裏面及び側面に絶縁膜８を形成する。絶
縁膜８の材質としては、シリコン酸化膜、有機絶縁膜、
などがある。シリコン酸化膜を形成するには、ＣＶＤ法
を用いたり、ＳＯＧを塗布したりするという方法を用い
る。有機絶縁膜を形成するには、例えばポリイミド樹脂
を塗布する方法を用いる。Next, the manufacturing method of this embodiment will be sequentially described with reference to the drawings. Step 1 (see FIG. 5): A lower wiring layer 3, an interlayer insulating film 4, an upper wiring layer 5, and an interlayer insulating film 6 are sequentially formed on a wafer (not shown), and back grinding is performed on the wafer. Then, a dicing process is performed to form the chip 1. An insulating film 8 is formed on the front and back surfaces and side surfaces of the chip 1. As the material of the insulating film 8, a silicon oxide film, an organic insulating film,
and so on. To form a silicon oxide film, a CVD method or a method of applying SOG is used. To form the organic insulating film, for example, a method of applying a polyimide resin is used.
【００３９】工程２（図６参照）；絶縁膜８上にレジス
トを塗布した後、露光工程及び現像工程を経てレジスト
パターン４１を形成する。露光工程では、紫外線を微小
径のビーム状にして走査し、チップ１を回転させること
で表裏面及び側面を露光させる。Step 2 (see FIG. 6): After applying a resist on the insulating film 8, a resist pattern 41 is formed through an exposure step and a development step. In the exposure step, ultraviolet rays are formed into a beam having a small diameter and scanned, and the chip 1 is rotated to expose the front and back surfaces and side surfaces.
【００４０】工程３（図７参照）；レジストパターン４
１をエッチングマスクとし、エッチングにより絶縁膜８
を除去して、コンタクトホール９を形成して上層の配線
層５の一部を露出させる。ここで、コンタクトホール９
の径は、絶縁膜８の膜厚に比べて十分に大きい。そのた
め、エッチング方法としては、等方性又は異方性エッチ
ングのいずれの方法を用いてもよい。次に、レジストパ
ターン４１を除去する。Step 3 (see FIG. 7): Resist pattern 4
1 as an etching mask and the insulating film 8
Is removed to form a contact hole 9 to expose a part of the upper wiring layer 5. Here, contact hole 9
Is sufficiently larger than the thickness of the insulating film 8. Therefore, as the etching method, either isotropic or anisotropic etching may be used. Next, the resist pattern 41 is removed.
【００４１】工程４（図８参照）；アルミニウム（Ａ
ｌ）や銅（Ｃｕ）等の材料をＰＶＤ（蒸着，スパッタな
ど）法を用いてチップ１の全面に堆積して、導電層４２
を形成する。Step 4 (see FIG. 8); Aluminum (A
1) or copper (Cu) or the like is deposited on the entire surface of the chip 1 by using the PVD (vapor deposition, sputtering, etc.) method, and the conductive layer 42 is formed.
To form.
【００４２】工程５（図９参照）；導電層４２上にレジ
ストを塗布した後、露光工程及び現像工程を経てレジス
トパターン４３を形成する。露光工程では、工程２と同
様に、紫外線を微小径のビーム状にして走査し、チップ
１を回転させることで表裏面及び側面を露光させる。Step 5 (see FIG. 9): After applying a resist on the conductive layer 42, a resist pattern 43 is formed through an exposure step and a development step. In the exposure step, as in step 2, ultraviolet rays are formed into a beam having a small diameter and scanned, and the chip 1 is rotated to expose the front and back surfaces and side surfaces.
【００４３】工程６（図１０参照）；レジストパターン
４３をエッチングマスクとして導電層４２をエッチング
して、チップ１のおもて面側から側面を通って裏面に延
設されたボンディングパッド１０を形成する。このボン
ディングパッド１０のうち、チップ１の裏面に形成され
た部分が裏面のボンディングパッド１１となり、チップ
１の側面に形成された部分が側面のボンディングパッド
１２となる。ここで、ボンディングパッド１０の寸法形
状に比べてその膜厚は十分に小さい。そのため、エッチ
ング方法としては、等方性又は異方性エッチングのいず
れの方法を用いてもよい。Step 6 (see FIG. 10): The conductive layer 42 is etched by using the resist pattern 43 as an etching mask to form the bonding pad 10 extending from the front surface side of the chip 1 to the back surface thereof. To do. Of the bonding pad 10, the portion formed on the back surface of the chip 1 serves as the back surface bonding pad 11, and the portion formed on the side surface of the chip 1 serves as the side bonding pad 12. Here, the film thickness is sufficiently smaller than the dimension and shape of the bonding pad 10. Therefore, as the etching method, either isotropic or anisotropic etching may be used.
【００４４】尚、上記実施例は以下のように変更しても
よく、その場合にも同様の作用及び効果を得ることがで
きる。 １）ボンディングパッド１１，１２にバンプを形成し、
ＴＡＢ法またはフリップチップ法でチップ１を実装す
る。The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained. 1) Form bumps on the bonding pads 11 and 12,
The chip 1 is mounted by the TAB method or the flip chip method.
【００４５】２）工程４において、先ずボンディングパ
ッド１０以外の領域に、レジストパターンを形成する。
次に、無電解メッキ法や選択ＣＶＤ法等を用いて、選択
的にボンディングパッド１０を形成する。2) In step 4, first, a resist pattern is formed in a region other than the bonding pad 10.
Next, the bonding pad 10 is selectively formed by using an electroless plating method or a selective CVD method.
【００４６】３）工程５において、レジストに代えて、
ＵＶ硬化樹脂を用いる。また、曲面に印刷可能な印刷技
術を用いて、チップ１の全面に印刷してエッチングマス
クとする。3) In step 5, instead of the resist,
UV curable resin is used. Further, by using a printing technique capable of printing on a curved surface, the entire surface of the chip 1 is printed to form an etching mask.
【００４７】４）ボンディングパッド１０として、ポリ
ピロール，ポリアニリン，ポリアセン等の有機導電材料
を用いる。この場合、ボンディングワイヤ１３，１４に
代えて、接着性導電剤（例えば、イオタイトＢ−３０Ｔ
（イオンケミー株式会社製）等）を用いて接続する。4) As the bonding pad 10, an organic conductive material such as polypyrrole, polyaniline, polyacene or the like is used. In this case, instead of the bonding wires 13 and 14, an adhesive conductive agent (for example, Iotite B-30T) is used.
(Manufactured by Aeon Chemie Co., Ltd.) and the like.
【００４８】５）絶縁膜８を、チップ表面のうちボンデ
ィングパッド１０が形成される部分（例えば、上記実施
例ではチップ１の周縁部表裏面及び側面）にのみ形成す
る。尚、図３，４では、チップ１の裏面の周縁部にだけ
ボンディングパッド１１を設けるようにしてある。しか
し、チップ１の裏面全体にボンディングパッド１１を設
けるようにしてもよい。その場合は、チップ１の周縁部
のおもて面，側面及び裏面全体に絶縁膜８を形成すれば
よい。5) The insulating film 8 is formed only on the portion of the chip surface where the bonding pad 10 is formed (for example, the front and back surfaces and the side surfaces of the peripheral portion of the chip 1 in the above embodiment). 3 and 4, the bonding pad 11 is provided only on the peripheral portion of the back surface of the chip 1. However, the bonding pad 11 may be provided on the entire back surface of the chip 1. In that case, the insulating film 8 may be formed on the entire front surface, side surface, and back surface of the peripheral portion of the chip 1.
【００４９】以上、本発明の一実施例について説明した
が、上記実施例から把握できる請求項以外の技術的思想
について、以下にそれらの効果とともに記載する。 イ）請求項６に記載の半導体装置の製造方法において、
チップ１のおもて面側に形成された導電層の下に素子を
形成する工程を備えた半導体装置の製造方法。この構成
により、チップ１を容易に形成することができる。Although one embodiment of the present invention has been described above, technical ideas other than the claims which can be understood from the above embodiment will be described below together with their effects. B) In the method of manufacturing a semiconductor device according to claim 6,
A method of manufacturing a semiconductor device, comprising a step of forming an element under a conductive layer formed on a front surface side of a chip 1. With this configuration, the chip 1 can be easily formed.
【００５０】ロ）請求項６に記載の半導体装置の製造方
法において、前記ボンディングパッド１０におけるチッ
プ１の裏面に形成された部分１１に対して、チップ１の
裏面からボンディングワイヤ１３を接続する工程と、チ
ップ１の側面に形成された部分１２に対して、チップ１
の側面からボンディングワイヤ１４を接続する工程を備
えた半導体装置の製造方法。この構成により、チップ１
のボンディングパッド１１，１２に対してボンディング
ワイヤ１３，１４を容易に接続できる。(B) In the method of manufacturing a semiconductor device according to claim 6, a step of connecting a bonding wire 13 from the back surface of the chip 1 to a portion 11 of the bonding pad 10 formed on the back surface of the chip 1. , The chip 1 with respect to the portion 12 formed on the side surface of the chip 1
A method of manufacturing a semiconductor device, comprising the step of connecting the bonding wire 14 from the side surface of the semiconductor device. With this configuration, the chip 1
The bonding wires 13 and 14 can be easily connected to the bonding pads 11 and 12.
【００５１】尚、本明細書において、発明の構成に係る
部材は以下のように定義されるものとする。チップと
は、シリコン基板を用いたものだけでなく、ガリウムヒ
素等のシリコン以外の半導体基板、表面に半導体薄膜が
形成された石英やガラス等の絶縁基板、等を用いたもの
を含むものとする。In the present specification, members relating to the constitution of the invention are defined as follows. The chip includes not only those using a silicon substrate but also those using a semiconductor substrate other than silicon such as gallium arsenide, an insulating substrate such as quartz or glass having a semiconductor thin film formed on the surface thereof, and the like.
【００５２】[0052]
【発明の効果】以上詳述したように本発明によれば、簡
単な構成で高集積化を図ることが可能な半導体装置を提
供することができる。また、そのような半導体装置の簡
単な製造方法を提供することができる。As described above in detail, according to the present invention, it is possible to provide a semiconductor device having a simple structure and high integration. Further, it is possible to provide a simple manufacturing method of such a semiconductor device.
【図１】 本発明を具体化した一実施例の半導体装置の
一部断面図。FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】 一実施例の半導体装置の一部斜視図。FIG. 2 is a partial perspective view of a semiconductor device according to an embodiment.
【図３】 パッケージングした半導体装置の概略平面
図。FIG. 3 is a schematic plan view of a packaged semiconductor device.
【図４】 図３のＡ−Ａ線断面図。FIG. 4 is a sectional view taken along line AA of FIG.
【図５】 製造方法を説明するための一部断面図。FIG. 5 is a partial cross-sectional view for explaining the manufacturing method.
【図６】 製造方法を説明するための一部断面図。FIG. 6 is a partial cross-sectional view for explaining the manufacturing method.
【図７】 製造方法を説明するための一部断面図。FIG. 7 is a partial cross-sectional view for explaining the manufacturing method.
【図８】 製造方法を説明するための一部断面図。FIG. 8 is a partial cross-sectional view for explaining the manufacturing method.
【図９】 製造方法を説明するための一部断面図。FIG. 9 is a partial cross-sectional view for explaining the manufacturing method.
【図１０】 製造方法を説明するための一部断面図。FIG. 10 is a partial cross-sectional view for explaining the manufacturing method.
【図１１】 従来の半導体装置の一部断面図。FIG. 11 is a partial cross-sectional view of a conventional semiconductor device.
【図１２】 従来の半導体装置の一部断面図。FIG. 12 is a partial cross-sectional view of a conventional semiconductor device.
１ チップ ８ 絶縁膜 １０ 導電層としてのボンディングパッド １１ （第１の）ボンディングパッド １２ （第２の）ボンディングパッド １３，１４ ボンディングワイヤ ４２ 導電層 1 Chip 8 Insulating Film 10 Bonding Pad as Conductive Layer 11 (First) Bonding Pad 12 (Second) Bonding Pad 13, 14 Bonding Wire 42 Conductive Layer
Claims (8)
ップ（１）の側面を通って裏面へ延設された導電層（１
０）を備えた半導体装置。1. A conductive layer (1) extending from the front surface side of the chip (1) to the back surface through the side surface of the chip (1).
0) equipped with a semiconductor device.
ップ（１）の側面を通って裏面まで延設された導電層よ
りなるボンディングパッド（１０）を備えた半導体装
置。2. A semiconductor device comprising a bonding pad (10) made of a conductive layer extending from the front surface side of the chip (1) through the side surface of the chip (1) to the back surface.
ップ（１）の側面を通って裏面まで延設された導電層よ
りなるボンディングパッド（１０）を備え、 前記ボンディングパッド（１０）のうち、チップ（１）
の裏面に形成された部分には、チップ（１）の裏面から
ボンディングワイヤ（１３）が接続され、チップ（１）
側面に形成された部分には、チップ（１）の側面からボ
ンディングワイヤ（１４）が接続される半導体装置。3. A bonding pad (10) comprising a conductive layer extending from the front surface side of the chip (1) through the side surface of the chip (1) to the back surface, the bonding pad (10) being provided. ) Out of the chips (1)
The bonding wire (13) is connected to the portion formed on the back surface of the chip (1) from the back surface of the chip (1).
A semiconductor device in which a bonding wire (14) is connected to the portion formed on the side surface from the side surface of the chip (1).
載の半導体装置において、 前記チップ（１）のおもて面側に形成された導電層の下
に素子を形成した半導体装置。4. The semiconductor device according to claim 1, wherein an element is formed below a conductive layer formed on a front surface side of the chip (1). .
パッド（１０）が形成される領域に絶縁膜（８）を形成
する工程と、 前記絶縁膜表面に導電層（４２）を形成する工程と、 その導電層をパターニングすることでボンディングパッ
ド（１０）を形成する工程とを備えた半導体装置の製造
方法。5. A step of forming an insulating film (8) on a region of the surface of the chip (1) where a bonding pad (10) is formed, and a step of forming a conductive layer (42) on the surface of the insulating film. And a step of forming a bonding pad (10) by patterning the conductive layer.
パッド（１０）が形成される領域に絶縁膜（８）を形成
する工程と、 前記絶縁膜表面に導電層（４２）を形成する工程と、 その導電層をパターニングすることで、チップ（１）の
おもて面側から、そのチップ（１）の側面を通って裏面
まで延設されたボンディングパッド（１０）を形成する
工程とを備えた半導体装置の製造方法。6. A step of forming an insulating film (8) on a region of the surface of the chip (1) where a bonding pad (10) is formed, and a step of forming a conductive layer (42) on the surface of the insulating film. Patterning the conductive layer to form a bonding pad (10) extending from the front surface side of the chip (1) to the back surface through the side surface of the chip (1). For manufacturing a semiconductor device.
において、 前記ボンディングパッド（１０）におけるチップ（１）
の裏面に形成された部分（１１）に対して、チップ
（１）の裏面からボンディングワイヤ（１３）を接続す
る工程を備えた半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the chip (1) in the bonding pad (10).
A method of manufacturing a semiconductor device, comprising a step of connecting a bonding wire (13) from the back surface of the chip (1) to a portion (11) formed on the back surface of the semiconductor device.
において、 前記ボンディングパッド（１０）におけるチップ（１）
の側面に形成された部分（１２）に対して、チップ
（１）の側面からボンディングワイヤ（１４）を接続す
る工程を備えた半導体装置の製造方法。8. The method of manufacturing a semiconductor device according to claim 6, wherein the chip (1) in the bonding pad (10).
A method of manufacturing a semiconductor device, comprising a step of connecting a bonding wire (14) from the side surface of the chip (1) to a portion (12) formed on the side surface of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606495A JP3599813B2 (en) | 1995-03-15 | 1995-03-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5606495A JP3599813B2 (en) | 1995-03-15 | 1995-03-15 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08255810A true JPH08255810A (en) | 1996-10-01 |
| JP3599813B2 JP3599813B2 (en) | 2004-12-08 |
Family
ID=13016663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5606495A Expired - Fee Related JP3599813B2 (en) | 1995-03-15 | 1995-03-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3599813B2 (en) |
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| WO2004079822A1 (en) * | 2003-03-07 | 2004-09-16 | Koninklijke Philips Electronics N.V. | Semiconductor device, semiconductor body and method of manufacturing thereof |
| JP2008112752A (en) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip |
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|---|---|---|---|---|
| JP2003068736A (en) * | 2001-08-24 | 2003-03-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| WO2004079822A1 (en) * | 2003-03-07 | 2004-09-16 | Koninklijke Philips Electronics N.V. | Semiconductor device, semiconductor body and method of manufacturing thereof |
| US7196409B2 (en) | 2003-03-07 | 2007-03-27 | Nxp B.V. | Semiconductor device, semiconductor body and method of manufacturing thereof |
| CN100401510C (en) * | 2003-03-07 | 2008-07-09 | Nxp股份有限公司 | Semiconductor device, semiconductor body and method of manufacturing thereof |
| JP2009530633A (en) * | 2006-03-20 | 2009-08-27 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | System-in-package platform for electronic microfluidic devices |
| JP2008112752A (en) * | 2006-10-27 | 2008-05-15 | Mitsubishi Heavy Ind Ltd | Semiconductor device, inspection instrument, manufacturing method of semiconductor device, and manufacturing method of chip |
| JP2009212458A (en) * | 2008-03-06 | 2009-09-17 | Sumitomo Electric Ind Ltd | Semiconductor device, electronic apparatus and method of manufacturing the same |
| WO2013143724A1 (en) * | 2012-03-30 | 2013-10-03 | Robert Bosch Gmbh | Method for producing at least one contacting surface of an element and sensor for recording a directional component of a directed measured value |
| FR2988905A1 (en) * | 2012-03-30 | 2013-10-04 | Bosch Gmbh Robert | METHOD FOR PRODUCING A COMPONENT HAVING A CONTACT SURFACE AND SENSOR FOR RECEIVING A DIRECTIONAL COMPONENT OF DIRECTIONAL MEASUREMENT SIZE |
| CN103928554A (en) * | 2014-04-21 | 2014-07-16 | 上海空间电源研究所 | Connecting method for solar cell array front and back face circuits |
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