KR100583948B1 - Semconductor device and method thereof - Google Patents

Semconductor device and method thereof Download PDF

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KR100583948B1
KR100583948B1 KR1020000009791A KR20000009791A KR100583948B1 KR 100583948 B1 KR100583948 B1 KR 100583948B1 KR 1020000009791 A KR1020000009791 A KR 1020000009791A KR 20000009791 A KR20000009791 A KR 20000009791A KR 100583948 B1 KR100583948 B1 KR 100583948B1
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semiconductor substrate
bumps
active elements
metal wiring
forming
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KR1020000009791A
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KR20010084610A (en
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변진현
최영수
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삼성전자주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치 및 그 제조방법에 관한 것으로서, 특히 본 발명의 장치는 복수의 능동소자들이 표면에 형성되고, 이들 능동소자들을 연결하기 위한 1차 금속배선이 형성되고, 1차 금속배선 상에 형성된 복수의 제 1 범프들을 가진 제 1 반도체 기판과, 제 1 반도체 기판 상에 형성된 복수의 능동소자들의 상호 연결 및 외부 연결을 위한 다층 금속배선들이 형성되고, 최상층에는 상기 제 1 범프들과 대응되는 복수의 제 2 펌프들이 형성된 제 2 반도체 기판을 포함한다. 제 1 반도체 기판의 제 1 범프들과 상기 제 2 반도체 기판의 제 2 범프들이 서로 대응하는 것들끼리 마주보도록 접촉한다. 따라서, 본 발명에서는 능동소자와 능동소자들을 상호 연결하기 위한 다층 금속배선들을 각각 다른 반도체 기판 상에서 제조한 다음에 이들을 마주보도록 접촉하여 집적회로 칩을 형성함으로써, 공정기간을 단축시킬 수 있고, 수율을 향상시킬 수 있어서 코스트를 절감할 수 있다. 또한, 다층 배선이 형성되지 않은 상태에서 능동소자들이 형성된 기판만을 테스트할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the device of the present invention has a plurality of active elements formed on a surface thereof, and a primary metal wiring for connecting these active elements is formed, A first semiconductor substrate having a plurality of first bumps formed therein, and multilayer metal interconnections for interconnection and external connection of a plurality of active elements formed on the first semiconductor substrate are formed, and an uppermost layer corresponding to the first bumps is formed. And a second semiconductor substrate on which a plurality of second pumps are formed. The first bumps of the first semiconductor substrate and the second bumps of the second semiconductor substrate are in contact with each other so as to face each other. Accordingly, in the present invention, by fabricating multi-layered metal wirings for interconnecting the active elements and the active elements on different semiconductor substrates, and then contacting them to face each other to form an integrated circuit chip, the process period can be shortened, and the yield can be reduced. The cost can be reduced by improving. In addition, it is possible to test only a substrate on which active devices are formed without a multilayer wiring.

Description

반도체 장치 및 그 제조방법{SEMCONDUCTOR DEVICE AND METHOD THEREOF}Semiconductor device and manufacturing method therefor {SEMCONDUCTOR DEVICE AND METHOD THEREOF}

도 1은 본 발명에 의한 능동소자가 형성된 제 1 반도체 기판을 나타낸 단면도.1 is a cross-sectional view showing a first semiconductor substrate on which an active device according to the present invention is formed.

도 2는 본 발명에 의한 다층 금속배선이 형성된 제 2 반도체 기판을 나타낸 단면도.Figure 2 is a cross-sectional view showing a second semiconductor substrate formed with a multi-layer metal wiring according to the present invention.

도 3은 제 1 반도체 기판과 제 2 반도체 기판을 마주보도록 접촉한 상태의 단면도. 3 is a cross-sectional view of a state in which the first semiconductor substrate and the second semiconductor substrate are in contact with each other.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10, 40 : 반도체 기판 12 : 필드 산화막10, 40: semiconductor substrate 12: field oxide film

14 : 게이트 산화막 16 : 게이트 전극14 gate oxide film 16 gate electrode

18 : 제 1 불순물영역 20 ; 스페이서18: first impurity region 20; Spacer

22 : 제 2 불순물 영역 24 : 열산화막22: second impurity region 24: thermal oxide film

26, 46 : 층간절연막 28 : 콘택홀26, 46 interlayer insulating film 28: contact hole

30, 44, 46 : 금속배선 32, 50 : 보호층30, 44, 46: metal wiring 32, 50: protective layer

34, 52 : 비아 36, 54 : 제 1 범프34, 52: Via 36, 54: First bump

42 : 절연막 60 : 리드 프레임의 내부 리드 42: insulating film 60: internal lead of lead frame

본 발명은 반도체 장치 및 그 제조방법에 관한 것으로서, 특히 능동소자와 다층배선을 각각 다른 반도체 기판 상에 형성한 다음에 이들을 마주보도록 연결하여 하나의 완성된 집적화로 칩을 형성함으로써 공정기간의 단축, 수율 증대, 효율적인 테스트를 할 수 있는 반도체 장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the active element and the multilayer wiring are formed on different semiconductor substrates, and then connected to face each other, thereby shortening the process period by forming a chip with one completed integration. The present invention relates to a semiconductor device capable of increasing yield and efficient testing, and a method of manufacturing the same.

일반적으로 반도체 장치는 하나의 반도체기판 상에 먼저 능동소자를 형성하고, 그 위에 다층으로 금속배선을 형성하여 능동소자들의 상호 연결 및 외부 연결을 하여 이루어진다. In general, a semiconductor device is formed by first forming an active element on a semiconductor substrate and then forming metal wirings in multiple layers thereon to interconnect and externally connect the active elements.

고집적화로 각 능동소자들의 사이즈가 미세해지고, 그 구조가 복잡해짐에 따라 금속배선도 2층에서 4층 또는 5층으로 증가되고 있다. 특히 금속배선은 하부 절연층의 스텝 커버리지가 나쁠 경우에는 쇼트 또는 단락 등의 불량이 발생하게 된다. 그러므로, 하부 절연막의 스텝 커버리지를 개선하기 위하여 금속배선 공정시 하부 절연막의 평탄화 공정이 수행되고 있다. As the size of each active element becomes smaller due to high integration and the structure thereof becomes complicated, the metal wiring is also increased from 2 layers to 4 layers or 5 layers. In particular, when the step coverage of the lower insulating layer is poor, the metal wiring may cause short circuit or short circuit. Therefore, in order to improve the step coverage of the lower insulating film, the planarization process of the lower insulating film is performed during the metallization process.

평탄화 공정은 크게 에치백 공정과 CMP(CHEMICAL MECHANICAL POLISING)공정이 있다. 통상적으로 1층의 금속배선시 적어도 2회의 CMP 공정이 요구되는 바, 평탄화를 위해 소요되는 공정기간이 약 3일 정도 소요되고 있다. The planarization process mainly includes an etch back process and a CMP (CHEMICAL MECHANICAL POLISING) process. In general, at least two CMP processes are required for one layer of metal wiring, and thus, a process period for planarization takes about 3 days.

그러므로, 5층의 금속배선이 요구되는 반도체 칩의 경우에는 평탄화 공정에서만 약 15일의 공정기간이 소요되게 된다. Therefore, in the case of a semiconductor chip that requires five layers of metal wiring, a process period of about 15 days is required only in the planarization process.

또한, CMP공정은 표면을 화학적 및 기계적으로 연마하기 때문에 이와 같은 공정 도중에 파티클이나 스크래치 등에 의해 이미 형성된 능동소자에 불량이 발생되어 전체적으로 수율이 떨어지는 문제가 있었다.In addition, since the CMP process chemically and mechanically polishes the surface, defects occur in active devices that are already formed by particles or scratches during the process, resulting in a drop in overall yield.

또한, 종래의 반도체 장치에서는 하나의 반도체 기판 상에 능동소자와 다층 금속배선을 형성하기 때문에 다층 금속배선가지 완료된 상태에서, EDS와 같은 테스트 작업이 가능하였다. 즉, 능동소자만 만들어 진 상태에서는 테스트가 불가능하였다. In addition, in the conventional semiconductor device, since the active element and the multilayer metal wiring are formed on one semiconductor substrate, a test operation such as EDS is possible in the state where the multilayer metal wiring is completed. In other words, it was impossible to test with only active elements.

본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 평탄화공정수가 많은 다층 금속배선과 능동소자를 각각 다른 반도체 기판에서 형성한 다음에 이들을 상호 접촉함으로써, 공정기간의 단축, 수율증대 및 효과적인 테스트가가능한 반도체 장치 및 그 제조방법을 제공하는 데 있다.An object of the present invention is to solve the problems of the prior art by forming a multi-layered metal wiring and a number of planarization process active elements on different semiconductor substrates and then contact them with each other, thereby shortening the processing time, increasing the yield and effective testing There is provided a semiconductor device and a method of manufacturing the same.

상기한 본 발명의 목적을 달성하기 위하여 본 발명의 방법은 제 1 반도체 기판 상에 능동소자들을 형성하고 1차 금속배선을 형성하고, 1차 금속배선 상에 제 1 범프들을 형성하는 단계와, 제 2 반도체 기판 상에 상기 제 1 반도체 기판 상에 형성된 능동소자들의 상호 접속 및 외부 접속을 위한 다층 금속배선을 형성하고, 최상층의 금속배선 상에 제 2 범프들을 형성하는 단계와, 상기 제 1 반도체 기판의 제 1 범프들과 상기 제 2 반도체 기판의 제 2 범프들이 서로 대응하는 것들끼리 마주 보도록하여 상호 접촉하는 단계를 구비하는 것을 특징으로 한다. In order to achieve the above object of the present invention, the method of the present invention comprises the steps of forming active elements on a first semiconductor substrate, forming a primary metal wiring, and forming first bumps on the primary metal wiring; Forming a multi-layered metal interconnection for interconnection and external connection of active elements formed on the first semiconductor substrate on the semiconductor substrate, and forming second bumps on the uppermost metal interconnection; And the first bumps of the second bumps and the second bumps of the second semiconductor substrate face each other so as to face each other.

상기 제 1 범프와 제 2 범프들 중 외부 접속용 상하 범프들 사이에는 리드 프레임의 내부리드가 사이에 놓여져 동시에 접속되는 것이 바람직하다. It is preferable that an inner lead of the lead frame is interposed between the first bumps and the upper and lower bumps of the second bumps to be connected at the same time.

본 발명의 장치는 복수의 능동소자들이 표면에 형성되고, 이들 능동소자들을 연결하기 위한 1차 금속배선이 형성되고, 1차 금속배선 상에 형성된 복수의 제 1 범프들을 가진 제 1 반도체 기판과, 상기 제 1 반도체 기판 상에 형성된 복수의 능동소자들의 상호 연결 및 외부 연결을 위한 다층 금속배선들이 형성되고, 최상층에는 상기 제 1 범프들과 대응되는 복수의 제 2 펌프들이 형성된 제 2 반도체 기판을 구비하고, 상기 제 1 반도체 기판의 제 1 범프들과 상기 제 2 반도체 기판의 제 2 범프들이 서로 대응하는 것들끼리 마주보도록 접촉하여서 된 것을 특징으로 한다. An apparatus of the present invention includes a first semiconductor substrate having a plurality of active elements formed on a surface thereof, a first metal wiring for connecting the active elements, and a plurality of first bumps formed on the first metal wiring; A multi-layered metal wiring is formed for interconnection and external connection of a plurality of active elements formed on the first semiconductor substrate, and a second semiconductor substrate having a plurality of second pumps corresponding to the first bumps is formed on an uppermost layer. The first bumps of the first semiconductor substrate and the second bumps of the second semiconductor substrate may be in contact with each other so as to face each other.

이하, 첨부한 도면을 참조하여, 본 발명의 일 실시예를 통해 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

도 1은 본 발명에 의한 능동소자가 형성된 제 1 반도체 기판을 나타낸고, 도 2는 본 발명에 의한 다층 금속배선이 형성된 제 2 반도체 기판을 나타내고, 도 3은 제 1 반도체 기판과 제 2 반도체 기판을 마주보도록 접촉한 상태를 나타낸다. 1 illustrates a first semiconductor substrate on which an active element according to the present invention is formed, FIG. 2 illustrates a second semiconductor substrate on which a multi-layered metal wiring is formed, and FIG. 3 illustrates a first semiconductor substrate and a second semiconductor substrate. Indicates a state of contact with each other.

도면을 참조하면, 본 발명의 반도체 장치는 제 1 반도체 기판(10) 상에 능동소자들과 제 1 층의 금속배선(30)과 제 1 범프들(36)이 형성된다. 제 2 반도체 기판(40) 상에 다층 금속배선들(44, 48)과 제 2 범프들(54)이 형성된다. Referring to the drawings, in the semiconductor device of the present invention, the active elements, the metal wiring 30 of the first layer and the first bumps 36 are formed on the first semiconductor substrate 10. Multi-layered metal wires 44 and 48 and second bumps 54 are formed on the second semiconductor substrate 40.

즉, 도 1을 참조하면, 반도체 기판(10) 상에 액티브 영역을 한정하는 필드 산화막(12)을 형성하고, 액티브 영역에 게이트 산화막(14), 게이트 전극(16)을 형성한다. 이어서, 게이트 전극(16)에 얼라인 되게 반도체 기판의 표면에 불순물을 주입하여 제 1 불순물영역(18)을 형성한다. 이어서, 게이트전극(16)의 측벽에 스 페이서(20)를 형성하고, 스페이서(20)에 얼라인되게 반도체 기판의 표면에 불순물을 이온 주입하여 제 2 불순물 영역(22)을 형성한다.That is, referring to FIG. 1, the field oxide film 12 defining the active region is formed on the semiconductor substrate 10, and the gate oxide film 14 and the gate electrode 16 are formed in the active region. Subsequently, impurities are implanted into the surface of the semiconductor substrate to be aligned with the gate electrode 16 to form the first impurity region 18. Subsequently, the spacer 20 is formed on the sidewall of the gate electrode 16, and the second impurity region 22 is formed by implanting impurities into the surface of the semiconductor substrate to be aligned with the spacer 20.

이어서, 열산화막(24)을 덮고, 그위에 BPSG와 같은 층간 절연막(26)을 형성한다. 층간 절연막(26)의 표면은 CMP 공정과 같은 평탄화 공정을 통하여 평탄하게 형성된다.Subsequently, the thermal oxide film 24 is covered, and an interlayer insulating film 26 such as BPSG is formed thereon. The surface of the interlayer insulating film 26 is formed flat through a planarization process such as a CMP process.

층간 절연막(26)에 콘택홀(28)을 형성한 다음에 1차 금속배선(30)을 형성한다. 1차 금속배선(30)을 보호막(32)으로 덮고 보호막(32)에 비아(34)를 형성한다. 보호막(34)의 각 비아에 제 1 범프(36)를 형성하여 능동소자가 형성된 제 1 반도체 기판(10)의 공정을 완료한다. After forming the contact hole 28 in the interlayer insulating layer 26, the primary metal wiring 30 is formed. The primary metal wiring 30 is covered with the passivation layer 32 and the vias 34 are formed in the passivation layer 32. A first bump 36 is formed in each via of the passivation layer 34 to complete the process of the first semiconductor substrate 10 in which the active element is formed.

한편, 제 2 반도체 기판(40) 상에 제 1 절연막(42)을 덮고, 제 1 금속배선(44)을 형성한다. 제 1 금속배선(44)를 제 1 층간 절연막(46)으로 덮고, CMP공정으로 제 1 층간 절연막(46)의 표면을 평탄하게 연마한다. 제 1 층간 절연막(46) 상에 제 2 금속배선(48)을 형성한 다음에 보호막(50)으로 덮는다. 보호막(50)에 비아(52)를 형성한 다음에 각 비아에 제 2 범프들(54)을 형성하여 다층 금속배선이 형성된 제 2 반도체 기판의 공정을 완료한다.On the other hand, the first insulating film 42 is covered on the second semiconductor substrate 40 to form the first metal wiring 44. The first metal wiring 44 is covered with the first interlayer insulating film 46, and the surface of the first interlayer insulating film 46 is smoothly polished by a CMP process. The second metal wiring 48 is formed on the first interlayer insulating film 46 and then covered with the protective film 50. After the vias 52 are formed in the passivation layer 50, the second bumps 54 are formed in each via to complete the process of the second semiconductor substrate on which the multi-layer metal wiring is formed.

도 3을 참조하면, 도 1 및 도 2에 도시한 능동소자의 반도체 기판(10)과 다층 금속배선의 반도체 기판(40)을 마주 보도록하여 서로 대응되는 제 1 범프들(34)과 제 2 범프들(54)이 서로 접촉되도록 한다. 이 때. 칩의 주변영역의 범프들(34, 54)의 사이에는 리드 프레임의 내부리드(60)가 사이에 놓이게 하여 상호 접촉한다. Referring to FIG. 3, the first bumps 34 and the second bumps corresponding to each other are disposed so as to face the semiconductor substrate 10 of the active device illustrated in FIGS. 1 and 2 and the semiconductor substrate 40 of the multi-layered metal wiring. The fields 54 are in contact with each other. At this time. An inner lead 60 of the lead frame is interposed between the bumps 34 and 54 of the peripheral area of the chip so as to contact each other.

즉, 본 발명에서는 능동소자의 제조라인과 다층 금속배선 제조라인을 동시에 운영하여 각각 제 1 반도체 기판에는 능동소자를 형성하고, 제 2 반도체 기판에는 다층 금속배선을 각각 형성한다. 이와 같이 각각 형성된 제 1 반도체 기판과 제 2 반도체 기판을 범프공정을 통하여 상호 연결함으로써, 하나의 완성된 집적회로 칩을 형성하게 된다. That is, in the present invention, the active device manufacturing line and the multi-layer metal wiring manufacturing line are operated simultaneously to form active devices on the first semiconductor substrate, and multi-layer metal wiring on the second semiconductor substrate, respectively. The first semiconductor substrate and the second semiconductor substrate, which are formed as described above, are interconnected through a bump process, thereby forming one completed integrated circuit chip.

그러므로, 종래의 한 라인에서 능동소자와 다층 금속배선을 순차적으로 형성한 방법에 비하여 공정기간을 단축시킬 수 있고, 능동소자의 후속 다층 금속배선공정에서 이미 만들어진 능동소자에 가해지는 여러 가지 화학적 및 기계적 습격(ATTACK)이 감소되므로 발생될 수 있는 불량발생을 억제시킬 수 있으므로 수율을 증대시킬수 있다. Therefore, the process time can be shortened compared to the method of sequentially forming the active element and the multi-layer metal wiring in one conventional line, and various chemical and mechanical effects applied to the active element already made in the subsequent multi-layer metal wiring process of the active element. Since the attack (ATTACK) is reduced, it is possible to suppress the occurrence of defects that can occur, thereby increasing the yield.

또한, 능동소자만 만들어진 상태, 즉 그 이상의 다층 금속배선이 형성되지 않은 상태에서 EDS와 같은 테스트하는 것이 가능하여 보다 효율적인 테스트가 가능하다. In addition, it is possible to test such as EDS in a state where only active devices are made, that is, no multi-layered metal wiring is formed, thereby enabling more efficient testing.

상술한 실시예에서는 3층 금속배선의 예를 들어 설명하였으나, 4층 또는 5층의 다층 금속배선에 대해서도 동일하게 적용 가능하다. In the above-described embodiment, the three-layer metal wiring has been described as an example, but the same applies to the four-layer or five-layer multilayer metal wiring.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야의 숙련된 당업자는 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

이상, 설명한 바와 같이 본 발명에서는 능동소자와 다층 금속배선을 각각 별 도의 반도체 기판에 형성한 다음에 이들을 결합시킴으로써 공정기간의 단축, 불량감소로 인한 수율증대, 효과적인 테스트 등이 가능하다.
As described above, in the present invention, the active elements and the multi-layered metal wirings are formed on separate semiconductor substrates, and then combined with each other, thereby shortening the process period, increasing yields due to defects, and effective testing.

Claims (3)

제 1 반도체 기판 상에 능동소자들을 형성하고 1차 금속배선을 형성하고, 1차 금속배선 상에 제 1 범프들을 형성하는 단계;Forming active elements on the first semiconductor substrate, forming a primary metal interconnection, and forming first bumps on the primary metal interconnection; 제 2 반도체 기판 상에 상기 제 1 반도체 기판 상에 형성된 능동소자들의 상호 접속 및 외부 접속을 위한 다층 금속배선을 형성하고, 최상층의 금속배선 상에 제 2 범프들을 형성하는 단계; 및Forming a multilayer metal interconnection for interconnection and external connection of active elements formed on the first semiconductor substrate on a second semiconductor substrate, and forming second bumps on the uppermost metal interconnection; And 상기 제 1 반도체 기판의 제 1 범프들과 상기 제 2 반도체 기판의 제 2 범프들이 서로 대응하는 것들끼리 마주 보도록하여 상호 접촉하는 단계를 구비하는 것을 특징으로 반도체 장치의 제조방법. And contacting the first bumps of the first semiconductor substrate and the second bumps of the second semiconductor substrate to face each other. 제 1 항에 있어서, 상기 제 1 범프와 제 2 범프들 중 외부 접속용 상하 범프들 사이에는 리드 프레임의 내부리드가 사이에 놓여져 동시에 접속되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein an inner lead of the lead frame is interposed between the first bumps and the upper and lower bumps for the external connection. 복수의 능동소자들이 표면에 형성되고, 이들 능동소자들을 연결하기 위한 1차 금속배선이 형성되고, 1차 금속배선 상에 형성된 복수의 제 1 범프들을 가진 제 1 반도체 기판; 및 A first semiconductor substrate having a plurality of active elements formed on a surface thereof, having a first metal wiring for connecting the active elements, and having a plurality of first bumps formed on the first metal wiring; And 상기 제 1 반도체 기판 상에 형성된 복수의 능동소자들의 상호 연결 및 외부 연결을 위한 다층 금속배선들이 형성되고, 최상층에는 상기 제 1 범프들과 대응되 는 복수의 제 2 펌프들이 형성된 제 2 반도체 기판을 구비하고, A multi-layered metal wiring is formed for interconnection and external connection of a plurality of active elements formed on the first semiconductor substrate, and a second semiconductor substrate having a plurality of second pumps corresponding to the first bumps is formed on an uppermost layer. Equipped, 상기 제 1 반도체 기판의 제 1 범프들과 상기 제 2 반도체 기판의 제 2 범프들이 서로 대응하는 것들끼리 마주보도록 접촉하여서 된 것을 특징으로 하는 반도체 장치. And the first bumps of the first semiconductor substrate and the second bumps of the second semiconductor substrate are in contact with each other so as to face each other.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5657022A (en) * 1979-10-17 1981-05-19 Seiko Epson Corp Liquid crystal display device
JPS60220939A (en) * 1985-03-20 1985-11-05 Hitachi Ltd Semiconductor integrated circuit device
JPS6450543A (en) * 1987-08-21 1989-02-27 Nec Corp Manufacture of semiconductor device
JPH0442957A (en) * 1990-06-06 1992-02-13 Matsushita Electron Corp Manufacture of semiconductor integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5657022A (en) * 1979-10-17 1981-05-19 Seiko Epson Corp Liquid crystal display device
JPS60220939A (en) * 1985-03-20 1985-11-05 Hitachi Ltd Semiconductor integrated circuit device
JPS6450543A (en) * 1987-08-21 1989-02-27 Nec Corp Manufacture of semiconductor device
JPH0442957A (en) * 1990-06-06 1992-02-13 Matsushita Electron Corp Manufacture of semiconductor integrated circuit device

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