JPS6450543A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6450543A JPS6450543A JP20871087A JP20871087A JPS6450543A JP S6450543 A JPS6450543 A JP S6450543A JP 20871087 A JP20871087 A JP 20871087A JP 20871087 A JP20871087 A JP 20871087A JP S6450543 A JPS6450543 A JP S6450543A
- Authority
- JP
- Japan
- Prior art keywords
- interconnections
- substrate
- substrates
- alloy
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To decrease restrictions on a process for forming interconnections and to prevent deterioration of reliability of a device during the formation of inter-connections, by separately forming interconnections on a semiconductor substrate carrying a device on the surface thereof and on an insulator substrate having a multilayer interconnections, respectively, and bonding these substrates together with their interconnection formed faces faced to each other and connecting corresponding interconnections with each other. CONSTITUTION:Interconnections 3 and 6 are formed respectively on a semiconductor substrate 1 having a device 2 formed thereon and on an insulator substrate 4 having multilayer, interconnections 6 formed thereon. These substrates 1 and 4 are bonded together with their interconnection formed faces faced to each other, and corresponding interconnections are connected to each other. According to an embodiment, a MOS semiconductor device 2 is formed on a silicon substrate 1, and Al-Si alloy vertical interconnections 3 are formed thereon. On the other hand, an Au interconnection 5 for providing through interconnections and bumps is formed on an insulating glass substrate 4 and then two layer interconnections 6 of Al-Si alloy are formed. Said silicon substrate 1 is positioned with respect to the insulating glass substrate 4 and the vertical interconnections 3 are connected to the Al-Si alloy two-layer interconnections 6 by means of thermocompression bonding. Then, low-melting glass 7 is injected into a space between the semiconductor and insulator substrates and into the periphery thereof so that the substrates are bonded together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20871087A JPS6450543A (en) | 1987-08-21 | 1987-08-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20871087A JPS6450543A (en) | 1987-08-21 | 1987-08-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6450543A true JPS6450543A (en) | 1989-02-27 |
Family
ID=16560798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20871087A Pending JPS6450543A (en) | 1987-08-21 | 1987-08-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6450543A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5589419A (en) * | 1994-07-26 | 1996-12-31 | Sony Corporation | Process for fabricating semiconductor device having a multilevel interconnection |
| US5814889A (en) * | 1995-06-05 | 1998-09-29 | Harris Corporation | Intergrated circuit with coaxial isolation and method |
| WO2001082367A1 (en) * | 2000-04-20 | 2001-11-01 | Hitachi, Ltd. | Integrated circuit and method of manufacture thereof |
| KR100583948B1 (en) * | 2000-02-28 | 2006-05-26 | 삼성전자주식회사 | Semconductor device and method thereof |
-
1987
- 1987-08-21 JP JP20871087A patent/JPS6450543A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5589419A (en) * | 1994-07-26 | 1996-12-31 | Sony Corporation | Process for fabricating semiconductor device having a multilevel interconnection |
| US5814889A (en) * | 1995-06-05 | 1998-09-29 | Harris Corporation | Intergrated circuit with coaxial isolation and method |
| KR100583948B1 (en) * | 2000-02-28 | 2006-05-26 | 삼성전자주식회사 | Semconductor device and method thereof |
| WO2001082367A1 (en) * | 2000-04-20 | 2001-11-01 | Hitachi, Ltd. | Integrated circuit and method of manufacture thereof |
| US6989600B2 (en) | 2000-04-20 | 2006-01-24 | Renesas Technology Corporation | Integrated circuit device having reduced substrate size and a method for manufacturing the same |
| JP4041675B2 (en) * | 2000-04-20 | 2008-01-30 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
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