JPS6189657A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To mount in high density by a flip-chip method or tape-carrier method useful for reducing a mounting size by providing a main chip provided at a function element region at the center of the main surface, an electrode bump for connecting an external conductor, a barrier bump provided on the main surface of the chip, and a hermetically sealed sub chip. CONSTITUTION:Function element regions 9, 10 as semiconductor devices are provided on a main chip substrate 7 and a sub chip substrate 8, mutually connected electrode groups 11, 12 are provided on the outer periphery, and the regions 9, 10 are electrically coupled by metal wiring pattern as required. External conductor connecting electrode pad group 13 is formed near the peripheral edge of the main chip 7, and electrically connected with the wiring pattern 15 under a protective film layer 14 with the group 11. The electromechanical coupling between the chips 7 and 9 having the basic structures used a flip-chip type. The chips 7 and 9 are all formed in the same steps as the normal semiconductor device manufacturing wafer process, and the process of forming the bump is then added.

Description

[Detailed Description of the Invention] Industrial Application Field This invention relates to semiconductor devices such as RC and LSI and their manufacturing method, and particularly provides a technology useful for downsizing and packaging high-density integrated circuits. .

Conventional configurations and their problems With the demand for smaller size and higher speed of system equipment, the integration and density of semiconductor integrated circuits (hereinafter referred to as LSI), which are the main components thereof, are rapidly increasing. At the same time, various small-sized high-density mounting methods have been proposed in order to promote miniaturization of the buff caging method for mounting LSI elements.

For example, as a wireless bonding method, Fig. 1) (
Flip chip method as shown in A) and 1) Figure (B)
) There are tape carrier methods such as the one shown in .

These methods include: 1) forming bumps 2 of solder or gold on a semiconductor element 1 (hereinafter simply referred to as a chip) as shown in the figure; After connecting with the lead conductor 6 formed on the material 5, the chip l is sealed by hermetic sealing or resin sealing.
It is a configuration that mechanically or environmentally protects the

In addition, in order to improve the packaging density, in the case of Flinopchipu, if multiple chips are arranged two-dimensionally on the same board, the packaging fJJ rate can be improved compared to the conventional wireless bonding method. However, since the arrangement is two-dimensional, there are two degrees.

Furthermore, when it comes to protecting the chip, especially against the effects of moisture, etc., if it is hermetically sealed, a sufficient effect can be obtained due to its nature, but in the case of resin molding, the chip itself is strongly protected, as is the case with general plastic molded ICs. It is necessary to form a protective film, a so-called puffy film.

Purpose of the Invention The present invention proposes high-density packaging using the flip-chip method or tape carrier method, which is useful for downsizing packaging, and also provides a semiconductor device with good environmental resistance, that is, high reliability, and a method for manufacturing the same. The purpose is to provide.

Structure of the Invention In order to realize high-density and highly reliable packaging, when forming electrode bumps for connecting external conductors on the main surface of the main LSI chip, the present invention provides a method for forming electrode bumps that surround the functional element area of the main LSI chip. A barrier bump (hereinafter tentatively referred to as a rectangular bump) is formed from a material having the same composition as the external conductor connection electrode bump.

Further, the main surface of a sub-chip having a dimension shape smaller in at least two sides than the main LSI chip is placed on the rectangular bump with the main LSI chip facing the main surface, and a step of connecting lead electrodes to the bumps of the main LSI chip is performed. In this heat treatment process, the sub-chip is simultaneously connected to the main LSI chip by square bumps, and the functional element area on the main surface of the main LSI chip is hermetically sealed.

In addition, when the sub-chip has a metal wiring pattern on its main surface or has a functional element area on its main surface like the main LSI chip, a group of interconnecting electrode bumps is placed inside the rectangular bumps of the main chip as described above. An electrical connection layer with the main chip is formed at the part of the subchip facing the interconnection electrode bump group, and the electrical connection layer between the main chip and the subchip is formed when performing airtight 1) sealing. This is a configuration that allows

DESCRIPTION OF THE EMBODIMENTS A first embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2(A) is a plan view showing the main surface of the main chip in the first embodiment of the present invention, and FIG. 2(B) is a plan view showing the main surface of the subchip.

The main surfaces of the main chip substrate 7 and the subchip substrate 8 each have a functional element region 9°lO as a semiconductor device.
Functional element area 9. There is a group of interconnection electrodes 1 on the outer periphery of the IO.
). 12 are provided, and the functional element regions 9 and 10 are respectively Ae as required.

They are electrically coupled by a metal wiring pattern (not shown) made of Mo or the like.゛Also, near the periphery i of the main chip 7, an electrode pad group 13 for external conductor connection is formed, and the interconnection electrode group 1) is formed by forming a wiring pattern under the protection 1!1IJi14 as shown in FIG. 15, each is electrically sticky.

The electrical and mechanical coupling between the main chip 7 and the sub-chip 8 having the above-mentioned basic configuration is carried out using a so-called free-button method.

The process of forming the electrode wiring pattern and the surface protective film for both the main chip 7 and the subchip 8 are the same as the normal semiconductor device manufacturing wafer process.
A subsequent bump formation process will be added.

That is, in the main chip 7, as shown in FIG. 3, the surface protection film 14 is subjected to hole-opening treatment at the portions of the interconnection electrode group 1) and the external electrode connection electrode pad group z3 to expose the electrode metal layer. Interconnection bumps 16 and electrode bumps 17 are formed at the same locations, respectively, as shown in FIG.

The structure and formation method of these bumps will be explained in detail with reference to FIG.

Electrode metal layer material 15 (eg aluminum) and protective film material 14 (υ1), for example Si'02. Ti, Cr, which has good adhesion to both Ti and Cr (SiN films).

The first layer is adhesive rif+8 made of Ni-Cr, etc., and the second layer is barrier metal scrap 19 that suppresses the reaction between the bump metal made of Pt, Pd, Ni, Rh, Cu, etc. and the electrode metal material (A1 etc.). Laminated and formed.

After that, 5n-p which becomes the bump main material as the third rfi
b, solder alloy layer 20 such as Sn-Ag with a thickness of 10 μm to several tens of μm
After laminating to a thickness of μm, photoetching is performed so that the laminated metal is selectively left on the interconnection electrode group 1) and the external electrode connection electrode pad group 13, as shown in the cross-sectional shape of FIG. Processing is performed to remove the excess laminated metal layer. At this time, the photoetching process simultaneously forms the functional element region 9 and the interconnection electrode portion 1) on the main surface of the main chip 7, as shown in the cross-sectional views of FIGS. 4 and 5 and the plan view of FIG. 2(A). The laminated metal layer is left in a shape surrounding -U, and the same part is sealed with a metal part, that is, a rectangular bump 2.
1 on the same main surface.

In this way, on the main surface of the main depth 7, as shown in the plan view of FIG. 2 and the local sectional view of FIG.
Fully bent protrusions with a height of μm, electrode bumps 17 are placed on the electrode pad group 13 for external electrode connection, connection bumps 16 are placed on the interconnection electrode group 1), and Square bumps 21 are formed on the outer surface protection film 14, respectively.

In the above description, the first to third metal layers are the main chip base Fi? An example has been described in which bumps are formed by selectively removing unnecessary metal laminated parts using a photo-etching process after layering the entire surface of the metal layer. Bumps are formed by laminating only the second layer, selectively leaving the laminated metal only in the necessary parts as in the above case, and selectively laminating the third layer (solder alloy layer) on the remaining laminated part. method may also be used.

Next, as shown in the plan view of FIG. 2(B) and the local cross-sectional view of FIG. When the main surfaces of the sub-chips 8 are placed one on top of the other, an adhesive layer 18.
The electrically connected portion 12 formed by laminating the barrier metal layer 19 and the /8F layer 23 is selectively formed, and a portion corresponding to the rectangular bump 21 of the main chip 7, a portion to be sealed and bonded 22 is formed.
have an adhesive layer 18., respectively. A barrier metal layer 19 and a welding layer 23 are selectively formed as Mt layers.

The presence or absence of welding N23 is determined by the composition of the solder alloy, which is the bump material formed on the main chip 7. For example, welding N23 is applied to the barrier metal 1ij19 of the subchip with a solder alloy such as Au, Ag, or 3U. A metal with good wettability is used.

The sub-chip 8 configured as described above is placed at a fixed position on the main surface of the main chip 7 with the main surfaces facing each other as shown in FIG.
The heat treatment is performed at a temperature slightly higher than the melting temperature of the solder alloy. Through this heat treatment, the connection pan 1) 6 on the main chip 7
and the rectangular bumps 21 are melt-bonded to the connected electrode portion 12 and the sealed bonded portion 22i of the sub-chip 8, respectively, and electrical connection between the functional element region 9 of the main chip 7 and the functional element region IO of the sub-chip 8 is established. At the same time, in order to weld the rectangular bumps 21, each functional element area 9 is
．． IO is hermetically sealed from the outside air.

Connection of the external electrode leads of the main chip 7 on which the subchip 8 is placed on the main surface constructed as described above is almost the same as that of a normal flip-chip mounting method. That is, FIG. 7 (A>
As shown, the wiring pattern conductor 4 of the flip chip board 3
After aligning and placing the electrode bump 17 on the surface, the solder alloy glue, which is the material of the bump, is flow-treated to form the free 7.
Mounting is performed on the petit sop board 3.

Further, FIG. 7(B) shows an example of mounting a tape carrier, in which the aforementioned electrode bumps 17 are matched with the lead conductors 6 of the film substrate 5, and then a bonding process is performed to form the lead conductors 6.
and electrode bumps 17 are welded together.

Note that the connection between the wiring pattern conductor 4 of the flip-chip substrate 3 or the lead conductor 6 of the film base Fi5 and the electrode bump 17 may be performed at the same time when the rectangular bump 21 and the sub-chip 8 are welded.

In this embodiment, when forming an electrode bump 17 for connection with an external conductor on a semiconductor main chip 8, a barrier-shaped rectangular bump surrounded by a functional element region 9 is formed of a material having the same composition as the bump 17. 21 is formed, the sub-chip 8 is placed on the barrier-like rectangular bumps 21, and a heat treatment, for example, a solder reflow process is performed, so that the external electrodes are connected and the sub-chip 8 is placed on the main chip 7 by the barrier-like rectangular bumps 21. The functional element region 9 of the main chip 7 and the functional element region 10 of the sub-chip 8 are both hermetically sealed.
Protection of the functional element regions 9 and 10 can be easily obtained through the same manufacturing process as the conventional bump formation process, and the reliability of the small, high-density packaging semiconductor device can be improved.

Next, a second embodiment of the present invention will be described based on FIGS. 8 and 9. Both the main chip and the subchip of the first embodiment are large-scale integrated circuit devices (for example, L
We have shown an example of a high-reliability, high-density packaging method for SI memory (SI memory), but in the case of a semiconductor device with a relatively small beam density, the main chip is the only chip that has a functional element area, and the sub-tinop has only a conductor wiring pattern. In some cases, groove bottoms with a pattern or no pattern at all are used.

For example, the wiring pattern on the main chip board requires multilayer wiring due to its functionality, but it is difficult to form multilayer wiring on the chip due to the pattern configuration, or by partially changing the wiring pattern on the main chip. When selectively using some of the multiple functions of the deep, a sub-chip 81 as shown in FIG. 8 and FIG. 9, which is an enlarged cross-sectional view of the same figure,
By adopting , the above-mentioned functional requirements can be easily satisfied, and
As in the case of the first embodiment, it can also serve to protect the functional element area of the main chip.

That is, as shown in FIG. 8, a conductive wiring pattern 24 suitable for the above purpose is formed on the main surface of the main panel 81, and each of the wiring patterns 24 is connected to the connected electrode part 12, and furthermore, the conductive wiring pattern 24 is connected to the connected electrode part 12. The outer periphery of the electrode portion 12 is surrounded by a sealed bonding portion 22, and these portions are covered with an adhesive layer 18 and a bonding layer 18, respectively, as shown in FIG. 9(A), as in the case of the first embodiment. Barrier metal 1+i! il 9 and /8 tails 23 are selectively formed.

Further, in FIG. 9(B), 5i02 is attached to the main surface of the subchip 81.
The same insulating film layer 14 is formed.

At the periphery of the bump 81, an adhesive layer 18, a barrier metal layer 19, and a welding layer 23, which are bonding layers to be sealed, are selectively formed at a portion corresponding to the rectangular bump 22 of the main chip 81.

The subchip 81 of the two examples above was used and placed on a predetermined location on the main chip in the same manner as in the first example! & By performing heat treatment, in the former example, the conductive wiring pattern 24 of the sub-chip and the connected electrode part 12 provide the desired bonding between the electrodes of the main chip, and the rectangular bumps 22 hermetically seal the functional element area. A stop is made. Also,
In the latter example, the functional element area of the main chip is '1', and the hermetic sealing effect is maintained by the subchip 81 and the rectangular buff '22.

A third embodiment of this invention will be described based on FIG. The third embodiment focuses on protecting the functional element area of the main chip, and FIG. 1O shows a cross-sectional view of this embodiment.

When forming the electrode bumps 17 on the main chip 7, rectangular bumps 21 are formed on the outer periphery of the functional element region 9 using the same composition material as the electrode bumps 17 described above. Later, the same bump alloy (for example, 5n-pb, Sn-Ag) is placed on the square bump 21.
etc.) with good wettability with Au, Ag, Ni, 5n
- A cover body (sub-chip) 25 made of a thin metal plate plated with Pb or the like, a ceramic thin plate plated with metallization, or a thin plate of the above-mentioned metal material is mounted on the top, and the electrode bumps 17 and external connection leads (not shown) are mounted on the lid body (subchip) 25. First, the electrode bumps 17 are melted and bonded through a heat treatment process (for example, the inner lead of the tape carrier), and the lid body 25 is melted and bonded to the rectangular bumps 21, so that the cup body 25 has the function of the main chip 7. The element region 9 is sealed, and the same portion is hermetically sealed.

In addition, the plating treatment or metallining treatment of the single body 25 may be applied not only to the entire surface of the square but also to only a portion facing the same portion when it is mounted on a square bump.

Effects of the Invention In the semiconductor device of the first invention, electrode bumps for external electrode connection are formed on the outer peripheral edge of the main surface of the main chip, and the main surface of the main chip is formed so as to surround the functional element area inside the electrode bumps. By forming a barrier-like bump on the barrier-like bump and placing the sub-chip on the barrier-like bump and adhering them to each other, the central part of the main surface of the main chip and the sub-chip is hermetically sealed. Can be sealed,
Therefore, miniaturization and high reliability can be achieved.

Further, according to the method for manufacturing a semiconductor device of the second invention, barrier-like bumps and electrode bumps for connecting external electrodes can be formed at the same time, and furthermore, the sub-chip and barrier bumps can be bonded by heat fusion. Therefore, the manufacturing process does not become complicated due to hermetic sealing.

Further, according to the method for manufacturing a semiconductor device of the third aspect of the invention, since the connection between the external conductor and the electrode bump and the connection between the barrier-like bump and the sub-nup are performed at the same time, the manufacturing becomes easier.

Further, according to the method for manufacturing a semiconductor device of the fourth aspect of the invention, the main chip and the subchip can be interconnected at the same time, making manufacturing easy.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIGS. 2A and 2B are plan views of the main chip and subchip in FIG. 1, and FIGS. 3 and 4 are 5 is a cross-sectional view taken along line 1-1' in FIG. 2(A), FIG. 6 is a cross-sectional view taken along line ■-■' in FIG. Figures (A) and (B) are cross-sectional views showing wireless bonding in the present invention, Figure 8 is a cross-sectional view of the main chip of a semiconductor device in a second embodiment of the present invention, and Figure 9 (A) is a cross-sectional view of the main chip of a semiconductor device in a second embodiment of the present invention. 9(B) is a sectional view of a modified example, FIG. 1θ is a sectional view of a semiconductor device according to a third embodiment of the present invention, FIG. B) is a sectional view showing conventional wireless bonding. 7...Main chip, 8...Sub chip, 9. lO・・
Functional element area, 16... Japanese tile connection bump, 17...
- Electrode bump for external conductor connection, 21... Square bump (barrier bump) 1: Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (8)

[Claims] (1) A main chip with a functional element area provided in the center of the main surface, an electrode bump for external conductor connection provided on the outer periphery of the main surface of this main chip, and the functional element area provided inside the electrode bump. A barrier bump provided on the main surface of the main chip so as to surround it, and placed and bonded to the barrier bump with its main surface facing the main surface of the main chip and not overlapping with the electrode bumps. and a sub-chip that hermetically seals the central portion of the principal surface of the main chip and the central portion of its own principal surface. (2) The main chip and the subchip are electrically connected by bonding a group of interconnecting electrode bumps provided on the main surface of the main chip inside the barrier-like bumps to the main surface of the subchip. The semiconductor device according to item (1). (3) The semiconductor device according to claim (2), wherein the function of the main chip is selected by a conductor wiring pattern formed on the main surface of the subchip. (4) The semiconductor device according to claim (2), wherein the sub-chip is provided with a functional element region that assists the function of the main chip in a central portion of the main surface. (5) The semiconductor device according to claim (1), wherein the sub-chip is a lid whose at least a surface is made of metal. (6) electrode bumps for external conductor connection located on the outer periphery of the main surface of a main chip having a functional element area in the central part of the main surface; simultaneously forming barrier-like bumps located on the main surface of the chip from the same composition material, and forming the barrier-like bumps with the main surface of the sub-chip facing the main surface of the main chip and not overlapping with the electrode bumps; placing the sub-chip on the barrier-like bump, and heat-treating the sub-chip with the sub-chip placed on the barrier-like bump to fuse the barrier-like bump and the sub-chip and hermetically seal the center portions of the main surfaces of the main chip and the sub-chip; A method for manufacturing a semiconductor device, comprising the step of: (7) an electrode bump for connecting an external conductor located on the outer periphery of the main surface of the main chip having a functional element area in the central part of the main surface; simultaneously forming barrier-like bumps located on the main surface of the chip from the same composition material, and forming the barrier-like bumps with the main surface of the sub-chip facing the main surface of the main chip and not overlapping with the electrode bumps; a step of placing an external connection conductor in opposing contact with the electrode bump; and a step of placing the sub-chip on the barrier-like bump and heat-treating the sub-chip while bringing the external connection conductor into opposing contact with the electrode bump. A method for manufacturing a semiconductor device, comprising the steps of: fusing the barrier-like bumps and the sub-chips to hermetically seal central portions of the main surfaces of the main chip and sub-chips, and connecting the external connection conductors to the electrode bumps. (8) electrode bumps for external conductor connection located on the outer periphery of the main surface of the main chip having a functional element area in the central part of the main surface; a step of simultaneously forming a barrier-like bump located on a main surface of a chip and a group of interconnecting electrode bumps located on the main surface of the main chip inside the barrier-like bump from the same composition material; placing the sub-chip on the barrier-like bump with its main surface facing each other and not overlapping the electrode bump; and heat-treating the sub-chip while it is placed on the barrier-like bump and the group of interconnecting electrode bumps. fusing the barrier-like bumps and the sub-chips to hermetically seal the central portions of the main surfaces of the main chip and the sub-chips, and electrically connecting the main chips and the sub-chips by the group of interconnection bumps. A method of manufacturing a semiconductor device including: