JP2001298050A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2001298050A JP2001298050A JP2000113772A JP2000113772A JP2001298050A JP 2001298050 A JP2001298050 A JP 2001298050A JP 2000113772 A JP2000113772 A JP 2000113772A JP 2000113772 A JP2000113772 A JP 2000113772A JP 2001298050 A JP2001298050 A JP 2001298050A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor device
- substrate
- resin
- image element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、情報通信機器、事
務用電子機器等に利用される半導体画像センサーを内蔵
し、さらに外部端子との接続配線などを有し、高密度実
装が可能な実装を可能とした半導体装置に関するもので
ある。本発明の半導体装置により、情報通信機器、事務
用電子機器等の小型化を容易にするものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a built-in semiconductor image sensor used for information communication equipment, office electronic equipment and the like, and further has connection wiring with external terminals, etc., and is capable of high-density mounting. The present invention relates to a semiconductor device that enables the above. The semiconductor device of the present invention facilitates miniaturization of information communication equipment, office electronic equipment, and the like.
【０００２】[0002]
【従来の技術】近年、半導体装置およびその製造方法は
電子機器の小型化、高機能化に伴い、小型化、高密度化
を要求されるようになり、たとえばＣＣＤやＣＭＯＳセ
ンサーといった画像センサーが開発されている。2. Description of the Related Art In recent years, as a semiconductor device and a method of manufacturing the same have been required to be reduced in size and increased in density as electronic devices have become smaller and more sophisticated, image sensors such as CCD and CMOS sensors have been developed. Have been.
【０００３】以下、従来の画像センサーと呼ばれる半導
体装置およびその製造方法について断面図を参照にしな
がら説明する。Hereinafter, a conventional semiconductor device called an image sensor and a method for manufacturing the same will be described with reference to sectional views.
【０００４】図６は、従来の画像センサーと呼ばれる半
導体装置を示す断面図である。図６において１０１は半
導体チップまたは半導体ウエハー、１０２は半導体ウエ
ハー１０１上に形成された画素部、１０３は電極パッ
ド、１０４は封止樹脂、１０５はリードフレーム、１０
６はダイスボンド材、１０７はＡｕ線、１０８は封止用
のガラスプレートである。FIG. 6 is a sectional view showing a conventional semiconductor device called an image sensor. 6, reference numeral 101 denotes a semiconductor chip or a semiconductor wafer; 102, a pixel portion formed on the semiconductor wafer 101; 103, an electrode pad; 104, a sealing resin; 105, a lead frame;
Reference numeral 6 denotes a die bond material, 107 denotes an Au wire, and 108 denotes a glass plate for sealing.
【０００５】同図に示すように、従来の画像センサーと
呼ばれる半導体装置は、半導体ウエハー１０１上の電極
パッド１０３がＡｕ線１０７を介してリードフレーム１
０５に接続されており、また半導体ウエハー１０１の主
面側がガラスプレート１０８により覆われた構造を有し
ている。As shown in FIG. 1, in a conventional semiconductor device called an image sensor, an electrode pad 103 on a semiconductor wafer 101 is connected to a lead frame 1 via an Au wire 107.
The main surface of the semiconductor wafer 101 is covered with a glass plate 108.
【０００６】次に、従来の半導体装置の製造方法につい
て、同図を参照にしながら説明する。Next, a conventional method for manufacturing a semiconductor device will be described with reference to FIG.
【０００７】まず、半導体ウエハー１０１をあらかじめ
封止樹脂１０４を形成したリードフレーム１０５上にダ
イボンド材１０６により接合する。First, a semiconductor wafer 101 is bonded to a lead frame 105 on which a sealing resin 104 has been formed in advance by a die bonding material 106.
【０００８】次に、Ａｕ線１０７を用いて周知のワイヤ
ーボンド法により、前記半導体ウエハー１０１上の電極
パッド１０３とリードフレーム１０５とを電気的に接続
する。Next, the electrode pad 103 on the semiconductor wafer 101 and the lead frame 105 are electrically connected by the well-known wire bonding method using the Au wire 107.
【０００９】次に、ガラスプレート１０８を接着剤（図
示せず）を用いて封止樹脂に接着する。以上により、半
導体装置を製造していた。Next, the glass plate 108 is bonded to the sealing resin using an adhesive (not shown). Thus, the semiconductor device was manufactured.
【００１０】すなわち、このような半導体装置の構造を
採用することにより、半導体ウエハー１０１上の画素部
１０２が封止樹脂で覆われることなく、なおかつＡｕ線
を保護することが可能になるので、情報通信機器、事務
用電子機器等の小型化を図れるものである。That is, by adopting such a structure of the semiconductor device, the pixel portion 102 on the semiconductor wafer 101 can be protected from the Au line without being covered with the sealing resin. It is possible to reduce the size of communication devices, office electronic devices, and the like.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら、前記従
来の半導体装置においては、以下のような諸問題があっ
た。However, the conventional semiconductor device has the following problems.
【００１２】前記従来の半導体装置では、半導体ウエハ
−とガラスプレートの間は中空であるため組立工程中に
ダストが半導体ウエハーの画素部に付着したり、組立
後、吸湿することにより、ガラスプレートの半導体ウエ
ハ側に結露を生じ、信頼性に乏しいという問題があっ
た。In the above-mentioned conventional semiconductor device, since the space between the semiconductor wafer and the glass plate is hollow, dust adheres to the pixel portion of the semiconductor wafer during the assembling process, or absorbs moisture after the assembling, so that the glass plate can be removed. There has been a problem that dew condensation occurs on the semiconductor wafer side, resulting in poor reliability.
【００１３】本発明は前記従来の諸問題を解決するもの
であり、その目的は、信頼性や実装密度の高い低コスト
の半導体装置およびその製造方法を提供することにあ
る。An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a low-cost semiconductor device having high reliability and high mounting density and a method of manufacturing the same.
【００１４】[0014]
【課題を解決するための手段】前記目的を達成するため
に本発明では、請求項１〜４に記載されている半導体装
置に関する手段と、請求項５〜６に記載されている半導
体装置の製造方法に関する手段とを講じている。In order to achieve the above object, according to the present invention, there are provided means relating to a semiconductor device as set forth in claims 1 to 4, and manufacturing of a semiconductor device as set forth in claims 5 to 6. We have taken steps on how to do it.
【００１５】本発明の基本的な半導体装置は、請求項１
に記載されているように、画像素子を含む半導体素子が
配設されている半導体基板と、前記半導体基板の主面上
に配列され、前記半導体素子に電気的に接続される素子
電極と、前記半導体基板の主面上の一部であり、少なく
とも画像素子部に形成された透明な絶縁樹脂層と、少な
くとも前記半導体基板上の前記素子電極を露出させるよ
うに前記絶縁樹脂層を部分的に除去して形成された開口
部と、前記素子電極上に形成されたバンプと、前記画像
素子部に相対する位置が貫通した樹脂基板と、前記樹脂
基板と前記バンプの接合部を保護する封止樹脂と、前記
樹脂基板に電気的に接続された外部電極を備えている。A basic semiconductor device according to the present invention is as follows.
As described in, a semiconductor substrate on which a semiconductor element including an image element is disposed, and an element electrode arranged on a main surface of the semiconductor substrate and electrically connected to the semiconductor element, A transparent insulating resin layer which is a part of the main surface of the semiconductor substrate and is formed at least in the image element portion, and the insulating resin layer is partially removed so as to expose at least the element electrode on the semiconductor substrate. And a bump formed on the element electrode, a resin substrate penetrating a position facing the image element portion, and a sealing resin for protecting a joint between the resin substrate and the bump. And an external electrode electrically connected to the resin substrate.
【００１６】これにより、透明な絶縁樹脂層が半導体基
板の主面を保護するので、画像素子部へのダスト付着が
なくなる。すなわち、信頼性の高い半導体装置を実現す
ることができる。Thus, since the transparent insulating resin layer protects the main surface of the semiconductor substrate, dust does not adhere to the image element portion. That is, a highly reliable semiconductor device can be realized.
【００１７】そして、従来のように、ガラスプレートと
封止樹脂からなる中空構造をしていないため、ガラスプ
レートの画像素子部側に結露が生じることがなくなる。Since the glass plate and the sealing resin do not have a hollow structure as in the prior art, dew condensation does not occur on the image element side of the glass plate.
【００１８】また封止樹脂を注入する際、絶縁樹脂がダ
ムとなり、画像素子部への封止樹脂の流出を防ぐことが
できる。Further, when the sealing resin is injected, the insulating resin becomes a dam, so that the leakage of the sealing resin to the image element portion can be prevented.
【００１９】前記半導体装置における前記半導体基板
は、請求項２に記載されているように前記絶縁樹脂は、
画像素子部の外周に形成されていてもよいし、請求項３
に記載されているように前記封止樹脂は、透明であって
もよい。According to a second aspect of the present invention, in the semiconductor device, the semiconductor substrate comprises:
4. The light emitting device according to claim 3, wherein the light emitting element is formed on an outer periphery of the image element portion.
As described in the above, the sealing resin may be transparent.
【００２０】請求項４に記載されているように、前記半
導体装置において、前記半導体基板の上に前記素子電極
の上方を開口して形成され、半導体素子を保護するため
のパッシベーション膜をさらに設けて、前記弾性体層を
前記パッシベーション膜の上に形成しておくことができ
る。According to a fourth aspect of the present invention, in the semiconductor device, a passivation film for protecting the semiconductor element is further provided on the semiconductor substrate, the opening being formed above the element electrode. The elastic layer may be formed on the passivation film.
【００２１】これにより、より信頼性の高い半導体装置
を得ることができる。Thus, a more reliable semiconductor device can be obtained.
【００２２】本発明の半導体装置の製造方法は、請求項
５に記載されているように、半導体基板上の主面上に透
明な絶縁樹脂層を形成する第１の工程と、前記絶縁樹脂
層のうち前記素子電極の上方に位置する領域を選択的に
除去して、前記素子電極を露出させる開口部を形成する
第２の工程と、前記素子電極にバンプ形成せ第３の工程
と、前記半導体基板を分割する第４の工程と、分割され
た前記半導体基板を樹脂基板に搭載する第５の工程と、
前記バンプと半導体基板の接合部を封止樹脂により封止
する第６の工程とを備えている。According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a transparent insulating resin layer on a main surface of a semiconductor substrate; A second step of selectively removing a region located above the element electrode to form an opening exposing the element electrode, a third step of forming a bump on the element electrode, A fourth step of dividing the semiconductor substrate, a fifth step of mounting the divided semiconductor substrate on a resin substrate,
And a sixth step of sealing the joint between the bump and the semiconductor substrate with a sealing resin.
【００２３】この方法により、チップに分離される前の
ウエハのままで、多数のチップ領域における画像素子上
に塗布した透明な絶縁樹脂層をパターニングすることに
より形成することができるので、製造コストを大幅に低
減することができる。よって、請求項１の半導体を容易
に実現することができる。According to this method, it is possible to form the transparent insulating resin layer applied on the image elements in a large number of chip areas by patterning the wafer as it is before being separated into chips. It can be significantly reduced. Therefore, the semiconductor of claim 1 can be easily realized.
【００２４】請求項６に記載されているように、前記半
導体装置の製造方法において、前記第１の工程の前にウ
エハを半導体チップ毎に切り離す工程をさらに備え、前
記第１〜第３の工程をチップ状態の半導体基板を用いて
行なってもよい。According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the method further comprises a step of separating a wafer into individual semiconductor chips before the first step. May be performed using a semiconductor substrate in a chip state.
【００２５】[0025]
【発明の実施の形態】以下、本発明の一実施形態につい
て、図面を参照しながら説明する。An embodiment of the present invention will be described below with reference to the drawings.
【００２６】まず、本発明の第１の実施形態について、
図１〜図４を参照しながら説明する。First, regarding the first embodiment of the present invention,
This will be described with reference to FIGS.
【００２７】図１は、本実施形態における半導体装置の
平面図であり、図２は本実施形態に係る半導体装置の断
面図、図３（ａ）〜（ｆ），図４（ａ）〜（ｃ）は本実
施形態における半導体装置の製造工程を示す断面図であ
る。FIG. 1 is a plan view of a semiconductor device according to the present embodiment, FIG. 2 is a cross-sectional view of the semiconductor device according to the present embodiment, and FIGS. 3 (a) to 3 (f) and 4 (a) to 4 (a). FIG. 3C is a cross-sectional view illustrating a manufacturing step of the semiconductor device in the embodiment.
【００２８】図１および図２において、１０はトランジ
スタ等の半導体素子および画像素子部１１によって構成
される半導体集積回路を内部に有する半導体基板であ
る。この半導体基板１０は、ウエハ状態であってもよい
し、ウエハから切り出されたチップ状態であってもよ
い。この半導体基板１０の主面の一部（電極配置領域）
には、半導体基板１０の素子電極１２が配置されてい
る。In FIGS. 1 and 2, reference numeral 10 denotes a semiconductor substrate having a semiconductor integrated circuit including a semiconductor element such as a transistor and an image element section 11 therein. The semiconductor substrate 10 may be in a wafer state or in a chip state cut out from the wafer. Part of the main surface of this semiconductor substrate 10 (electrode arrangement region)
, An element electrode 12 of a semiconductor substrate 10 is arranged.
【００２９】ただし、本実施形態では、電極配置領域
は、半導体基板がチップに分割されている場合には、そ
の周辺部である。また、半導体基板１０の主面上におい
て、素子電極１２を除く領域に絶縁樹脂層１３が設けら
れている。In the present embodiment, however, the electrode arrangement region is a peripheral portion when the semiconductor substrate is divided into chips. In addition, an insulating resin layer 13 is provided on the main surface of the semiconductor substrate 10 in a region excluding the device electrode 12.
【００３０】なお、半導体基板１０の主面のうち素子電
極１２以外の領域は、パッシベーション膜（図示せず）
によって覆われている。素子電極１２の上にはバンプ１
４が形成されており、貫通穴１５が設けられた樹脂基板
１６の配線金属１７と電気的に接続されている。A region other than the device electrode 12 on the main surface of the semiconductor substrate 10 is covered with a passivation film (not shown).
Covered by The bump 1 is formed on the device electrode 12.
4 are formed, and are electrically connected to the wiring metal 17 of the resin substrate 16 provided with the through holes 15.
【００３１】また、バンプ１４と配線金属１７の接続部
は、封止樹脂１８により保護されている。また、配線金
属の一部には外部電極としてはんだボール１９が搭載さ
れている。なお、樹脂基板１６は、配線金属１７のバン
プ１４との接続部およびはんだボール搭載部以外の領域
はソルダーレジスト２０で覆われている。The connection between the bump 14 and the wiring metal 17 is protected by a sealing resin 18. A solder ball 19 is mounted on a part of the wiring metal as an external electrode. The resin substrate 16 is covered with a solder resist 20 in a region other than a connection portion between the wiring metal 17 and the bump 14 and a solder ball mounting portion.
【００３２】本実施形態の半導体装置によると、半導体
基板１０の画像素子部１１が絶縁樹脂層１３により保護
されているので、外部からの機械的ダメージに強い構造
となっている。According to the semiconductor device of the present embodiment, since the image element portion 11 of the semiconductor substrate 10 is protected by the insulating resin layer 13, the structure is resistant to external mechanical damage.
【００３３】また、信頼性の観点から半導体基板の素子
電極と樹脂基板の配線金属との接合部を封止する必要が
あるがその際、絶縁樹脂は、封止樹脂の画素部への進入
を防止するダムの役割を果たすため、信頼性の高い実装
構造を実現することができる。From the viewpoint of reliability, it is necessary to seal the joint between the device electrode of the semiconductor substrate and the wiring metal of the resin substrate. At this time, the insulating resin prevents the sealing resin from entering the pixel portion. Since it plays a role of a dam for preventing, a highly reliable mounting structure can be realized.
【００３４】以上、本実施形態の半導体装置は、開口部
１５を有した樹脂基板１６上に画像素子部１１を含む半
導体素子が配置されている半導体基板１０がバンプ１４
を介して前記樹脂基板上の配線金属１７と接合され、前
記樹脂基板１６とバンプ１４との領域が封止樹脂１８で
封止され、前記半導体基板１０の画像素子部１１が絶縁
樹脂１３で部分的に被覆されて、その画像素子部１１が
前記樹脂基板１６の開口部１５に位置し、前記樹脂基板
１６上にはんだボール１９が外部端子として設けられて
いる半導体装置である。As described above, in the semiconductor device of the present embodiment, the semiconductor substrate 10 having the image element portion 11 on the resin substrate 16 having the opening 15
And a region between the resin substrate 16 and the bump 14 is sealed with a sealing resin 18, and the image element portion 11 of the semiconductor substrate 10 is partially The semiconductor device is a semiconductor device in which the image element portion 11 is covered with a mask, the image element portion 11 is located in the opening 15 of the resin substrate 16, and the solder ball 19 is provided on the resin substrate 16 as an external terminal.
【００３５】次に、本実施形態の半導体装置の製造方法
について、図３（ａ）〜（ｆ）および図４（ａ）〜
（ｃ）を参照しながら説明する。図３（ａ）〜（ｆ）お
よび図４（ａ）〜（ｃ）は、図１および図２に示す半導
体装置の構造を実現するための製造工程を示す断面図で
ある。Next, the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.
This will be described with reference to FIG. FIGS. 3A to 3F and FIGS. 4A to 4C are cross-sectional views showing manufacturing steps for realizing the structure of the semiconductor device shown in FIGS.
【００３６】まず、図３（ａ）に示すように表面に画像
素子部１１、素子電極１２を有した半導体基板１０を用
意し、そして図３（ｂ）に示すように、半導体基板１０
の主面にそれぞれ形成された半導体基板１０の画像素子
部１１と素子電極１２とパッシベーション膜（図示せ
ず）との上に、感光性を有する絶縁材料を３０［μｍ］
程度の厚みで塗布して乾燥することにより絶縁樹脂層１
３を形成する。First, as shown in FIG. 3A, a semiconductor substrate 10 having an image element portion 11 and an element electrode 12 on its surface is prepared, and as shown in FIG.
An insulating material having photosensitivity of 30 [μm] is formed on the image element portion 11, the element electrode 12, and the passivation film (not shown) of the semiconductor substrate 10 formed on the main surface of the semiconductor substrate 10, respectively.
Insulating resin layer 1
Form 3
【００３７】次に図３（ｃ）に示すように、乾燥された
絶縁樹脂層１３に対して露光と現像とを順次行って、半
導体基板１０の素子電極１１の部分が開口した絶縁樹脂
層１３を形成する。Next, as shown in FIG. 3C, exposure and development are sequentially performed on the dried insulating resin layer 13 so that the insulating resin layer 13 in which the element electrode 11 of the semiconductor substrate 10 is open is opened. To form
【００３８】なお、感光性を有する絶縁樹脂層１３の絶
縁材料としては、例えばカルド樹脂やアクリレート系エ
ポキシ等のポリマーでよく、絶縁性で透明であればよ
く、無色透明が望ましい。The insulating material of the insulating resin layer 13 having photosensitivity may be, for example, a cardo resin or a polymer such as an acrylate-based epoxy, as long as it is insulating and transparent, and preferably colorless and transparent.
【００３９】また、感光性を有する絶縁樹脂層１３は液
状材料を乾燥させて形成する必要はなく、フィルム状に
予め形成された材料を用いても構わない。その場合に
は、フィルム状の絶縁樹脂１３を半導体基板１０上に貼
りあわせ、露光、現像することで絶縁樹脂層１３に開口
部を形成することができ、半導体基板１０上の素子電極
１２を露出させることができる。The insulating resin layer 13 having photosensitivity does not need to be formed by drying a liquid material, and may be a material formed in a film shape in advance. In that case, an opening can be formed in the insulating resin layer 13 by bonding a film-shaped insulating resin 13 on the semiconductor substrate 10, exposing and developing, thereby exposing the element electrode 12 on the semiconductor substrate 10. Can be done.
【００４０】さらに、絶縁樹脂層１３を構成する絶縁材
料が感光性を有する必要はない。感光性を有しな絶縁材
料を用いる場合には、レーザーやプラズマによる機械的
な加工もしくはエッチングなどの化学的加工により、半
導体基板１０上の素子電極１２を露出させることができ
る。Further, the insulating material constituting the insulating resin layer 13 does not need to have photosensitivity. When an insulating material having no photosensitivity is used, the device electrode 12 on the semiconductor substrate 10 can be exposed by mechanical processing using laser or plasma or chemical processing such as etching.
【００４１】次に、図３（ｄ）に示すように、半導体基
板１０上の素子電極１２上にバンプ１４を電解めっき法
あるいは無電解めっき法を用いて形成する。なおバンプ
としては、Ｓｎ−Ｐｂ共晶はんだでもよく、Ｓｎ−Ｐｂ
高温はんだ、Ｎｉ、Ｓｎ、Ｃｕ、Ａｇ、Ａｕ等の金属お
よびその合金であってもよい。Next, as shown in FIG. 3D, bumps 14 are formed on the device electrodes 12 on the semiconductor substrate 10 by using an electrolytic plating method or an electroless plating method. In addition, Sn-Pb eutectic solder may be used as the bump, and Sn-Pb
High-temperature solder, metals such as Ni, Sn, Cu, Ag, and Au and alloys thereof may be used.
【００４２】次に、図３（ｅ），図３（ｆ）に示すよう
に、ダイシングソーにて、半導体基板１０をチップ単位
に分割する。Next, as shown in FIGS. 3E and 3F, the semiconductor substrate 10 is divided into chips by a dicing saw.
【００４３】次に、図４（ａ）に示すように、チップ状
の半導体構成体２１を樹脂基板１６の配線金属１７上に
搭載し、溶融することでバンプ１４と配線金属１７を電
気的に接続する。またソルダーレジスト２０で樹脂基板
１６上の配線金属１７のバンプ１４との接続部およびは
んだボール搭載部以外の領域を被覆する。Next, as shown in FIG. 4A, the chip-shaped semiconductor structure 21 is mounted on the wiring metal 17 of the resin substrate 16 and melted to electrically connect the bump 14 and the wiring metal 17. Connecting. In addition, the solder resist 20 covers a region other than the connection portion between the wiring metal 17 and the bump 14 on the resin substrate 16 and the solder ball mounting portion.
【００４４】なお、バンプ１４と配線金属１７との接続
は、導電性ペーストを用いても構わない。The connection between the bump 14 and the wiring metal 17 may be made using a conductive paste.
【００４５】次に、図４（ｂ）に示すように、封止樹脂
１８を用いてバンプ１４と配線金属１７の接合部を封止
する。Next, as shown in FIG. 4B, the joint between the bump 14 and the wiring metal 17 is sealed using a sealing resin 18.
【００４６】次に、図４（ｃ）に示すように、配線金属
１７の一部に外部電極としてはんだボール１９を搭載す
る。Next, as shown in FIG. 4C, a solder ball 19 is mounted on a part of the wiring metal 17 as an external electrode.
【００４７】なお、図５の別の半導体装置の形態を示す
断面図に示すように、はんだボール１９を樹脂基板１６
上の半導体構成体２１（半導体基板）が搭載される反対
側に形成してもよい。As shown in a cross-sectional view of another embodiment of the semiconductor device shown in FIG.
It may be formed on the opposite side where the upper semiconductor structure 21 (semiconductor substrate) is mounted.
【００４８】以上の工程によって、本実施形態に係る半
導体装置を得ることができる。Through the above steps, the semiconductor device according to the present embodiment can be obtained.
【００４９】[0049]
【発明の効果】本発明の半導体装置は、画像素子部が絶
縁樹脂により保護されているので、機械的なダメージに
強い半導体装置である。さらにフリップチップ接続され
ており、ガラスプレート等の部材が必要でないため薄型
の半導体装置である。The semiconductor device of the present invention is a semiconductor device which is resistant to mechanical damage since the image element portion is protected by the insulating resin. Further, the semiconductor device is a thin semiconductor device because it is flip-chip connected and does not require a member such as a glass plate.
【００５０】またその製造方法においては、封止樹脂の
流出を画像素子部に形成した絶縁樹脂により防止できる
ため、画像素子部を覆うこと無く、バンプと樹脂基板の
配線金属との接続部を保護することができるので、より
低コストで高性能な小型半導体装置を形成することがで
きる。In the manufacturing method, since the sealing resin can be prevented from leaking out by the insulating resin formed on the image element portion, the connection portion between the bump and the wiring metal of the resin substrate can be protected without covering the image element portion. Therefore, a small-sized semiconductor device with higher performance and lower cost can be formed.
【図１】本発明の一実施形態における半導体装置を示す
平面図FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の一実施形態における半導体装置を示す
断面図FIG. 2 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図３】本発明の一実施形態における半導体装置の製造
工程を示す断面図FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;
【図４】本発明の一実施形態における半導体装置の製造
工程を示す断面図FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention;
【図５】本発明の一実施形態における半導体装置を示す
断面図FIG. 5 is a sectional view showing a semiconductor device according to one embodiment of the present invention;
【図６】従来の半導体装置を示す断面図FIG. 6 is a sectional view showing a conventional semiconductor device.
１０ 半導体基板 １１ 画像素子部 １２ 素子電極 １３ 絶縁樹脂層 １４ バンプ １５ 貫通穴 １６ 樹脂基板 １７ 配線金属 １８ 封止樹脂 １９ はんだボール ２０ ソルダーレジスト ２１ 半導体構成体 １０１ ウエハー １０２ 画像素子部 １０３ 電極パッド １０４ 封止樹脂 １０５ リードフレーム １０６ ダイスボンド材 １０７ Ａｕ線 １０８ ガラスプレート REFERENCE SIGNS LIST 10 semiconductor substrate 11 image element section 12 element electrode 13 insulating resin layer 14 bump 15 through hole 16 resin substrate 17 wiring metal 18 sealing resin 19 solder ball 20 solder resist 21 semiconductor structure 101 wafer 102 image element section 103 electrode pad 104 sealing Stop resin 105 Lead frame 106 Die bond material 107 Au wire 108 Glass plate
───────────────────────────────────────────────────── フロントページの続き (72)発明者 戒能 憲幸 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 植田 賢治 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 竹村 康司 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 丸尾 哲正 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 (72)発明者 松村 信弥 大阪府高槻市幸町１番１号 松下電子工業 株式会社内 Ｆターム(参考） 4M118 AA08 AA10 AB01 BA08 BA14 HA25 HA31 HA40 5F044 KK02 LL07 LL11 LL15 QQ00 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Noriyuki Kaino, Inventor 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation (72) Inventor Kenji Ueda 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics (72) Inventor Koji Takemura 1-1, Sachimachi, Takatsuki-shi, Osaka, Japan Matsushita Electronics Corporation (72) Inventor Tetsumasa Maruo 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics, Inc. 72) Inventor: Shinya Matsumura 1-1-1, Komachi, Takatsuki-shi, Osaka Prefecture F-term (reference) 4M118 AA08 AA10 AB01 BA08 BA14 HA25 HA31 HA40 5F044 KK02 LL07 LL11 LL15 QQ00
Claims (6)
を含む半導体素子が配置されている半導体基板がバンプ
を介して前記樹脂基板上の配線金属と接合され、前記樹
脂基板とバンプとの領域が封止樹脂で封止され、前記半
導体基板の画像素子部が絶縁樹脂で部分的に被覆され
て、前記画像素子部が前記樹脂基板の開口部に位置し、
前記樹脂基板上に外部端子が設けられていることを特徴
とする半導体装置。1. A semiconductor substrate having a semiconductor element including an image element portion disposed on a resin substrate having an opening is joined to a wiring metal on the resin substrate via a bump, and the resin substrate and the bump are connected to each other. Region is sealed with a sealing resin, the image element portion of the semiconductor substrate is partially covered with an insulating resin, the image element portion is located at the opening of the resin substrate,
A semiconductor device, wherein external terminals are provided on the resin substrate.
記絶縁樹脂は、画像素子部の外周に形成されていること
を特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said insulating resin is formed on an outer periphery of an image element portion.
記封止樹脂は無色透明であることを特徴とする半導体装
置。3. The semiconductor device according to claim 1, wherein said sealing resin is colorless and transparent.
の半導体装置において、前記半導体素子の上に前記素子
電極の上方を開口して形成され、半導体素子を保護する
ためのパッシベーション膜をさらに備え、前記絶縁層
は、前記パッシベーション膜の上に形成されていること
を特徴とする半導体装置。4. The passivation film for protecting a semiconductor element according to claim 1, wherein said semiconductor element is formed on said semiconductor element with an opening above said element electrode. And the insulating layer is formed on the passivation film.
層を形成する第１の工程と、前記絶縁樹脂層のうち前記
素子電極の上方に位置する領域を選択的に除去して、前
記素子電極を露出させる開口部を形成する第２の工程
と、前記素子電極にバンプ形成せ第３の工程と、前記半
導体基板を分割する第４の工程と、分割された前記半導
体基板を樹脂基板に搭載する第５の工程と、前記バンプ
と半導体基板の接合部を封止樹脂により封止する第６の
工程とを備えていることを特徴とする半導体装置の製造
方法。5. A first step of forming a transparent insulating resin layer on a main surface of a semiconductor substrate, and selectively removing a region of the insulating resin layer located above the element electrode, A second step of forming an opening for exposing the element electrode, a third step of forming a bump on the element electrode, a fourth step of dividing the semiconductor substrate, A method of manufacturing a semiconductor device, comprising: a fifth step of mounting on a substrate; and a sixth step of sealing a joint between the bump and the semiconductor substrate with a sealing resin.
おいて、前記第１の工程の前に、ウエハを半導体チップ
毎に切り離す工程をさらに備え、前記第１〜３の工程
は、チップ状態の半導体基板を用いて行われることを特
徴とする半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, further comprising, before the first step, a step of separating the wafer into semiconductor chips, wherein the first to third steps are performed in a chip state. A method for manufacturing a semiconductor device, wherein the method is performed using a semiconductor substrate.
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| JP2000113772A JP4244096B2 (en) | 2000-04-14 | 2000-04-14 | Semiconductor device and manufacturing method thereof |
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| JP2000113772A JP4244096B2 (en) | 2000-04-14 | 2000-04-14 | Semiconductor device and manufacturing method thereof |
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| JP2008124278A Division JP2008219041A (en) | 2008-05-12 | 2008-05-12 | Semiconductor device and method of manufacturing the same |
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| JP4244096B2 JP4244096B2 (en) | 2009-03-25 |
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Cited By (6)
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|---|---|---|---|---|
| JP2004165191A (en) * | 2002-11-08 | 2004-06-10 | Oki Electric Ind Co Ltd | Semiconductor device, method of manufacturing semiconductor device, and camera system |
| WO2006025698A1 (en) * | 2004-09-02 | 2006-03-09 | Optopac, Inc. | Method of making camera module in wafer level |
| JP2006147916A (en) * | 2004-11-22 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Optical device and optical equipment |
| US7154156B2 (en) | 2003-04-28 | 2006-12-26 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
| JP2007507879A (en) * | 2003-10-01 | 2007-03-29 | オプトパック、インコーポレイテッド | Electronic package for semiconductor device for photodetection and packaging method thereof |
| JP2007523473A (en) * | 2004-01-15 | 2007-08-16 | オプトパック、インコーポレイテッド | Photo image sensor electronic package in mobile phone camera module and its manufacture and assembly |
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2000
- 2000-04-14 JP JP2000113772A patent/JP4244096B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004165191A (en) * | 2002-11-08 | 2004-06-10 | Oki Electric Ind Co Ltd | Semiconductor device, method of manufacturing semiconductor device, and camera system |
| US7525167B2 (en) | 2002-11-08 | 2009-04-28 | Oki Semiconductor Co., Ltd. | Semiconductor device with simplified constitution |
| US7154156B2 (en) | 2003-04-28 | 2006-12-26 | Matsushita Electric Industrial Co., Ltd. | Solid-state imaging device and method for producing the same |
| US7367120B2 (en) | 2003-04-28 | 2008-05-06 | Matsushita Electric Industrial Co., Ltd. | Method for producing a solid-state imaging device |
| JP2007507879A (en) * | 2003-10-01 | 2007-03-29 | オプトパック、インコーポレイテッド | Electronic package for semiconductor device for photodetection and packaging method thereof |
| JP2010283380A (en) * | 2003-10-01 | 2010-12-16 | Optopac Inc | Electronic package of photo-sensing semiconductor device, and packaging method thereof |
| JP2007523473A (en) * | 2004-01-15 | 2007-08-16 | オプトパック、インコーポレイテッド | Photo image sensor electronic package in mobile phone camera module and its manufacture and assembly |
| WO2006025698A1 (en) * | 2004-09-02 | 2006-03-09 | Optopac, Inc. | Method of making camera module in wafer level |
| JP2008512851A (en) * | 2004-09-02 | 2008-04-24 | オプトパック、インコーポレイテッド | Method for manufacturing camera module at wafer level |
| JP2006147916A (en) * | 2004-11-22 | 2006-06-08 | Matsushita Electric Ind Co Ltd | Optical device and optical equipment |
| US7302125B2 (en) | 2004-11-22 | 2007-11-27 | Matsushita Electric Industrial Co., Ltd. | Optical device and optical apparatus |
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