JPH0410649A - Manufacture of semiconductor substrate for three-dimensional packaging - Google Patents

Manufacture of semiconductor substrate for three-dimensional packaging

Info

Publication number
JPH0410649A
JPH0410649A JP11344690A JP11344690A JPH0410649A JP H0410649 A JPH0410649 A JP H0410649A JP 11344690 A JP11344690 A JP 11344690A JP 11344690 A JP11344690 A JP 11344690A JP H0410649 A JPH0410649 A JP H0410649A
Authority
JP
Japan
Prior art keywords
substrate
holes
semiconductor substrate
insulator
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11344690A
Other languages
Japanese (ja)
Other versions
JP2847890B2 (en
Inventor
Shinichiro Ishida
進一郎 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP11344690A priority Critical patent/JP2847890B2/en
Publication of JPH0410649A publication Critical patent/JPH0410649A/en
Application granted granted Critical
Publication of JP2847890B2 publication Critical patent/JP2847890B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To stick to laminate many semiconductor substrates directly by forming pads, which are connected to each other through holes, on both faces of the semiconductor substrates. CONSTITUTION:Circuits 1a and electrode pads 1b are formed on one face of an Si substrate 1. The face, having the circuits 1a, of the Si substrate 1 is attached to an SiO2 substrate 11 as a supporting substrate and then the Si substrate 1 is abraded to a thickness of about several micrometers. Through holes 2 are made by reactive ion etching(RIE), where the electrode pads 1b are formed. The through holes are filled with an insulator 3 such as SiO2 by the CVD method, and the insulator 3 is laminated on the abraded face of the Si substrate 1. Smaller through holes 4 than the through holes 2 are made in the insulator 3 in the through holes 2 by windowing and a film of a conductor such as Al is formed by sputtering or deposition and patterned to make connection pads 5 connected to the electrode pads 1b through the through holes 4.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は3次元高密度実装用の半導体回路基板の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor circuit board for three-dimensional high-density packaging.

〈従来の技術〉 高密度3次元ICを得るためには、回路が形成された半
導体基板を多層に積層して、相互に電気的に接続する必
要がある。
<Prior Art> In order to obtain a high-density three-dimensional IC, it is necessary to stack semiconductor substrates on which circuits are formed in multiple layers and electrically connect them to each other.

従来、3次元ICを得る技術としては、各ICの入出力
間における張り合わせ方式、また素子レベルでの張り合
わせ方式、あるいはモノリシック方式等がある。これら
の方式のうち、入出力間における張り合わせ方式は、技
術上の問題が少なく生産が容易で、かつ歩留りが高い点
、さらには種々の機能をもつICを積層できる等の利点
がある。
Conventionally, techniques for obtaining three-dimensional ICs include a method of bonding between input and output of each IC, a method of bonding at the element level, a monolithic method, and the like. Among these methods, the bonding method between input and output has advantages such as fewer technical problems, easy production, high yield, and the ability to stack ICs with various functions.

〈発明が解決しようとする課題〉 ところで、上述の入出力間での張り合わせ方式において
は、パッド電極の面積を大きくとる必要があり、集積度
の高度化は困難で、しかも、各ICチップ間に隙間があ
るため、チップの冷却効果が低いといった問題が残され
ている。
<Problem to be solved by the invention> By the way, in the above-mentioned bonding method between input and output, it is necessary to take a large area for the pad electrode, making it difficult to increase the degree of integration. The problem remains that the chip cooling effect is low because of the gaps.

〈課題を解決するための手段〉 上記の従来の問題点を解決するために、本発明では、実
施例に対応する第1図に示すように、−面に回路1aお
よび電極パッド1bが形成された半導体基板1にスルー
ホール4を穿って、電極パッド1bを半導体基板1の他
面側に露呈させた後、その半導体基板1の他面に、スル
ーホール4を通じて電極パッド1bに導通ずる接続パッ
ド5を形成している。
<Means for Solving the Problems> In order to solve the above conventional problems, in the present invention, as shown in FIG. 1 corresponding to the embodiment, a circuit 1a and an electrode pad 1b are formed on the negative side. After drilling a through hole 4 in the semiconductor substrate 1 to expose the electrode pad 1b on the other surface of the semiconductor substrate 1, a connection pad is formed on the other surface of the semiconductor substrate 1 to be electrically connected to the electrode pad 1b through the through hole 4. 5 is formed.

〈作用〉 半導体基板1の両面にスルーホール4を通じて互いに導
通するパッド1bおよび5を形成することにより、半導
体基板1を多層に積層するにあたり、各基板1を直接的
に張り合わせることが可能となる。
<Function> By forming pads 1b and 5 that are electrically connected to each other through through holes 4 on both sides of semiconductor substrate 1, it becomes possible to directly bond each substrate 1 together when stacking semiconductor substrates 1 in multiple layers. .

〈実施例〉 本発明の実施例を、以下、図面に基づいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.

第1図は本発明実施例の工程説明図である。FIG. 1 is a process explanatory diagram of an embodiment of the present invention.

まず、(a)に示すように、−面に回路1aおよび電極
パッド1bを形成したSi基板1を、その回路1aの側
の面を、支持基板としてのS i O7基板11に接着
し、この状態で、Si基板1を研磨して数μm程度の厚
さにする[有])。
First, as shown in (a), a Si substrate 1 on which a circuit 1a and an electrode pad 1b are formed on the negative side is bonded with its circuit 1a side side to an SiO7 substrate 11 serving as a supporting substrate. In this state, the Si substrate 1 is polished to a thickness of approximately several μm.

次に、RIE (リアクティブイオンエツチング)法等
により、電極パッド1bの形成位置に貫通孔2を開孔し
た後(C)、CVD法により、S i 0,2等の絶縁
物3を貫通孔2に充填するとともに、Si基板1の研磨
面に積層する(d)。
Next, after a through hole 2 is formed at the formation position of the electrode pad 1b by RIE (reactive ion etching) method or the like (C), an insulator 3 such as S i 0, 2 is formed in the through hole by a CVD method. 2 and laminated on the polished surface of the Si substrate 1 (d).

次に、RIE法等により貫通孔2に充填した絶縁物3の
窓明けを行って、その貫通孔2よりも小さなスルーホー
ル4を形成する(e)。そして、スパッタもしくは蒸着
法等によって、A1等の導電性物質を成膜した後、その
膜のパターニングを行うことによって、げ)に示すよう
に、電極パッド1bにスルーホール4を通じて導通する
接続パッド5を得る。以上の手順により、厚さが数μm
程度で、かつ両面にパッド1aおよび5が形成されたS
i半導体回路基板を得ることができる。
Next, the insulator 3 filled in the through hole 2 is opened by RIE method or the like to form a through hole 4 smaller than the through hole 2 (e). After forming a film of a conductive material such as A1 by sputtering or vapor deposition, the film is patterned to form a connection pad 5 that is electrically connected to the electrode pad 1b through the through hole 4, as shown in FIG. get. By the above procedure, the thickness is several μm.
S with pads 1a and 5 formed on both sides.
i A semiconductor circuit board can be obtained.

以上のような半導体回路基板を、一般に用いられている
ICの張り合わせ法によって、3次元化するわけである
が、その方法を以下に述べる。第2図はその手順を説明
する図である。
The semiconductor circuit board as described above is made three-dimensional by a commonly used IC bonding method, and the method will be described below. FIG. 2 is a diagram explaining the procedure.

まず、第1図の工程で得られた半導体回路基板の接続パ
ッド5上に、張り合わせのための垂直配線6を形成する
(a)。なお、7は絶縁膜である。次いで、(ハ)に示
すように、ポリイミド8により表面の平坦化行っておく
First, vertical interconnections 6 for bonding are formed on the connection pads 5 of the semiconductor circuit board obtained in the process shown in FIG. 1 (a). Note that 7 is an insulating film. Next, as shown in (c), the surface is flattened using polyimide 8.

次に、上記の(a)、 (b)工程において得られた回
路基板を二つ用意しておき、この二つの回路基板を(C
)に示すように、相互に対向させ、かつ、その垂直配線
6を互いに接触させた状態で、その両者を熱圧着により
接続する。次いで支持基板としてのSiO□基板11の
いずれか一方を剥がすことによって、(d)に示すよう
な積層構造を得る。そして以上の(a)〜(d)工程を
順次繰り返すことによって、半導体回路が多層に積層さ
れた構造、つまり3次元ICを実現できる。このような
3次元ICで例えばセンサ用の増幅回路等を作成するこ
とによって、センサチップと一体化したコンパクトなセ
ンサユニットを構築することができる。
Next, prepare two circuit boards obtained in steps (a) and (b) above, and combine these two circuit boards with (C
), the two are connected by thermocompression bonding with the vertical wires 6 facing each other and in contact with each other. Next, by peeling off one of the SiO□ substrates 11 as supporting substrates, a laminated structure as shown in (d) is obtained. By sequentially repeating the above steps (a) to (d), a structure in which semiconductor circuits are stacked in multiple layers, that is, a three-dimensional IC can be realized. By creating, for example, an amplifier circuit for a sensor using such a three-dimensional IC, a compact sensor unit integrated with a sensor chip can be constructed.

なお、以上の本発明実施例によると、半導体基板1に穿
った貫通孔2に絶縁物3を充填した後、その絶縁物3に
、貫通孔2よりも小さいスルーホール4を形成するので
、後の工程においてそのスルーホール4の内部に充填さ
れる導電材は、半導体基板1に対して電気的に絶縁され
、これにより信号入出力による影響が半導体基板1に及
ぶこと等を防止することができる。
According to the embodiment of the present invention described above, after the through hole 2 drilled in the semiconductor substrate 1 is filled with the insulator 3, the through hole 4, which is smaller than the through hole 2, is formed in the insulator 3. The conductive material filled inside the through hole 4 in the process is electrically insulated from the semiconductor substrate 1, thereby preventing the influence of signal input/output from reaching the semiconductor substrate 1. .

〈発明の効果〉 以上説明したように、本発明によれば、半導体基板の両
面に、その基板そのものに形成したスルーホールを通じ
て互いに導通ずるパッドを形成したから、任意複数枚の
半導体基板を多層化することが可能となって、大規模の
3次元ICを容易に実現できる。しかも、各半導体基板
を直接的に張り合わせることができることから、そのパ
ッド面積を狭(することが可能となり、高密度の3次元
ICを得ることができるとともに、半導体基板の冷却効
率も向上する。
<Effects of the Invention> As explained above, according to the present invention, pads that are electrically connected to each other through through holes formed in the substrate itself are formed on both sides of the semiconductor substrate, so that any number of semiconductor substrates can be multilayered. This makes it possible to easily realize large-scale three-dimensional ICs. Furthermore, since each semiconductor substrate can be directly bonded together, the pad area can be reduced, a high-density three-dimensional IC can be obtained, and the cooling efficiency of the semiconductor substrate can also be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の工程説明図、第2図は本発明実
施例によって得られた半導体回路基板を用いて、3次元
ICを構築する手順の例を説明する図である。 1・・・St基板 1a・・・回路 1b・・・電極パッド 2・・・貫通孔 ・絶縁物 ・ スルーホール ・接続パッド ・垂直配線 ・絶縁膜 ・ポリイミド
FIG. 1 is a process explanatory diagram of an embodiment of the present invention, and FIG. 2 is a diagram illustrating an example of a procedure for constructing a three-dimensional IC using a semiconductor circuit board obtained by an embodiment of the present invention. 1...St substrate 1a...Circuit 1b...Electrode pad 2...Through hole, insulator, through hole, connection pad, vertical wiring, insulating film, polyimide

Claims (1)

【特許請求の範囲】[Claims]  一面に回路および電極パッドが形成された半導体基板
にスルーホールを穿って、上記電極パッドを上記半導体
基板の他面側に露呈させた後、その半導体基板の他面に
、上記スルーホールを通じて上記電極パッドに導通する
接続パッドを形成する、3次元実装用半導体基板の製造
方法。
A through hole is formed in a semiconductor substrate on which a circuit and an electrode pad are formed on one side, and the electrode pad is exposed on the other side of the semiconductor substrate. A method for manufacturing a semiconductor substrate for three-dimensional mounting, which forms a connection pad that is conductive to a pad.
JP11344690A 1990-04-27 1990-04-27 Method of manufacturing semiconductor substrate for three-dimensional mounting Expired - Lifetime JP2847890B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11344690A JP2847890B2 (en) 1990-04-27 1990-04-27 Method of manufacturing semiconductor substrate for three-dimensional mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11344690A JP2847890B2 (en) 1990-04-27 1990-04-27 Method of manufacturing semiconductor substrate for three-dimensional mounting

Publications (2)

Publication Number Publication Date
JPH0410649A true JPH0410649A (en) 1992-01-14
JP2847890B2 JP2847890B2 (en) 1999-01-20

Family

ID=14612439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11344690A Expired - Lifetime JP2847890B2 (en) 1990-04-27 1990-04-27 Method of manufacturing semiconductor substrate for three-dimensional mounting

Country Status (1)

Country Link
JP (1) JP2847890B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856023B2 (en) 2002-01-22 2005-02-15 Canon Kabushiki Kaisha Semiconductor device and method of manufacturing semiconductor device
JP2008028407A (en) * 1997-04-04 2008-02-07 Glenn J Leedy Information processing method
US8035233B2 (en) 1997-04-04 2011-10-11 Elm Technology Corporation Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer
US8080442B2 (en) 2002-08-08 2011-12-20 Elm Technology Corporation Vertical system integration
JP2012178520A (en) * 2011-02-28 2012-09-13 Elpida Memory Inc Semiconductor apparatus and manufacturing method thereof

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011181176A (en) * 1997-04-04 2011-09-15 Glenn J Leedy Information processing method and laminated integrated circuit memory
US8288206B2 (en) 1997-04-04 2012-10-16 Elm Technology Corp Three dimensional structure memory
JP2008028407A (en) * 1997-04-04 2008-02-07 Glenn J Leedy Information processing method
JP2008166831A (en) * 1997-04-04 2008-07-17 Glenn J Leedy Method of processing information
JP2008166832A (en) * 1997-04-04 2008-07-17 Glenn J Leedy Information processing method
JP2008172254A (en) * 1997-04-04 2008-07-24 Glenn J Leedy Information processing method
US8410617B2 (en) 1997-04-04 2013-04-02 Elm Technology Three dimensional structure memory
US8035233B2 (en) 1997-04-04 2011-10-11 Elm Technology Corporation Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer
US8318538B2 (en) 1997-04-04 2012-11-27 Elm Technology Corp. Three dimensional structure memory
US6856023B2 (en) 2002-01-22 2005-02-15 Canon Kabushiki Kaisha Semiconductor device and method of manufacturing semiconductor device
US7125810B2 (en) 2002-01-22 2006-10-24 Canon Kabushiki Kaisha Semiconductor device and method of manufacturing semiconductor device
US8080442B2 (en) 2002-08-08 2011-12-20 Elm Technology Corporation Vertical system integration
US8269327B2 (en) 2002-08-08 2012-09-18 Glenn J Leedy Vertical system integration
JP2012178520A (en) * 2011-02-28 2012-09-13 Elpida Memory Inc Semiconductor apparatus and manufacturing method thereof

Also Published As

Publication number Publication date
JP2847890B2 (en) 1999-01-20

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