JP3171172B2 - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JP3171172B2
JP3171172B2 JP27181598A JP27181598A JP3171172B2 JP 3171172 B2 JP3171172 B2 JP 3171172B2 JP 27181598 A JP27181598 A JP 27181598A JP 27181598 A JP27181598 A JP 27181598A JP 3171172 B2 JP3171172 B2 JP 3171172B2
Authority
JP
Japan
Prior art keywords
integrated circuit
wiring
substrate
wiring layer
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27181598A
Other languages
Japanese (ja)
Other versions
JP2000101015A (en
Inventor
宏希 平沢
臣吾 柳原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27181598A priority Critical patent/JP3171172B2/en
Priority to US09/401,128 priority patent/US6340839B1/en
Publication of JP2000101015A publication Critical patent/JP2000101015A/en
Application granted granted Critical
Publication of JP3171172B2 publication Critical patent/JP3171172B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、複数の集積回路
が搭載される混成集積回路に関する。The present invention relates to a hybrid integrated circuit on which a plurality of integrated circuits are mounted.

【０００２】[0002]

【従来の技術】近年、ＬＳＩの高集積化・高速化は著し
く、多ピンでクロック周波数が１００ＭＨｚ以上で動作
するチップが出現し始めている。このような高速動作す
るチップのシングルチップ実装では、パッケージとプリ
ント基板を伝送する信号遅延が大きくなり、また、パッ
ケージの持つ寄生容量やインダクタンスの影響も、シス
テム設計上無視できなくなってきている。そして、それ
らのことが、システム全体の高速化を妨げる要因となっ
てきている。そこで、混成集積回路（マルチチップモジ
ュール：ＭＣＭ）とすることで、チップ同士をできるだ
け近づけて配置してパッケージに起因するチップ間の信
号遅延が減らせ、単一チップでの高速性を、複数チップ
のシステムでも損なわずに引き出すことが可能となる。2. Description of the Related Art In recent years, high integration and high speed of LSIs have been remarkable, and chips which operate at a clock frequency of 100 MHz or more with many pins have begun to appear. In such single-chip mounting of a chip that operates at a high speed, the signal delay transmitted between the package and the printed circuit board increases, and the influence of the parasitic capacitance and inductance of the package cannot be ignored in system design. These factors have become factors that hinder the speeding up of the entire system. Therefore, by adopting a hybrid integrated circuit (multi-chip module: MCM), the chips are arranged as close as possible to reduce the signal delay between chips due to the package, and the high speed of a single chip can be reduced. It is possible to draw out without damaging the system.

【０００３】図６は、そのようなＭＣＭの構成を示す断
面図である。このＭＣＭの構成について説明すると、ま
ず、リードフレーム６０１上のアイランド部６０１ａ上
に絶縁層６０２を介して配線層６０３が形成され、この
配線層６０３上に層間絶縁膜６０４を介して上層配線層
６０５が形成されている。そして、上層配線層６０５上
の所定位置に集積回路チップ６０６や抵抗チップ６０７
が実装されている。また、集積回路チップ６０６は、上
層配線層６０５の所定の所にワイヤー６０８で接続され
ている。また、上層配線層６０５の所定箇所とリード６
０１ｂとが、それぞれワイヤー６０８ａで接続されてい
る。そして、リード６０１ｂの先端が露出した状態で、
モールド樹脂６０９により封止されている。FIG. 6 is a sectional view showing the structure of such an MCM. The structure of the MCM will be described. First, a wiring layer 603 is formed on an island portion 601 a on a lead frame 601 via an insulating layer 602, and an upper wiring layer 605 is provided on the wiring layer 603 via an interlayer insulating film 604. Are formed. The integrated circuit chip 606 and the resistor chip 607 are placed at predetermined positions on the upper wiring layer 605.
Has been implemented. The integrated circuit chip 606 is connected to a predetermined portion of the upper wiring layer 605 by a wire 608. Also, a predetermined portion of the upper wiring layer 605 and the lead 6
01b are connected by wires 608a. Then, with the tip of the lead 601b exposed,
It is sealed with a mold resin 609.

【０００４】[0004]

【発明が解決しようとする課題】ところで、上述した従
来のＭＣＭでは、混載している各集積回路チップに接続
する接地の配線は、図６の配線層６０３に形成されてい
る。そして、その接地の配線は、アイランド部６０１ａ
の周端部に近いところで、上層配線層６０５に形成され
ている電極部に層間絶縁膜６０４を介して接続し、その
電極部より所定のリードに、ワイヤーにより接続するよ
うにしていた。ところが、その配線層６０３には、当然
であるが、接地に接続しては問題となる多くの配線が形
成されている。このため、従来では、配線層６０３にお
いて、上述した接地のための配線の引き回しが非常に複
雑になるため、混載する集積回路チップの数を多くでき
ないという問題があった。この発明は、以上のような問
題点を解消するためになされたものであり、ＭＣＭの集
積度をより向上させることを目的とする。By the way, in the above-mentioned conventional MCM, the ground wiring connected to each integrated circuit chip is formed in the wiring layer 603 in FIG. The ground wiring is connected to the island portion 601a.
Is connected to an electrode portion formed in the upper wiring layer 605 via an interlayer insulating film 604, and is connected to a predetermined lead from the electrode portion by a wire. However, the wiring layer 603 has a number of wirings which are of course problematic when connected to the ground. For this reason, in the related art, there is a problem in that the routing of the wiring for grounding described above becomes very complicated in the wiring layer 603, so that the number of integrated circuit chips to be mounted cannot be increased. The present invention has been made to solve the above problems, and has as its object to further improve the integration degree of the MCM.

【０００５】[0005]

【課題を解決するための手段】この発明の混成集積回路
は、金属からなる基板と、この基板の表面上に絶縁層を
介して形成された配線層からなる複数の配線と、配線層
上に配置されて所定の配線と接続端子が接続された集積
回路チップと、基板周辺に基板と絶縁分離されて配置さ
れ所定の配線に接続された複数の端子とを備え、加え
て、絶縁層に接続端子が接続された所定の配線から基板
に接続する貫通接続部を備え、この貫通接続部および基
板を介して接続端子が接続された所定の配線に固定電位
が接続されているようにした。従って、基板が固定電位
の端子となる。また、この発明の混成集積回路は、金属
からなる基板と、この基板表面上に配線を含む配線層と
絶縁層が交互に複数積層された多層配線構造体が構成さ
れ、最上層の配線層上に配置されて多層配線構造体の最
上層の所定の配線と接続端子が接続された集積回路チッ
プと、基板周辺に基板と絶縁分離されて配置されて多層
配線構造体の所定の配線に接続された複数の端子とを備
え、加えて、複数の絶縁層に接続端子が接続された所定
の配線から基板に接続する貫通接続部を備え、この貫通
接続部および基板を介して接続端子が接続された所定の
配線に固定電位が接続されているようにした。従って、
基板が固定電位の端子となる。Means for Solving the Problems] hybrid integrated circuit of the present invention comprises a substrate made of a metal, a plurality of wires made of a wiring layer formed through an insulating layer on the surface of the substrate, the wiring layer <br /> disposed on comprises a given integrated circuit chip wiring and the connecting terminal is connected, and a plurality of terminals are arranged to be substrate and the insulating isolation connected to predetermined wiring around the substrate, in addition, It is provided with a through connection portion connecting a predetermined wiring with the connection terminal connected to the insulating layer to the substrate, and a fixed potential is connected to the predetermined wiring to which the connection terminal is connected via the through connection portion and the substrate. I made it. Therefore, the substrate serves as a fixed potential terminal. Further, the hybrid integrated circuit of the present invention comprises a metal substrate and a wiring layer including wiring on the surface of the substrate.
A multilayer wiring structure in which a plurality of insulating layers are alternately stacked is configured.
And placed on the uppermost wiring layer to
An integrated circuit chip connected to the upper layer of the predetermined wiring terminal is connected, is arranged to be substrate and the insulating isolation around the substrate a multilayer
And a plurality of terminals connected to a predetermined wiring of the wiring structure, in addition, the connection terminals are connected to a plurality of insulating layers given
A through connection portion for connecting the wiring to the substrate, and a connection terminal connected to the connection terminal via the through connection portion and the substrate .
A fixed potential was connected to the wiring . Therefore,
The substrate serves as a fixed potential terminal.

【０００６】[0006]

【発明の実施の形態】以下この発明の実施の形態を図を
参照して説明する。 実施の形態１ はじめに、この発明の第１の実施の形態について説明す
る。図１は、この実施の形態１における混成集積回路の
概略的な構成を示す斜視図および断面図である。なお、
（ａ）は斜視図、（ｂ）は断面図である。この実施の形
態１の混成集積回路について説明すると、まず、金属板
から構成されたリードフレーム１０１のアイランド１０
１ａ上に、下部絶縁層１０２を介して第１配線層１０３
が形成されている。また、第１配線層１０３の一部の領
域上には、層間絶縁層１０４を介して第２配線層１０５
が形成され、この第２配線層１０５の所定のパタン上
に、集積回路チップ１０６や抵抗やコンデンサなどの単
一チップ１０７が配置されている。Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 First, a first embodiment of the present invention will be described. FIG. 1 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to the first embodiment. In addition,
(A) is a perspective view, (b) is a sectional view. The hybrid integrated circuit according to the first embodiment will be described. First, an island 10 of a lead frame 101 formed of a metal plate is used.
1a via a lower insulating layer 102 and a first wiring layer 103
Are formed. Further, on a part of the first wiring layer 103, a second wiring layer 105 is interposed via an interlayer insulating layer 104.
Are formed, and an integrated circuit chip 106 and a single chip 107 such as a resistor or a capacitor are arranged on a predetermined pattern of the second wiring layer 105.

【０００７】そして、第１配線層１０３と第２配線層１
０５とは、層間絶縁層１０４を貫通するビア内に形成さ
れた貫通接続部１０８を介して所定の箇所で接続してい
る。また、集積回路チップ１０６および単一チップ１０
７は、ワイヤ１０９ａにより第２配線層１０５の電極に
接続している。また、第１配線層１０３の電極パッド１
０３ａおよび第２配線層１０５の電極パッド１０５ａと
リード１０１ｂとは、ワイヤ１０９ｂで接続している。
そして、この実施の形態１では、各集積回路チップ１０
６の接地を、下部絶縁層１０２および層間絶縁層１０４
を貫通するスルーホール内に形成された貫通接続部１１
０を介し、アイランド１０１ａに接続させるようにし
た。すなわち、集積回路チップ１０６の接地などの固定
電位端子−第２配線層１０５の所定の電極−貫通接続部
１１０−アイランド１０１ａと接続するようにした。な
お、各集積回路チップ１０６への電源電位などの固定電
位の接続を、上述したように、貫通接続部１１０を介し
てアイランド１０１ａに接続させるようにしても良い。The first wiring layer 103 and the second wiring layer 1
05 is connected at a predetermined position via a through connection portion 108 formed in a via penetrating the interlayer insulating layer 104. Also, the integrated circuit chip 106 and the single chip 10
7 is connected to an electrode of the second wiring layer 105 by a wire 109a. The electrode pad 1 of the first wiring layer 103
03a and the electrode pad 105a of the second wiring layer 105 and the lead 101b are connected by a wire 109b.
In the first embodiment, each integrated circuit chip 10
6 to the lower insulating layer 102 and the interlayer insulating layer 104.
Connecting portion 11 formed in a through hole penetrating through
0 to the island 101a. That is, the connection is made to the fixed potential terminal such as the ground of the integrated circuit chip 106, the predetermined electrode of the second wiring layer 105, the through connection portion 110, and the island 101 a. Note that the connection of the fixed potential such as the power supply potential to each integrated circuit chip 106 may be connected to the island 101a via the through connection 110 as described above.

【０００８】なお、図示していないが、集積回路チップ
１０６やワイヤ１０９ａなどを含むリードフレーム１０
１上部を、モールド樹脂で覆い隠すようにしてもよい。
このように、回路形成部などをモールド樹脂で封止する
ことで、混成集積回路の信頼性を向上させることができ
る。以上説明したように、この実施の形態１では、混載
する集積回路チップそれぞれへの接地や電源電位などの
固定電位を、貫通接続部１１０およびアイランド１０１
ａを介して接続するようにしたので、たとえば、第１配
線層１０３や第２配線層１０５などの配線層において固
定電位接続のための配線を引き回す必要がなくなる。こ
の結果、たとえば、第１配線層１０３や第２配線層１０
５においては、固定電位接続のため以外の配線のための
領域をより多くとれるようになり、混載する集積回路チ
ップの数をより多くすることが可能となる。Although not shown, the lead frame 10 including the integrated circuit chip 106, the wires 109a, etc.
The upper part 1 may be covered with a mold resin.
As described above, by sealing the circuit forming portion and the like with the mold resin, the reliability of the hybrid integrated circuit can be improved. As described above, in the first embodiment, the fixed potentials such as the ground and the power supply potential for each of the integrated circuit chips to be mixed are applied to the through-connection portion 110 and the island 101.
Since the connection is made via a, there is no need to route wiring for fixed potential connection in wiring layers such as the first wiring layer 103 and the second wiring layer 105, for example. As a result, for example, the first wiring layer 103 or the second wiring layer 10
In 5, the area for the wiring other than the connection for the fixed potential can be increased, and the number of integrated circuit chips to be mounted can be increased.

【０００９】実施の形態２ 次に、この発明の第２の実施の形態について説明する。
図２は、この実施の形態２における混成集積回路の概略
的な構成を示す斜視図および断面図である。なお、
（ａ）は斜視図、（ｂ）は断面図である。この実施の形
態２の混成集積回路について説明すると、まず、金属板
から構成されたリードフレーム２０１のアイランド２０
１ａ上に、下部絶縁層２０２を介して第１配線層２０３
が形成されている。また、第１配線層２０３の一部の領
域上には、層間絶縁層２０４を介して第２配線層２０５
が形成され、この第２配線層２０５の所定のパタン上
に、集積回路チップ２０６や抵抗やコンデンサなどの単
一チップ２０７が配置されている。Second Embodiment Next, a second embodiment of the present invention will be described.
FIG. 2 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to the second embodiment. In addition,
(A) is a perspective view, (b) is a sectional view. The hybrid integrated circuit according to the second embodiment will be described. First, the island 20 of the lead frame 201 made of a metal plate is used.
1a via a lower insulating layer 202 and a first wiring layer 203
Are formed. Further, on a part of the first wiring layer 203, a second wiring layer 205 is interposed via an interlayer insulating layer 204.
Are formed, and an integrated circuit chip 206 and a single chip 207 such as a resistor or a capacitor are arranged on a predetermined pattern of the second wiring layer 205.

【００１０】そして、この実施の形態２においては、ア
イランド２０１ａの裏面にも、下部絶縁層２０２ａを介
して第１配線層２０３ａが形成されている。また、第１
配線層２０３ａの一部の領域上には、層間絶縁層２０４
ａを介して第２配線層２０５ａが形成され、この第２配
線層２０５ａの所定のパタン上に、前述したアイランド
２０１ａ表面上と同様に、集積回路チップ２０６ａや抵
抗やコンデンサなどの単一チップ２０７ａが配置されて
いるようにした。すなわち、この実施の形態２において
は、リードフレーム２０１の両面に集積回路チップを混
載するようにした。In the second embodiment, the first wiring layer 203a is also formed on the back surface of the island 201a via the lower insulating layer 202a. Also, the first
An interlayer insulating layer 204 is formed on a part of the wiring layer 203a.
A second wiring layer 205a is formed via the first wiring layer 205a, and a single chip 207a such as an integrated circuit chip 206a or a resistor or a capacitor is formed on a predetermined pattern of the second wiring layer 205a in the same manner as on the surface of the island 201a. Was arranged. That is, in the second embodiment, the integrated circuit chips are mixedly mounted on both sides of the lead frame 201.

【００１１】そして、前述した実施の形態１と同様に、
まず、第１配線層２０３と第２配線層２０５とは層間絶
縁層２０４を貫通するビア内に形成された貫通接続部２
０８を介して所定の箇所で接続し、また、集積回路チッ
プ２０６および単一チップ２０７は、ワイヤ２０９ａに
より第２配線層２０５の電極に接続し、それらで回路を
構成している。また、第１配線層２０３の電極パッド２
２３および第２配線層２０５の電極パッド２２５は、ワ
イヤ２０９ｂで所定のリード２０１ｂに接続してある。Then, similarly to the first embodiment,
First, the first wiring layer 203 and the second wiring layer 205 are connected to the through connection portion 2 formed in a via penetrating the interlayer insulating layer 204.
08, and the integrated circuit chip 206 and the single chip 207 are connected to the electrodes of the second wiring layer 205 by wires 209a, thereby forming a circuit. Also, the electrode pad 2 of the first wiring layer 203
23 and the electrode pad 225 of the second wiring layer 205 are connected to predetermined leads 201b by wires 209b.

【００１２】また、同様に、第１配線層２０３ａと第２
配線層２０５ａとは、層間絶縁層２０４ａを貫通するビ
ア内に形成された貫通接続部２０８ａを介して所定の箇
所で接続し、また、集積回路チップ２０６ａおよび単一
チップ２０７ａは、ワイヤ２０９ａにより第２配線層２
０５の電極に接続し、それらで回路を構成している。ま
た、第１配線層２０３ａの電極パッド２２３ａおよび第
２配線層２０５ａの電極パッド２２５ａと所定のリード
２０１ｂとは、ワイヤ２０９ｂで接続している。なお、
図２（ｂ）では、それらワイヤ２０９ｂの全ては図示し
ていない。Similarly, the first wiring layer 203a and the second
The wiring layer 205a is connected at a predetermined position via a through connection portion 208a formed in a via penetrating the interlayer insulating layer 204a, and the integrated circuit chip 206a and the single chip 207a are connected to each other by a wire 209a. 2 wiring layer 2
The circuit is formed by connecting to the electrodes 05. The electrode pad 223a of the first wiring layer 203a and the electrode pad 225a of the second wiring layer 205a are connected to a predetermined lead 201b by a wire 209b. In addition,
In FIG. 2B, all of the wires 209b are not shown.

【００１３】そして、この実施の形態２においても、各
集積回路チップ２０６への接地や電源電位などの固定電
位を、下部絶縁層２０２および層間絶縁層２０４を貫通
するスルーホール内に形成された貫通接続部２１０を介
し、加えてアイランド２０１ａを介して接続させるよう
にした。また、裏面に形成した各集積回路チップ２０６
ａへの固定電位の接続も、下部絶縁層２０２ａおよび層
間絶縁層２０４ａを貫通するスルーホール内に形成され
た貫通接続部２１０ａを介し、そしてアイランド２０１
ａを介すて行うようにした。すなわち、集積回路チップ
２０６の固定電位端子−第２配線層２０５の所定の電極
−貫通接続部２１０−アイランド２０１ａと接続するよ
うにした。また、同様に、集積回路チップ２０６ａの固
定電位端子−第２配線層２０５ａの所定の電極−貫通接
続部２１０ａ−アイランド２０１ａと接続するようにし
た。Also in the second embodiment, a fixed potential such as grounding or a power supply potential for each integrated circuit chip 206 is applied to the through holes formed in the lower insulating layer 202 and the interlayer insulating layer 204. The connection is made via the connection part 210 and additionally via the island 201a. Also, each integrated circuit chip 206 formed on the back surface
The fixed potential is also connected to the island 201 through the through connection portion 210a formed in a through hole penetrating the lower insulating layer 202a and the interlayer insulating layer 204a.
a. That is, the connection is made to the fixed potential terminal of the integrated circuit chip 206, the predetermined electrode of the second wiring layer 205, the through connection portion 210, and the island 201a. Similarly, a connection is made between the fixed potential terminal of the integrated circuit chip 206a, the predetermined electrode of the second wiring layer 205a, the through connection portion 210a, and the island 201a.

【００１４】なお、図示していないが、集積回路チップ
２０６やワイヤ２０９ａなどを含むリードフレーム２０
１上部を、モールド樹脂で覆い隠すようにしてもよい。
このように、回路形成部などをモールド樹脂で封止する
ことで、混成集積回路の信頼性を向上させることができ
る。以上説明したように、この実施の形態２において
も、混載する集積回路チップそれぞれの固定電位への接
続を、アイランド２０１ａを介して行うようにした。こ
のため、たとえば、第１配線層２０３や第２配線層２０
５などの配線層において、接地などの固定電位接続のた
めの配線を引き回す必要がなくなる。この結果、たとえ
ば、第１配線層２０３や第２配線層２０５、そして、第
１配線層２０３ａや第２配線層２０５ａにおいては、固
定電位接続のため以外の配線のための領域をより多くと
れるようになり、混載する集積回路チップの数をより多
くすることが可能となる。Although not shown, the lead frame 20 including the integrated circuit chip 206, the wires 209a, etc.
The upper part 1 may be covered with a mold resin.
As described above, by sealing the circuit forming portion and the like with the mold resin, the reliability of the hybrid integrated circuit can be improved. As described above, also in the second embodiment, the connection of each of the integrated circuit chips to be mounted to the fixed potential is performed via the island 201a. Therefore, for example, the first wiring layer 203 or the second wiring layer 20
In a wiring layer such as 5, there is no need to route wiring for fixed potential connection such as grounding. As a result, for example, in the first wiring layer 203 and the second wiring layer 205, and in the first wiring layer 203a and the second wiring layer 205a, more areas for wiring other than for fixed potential connection can be obtained. Therefore, the number of integrated circuit chips to be mounted can be increased.

【００１５】実施の形態３ 次に、この発明の第３の実施の形態について説明する。
図３は、この実施の形態３における混成集積回路の概略
的な構成を示す斜視図および断面図である。なお、
（ａ）は斜視図、（ｂ），（ｃ）は断面図である。この
実施の形態３の混成集積回路について説明すると、ま
ず、金属板から構成されたリードフレーム３０１のアイ
ランド３０１ａからリード３０１ｂの一部にかけて、そ
の上に下部絶縁層３０２を介して第１配線層３０３が形
成されている状態とした。また、第１配線層３０３の上
に、層間絶縁層３０４を介して第２配線層３０５が形成
されいる状態とした。また、この第２配線層３０５の所
定のパタン上に、集積回路チップ３０６や抵抗やコンデ
ンサなどの単一チップ３０７が配置されている状態とし
た。Third Embodiment Next, a third embodiment of the present invention will be described.
FIG. 3 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to the third embodiment. In addition,
(A) is a perspective view, (b), (c) is a sectional view. The hybrid integrated circuit according to the third embodiment will be described. First, from the island 301a of the lead frame 301 formed of a metal plate to a part of the lead 301b, the first wiring layer 303 is disposed thereon via the lower insulating layer 302. Was formed. Further, the second wiring layer 305 was formed on the first wiring layer 303 with the interlayer insulating layer 304 interposed therebetween. Further, the integrated circuit chip 306 and the single chip 307 such as a resistor and a capacitor are arranged on a predetermined pattern of the second wiring layer 305.

【００１６】また、第１配線層３０３と第２配線層３０
５とは層間絶縁層３０４を貫通するビア内に形成された
貫通接続部３０８を介して所定の箇所で接続し、また、
集積回路チップ３０６および単一チップ３０７は、ワイ
ヤ３０９により第２配線層３０５の電極に接続し、それ
らで回路を構成している。また、第１配線層３０３にお
いては、リード３０１ｂ上にまで延在している下部絶縁
層３０２におけるビア内に形成された貫通接続部３１０
ａにより、第１配線層３０３と所定のリード３０１ｂが
接続するようにしている。同様に、第２配線層３０５に
おいては、リード３０１ｂ上にまで延在している下部絶
縁層３０２および層間絶縁層３０４を貫通したビア内に
形成された貫通接続部３１０ｂにより、第２配線層３０
５と所定のリード３０１ｂとが接続するようにしてい
る。The first wiring layer 303 and the second wiring layer 30
5 is connected at a predetermined position via a through connection portion 308 formed in a via penetrating through the interlayer insulating layer 304;
The integrated circuit chip 306 and the single chip 307 are connected to the electrodes of the second wiring layer 305 by wires 309, and a circuit is constituted by them. In the first wiring layer 303, the through connection portion 310 formed in the via in the lower insulating layer 302 extending up to the lead 301 b
By a, the first wiring layer 303 is connected to the predetermined lead 301b. Similarly, in the second wiring layer 305, the second wiring layer 30 is formed by the through connection portion 310b formed in the via penetrating the lower insulating layer 302 and the interlayer insulating layer 304 extending to the lead 301b.
5 and a predetermined lead 301b are connected.

【００１７】そして、この実施の形態３においても、各
集積回路チップ３０６への接地などの固定電位の接続
を、下部絶縁層３０２および層間絶縁層３０４を貫通す
るスルーホール内に形成された貫通接続部３１１を介
し、そして、アイランド３０１ａを介して行うようにし
た。すなわち、集積回路チップ３０６の接地等の固定電
位端子−第２配線層３０５の所定の電極−貫通接続部３
１１−アイランド３０１ａと接続するようにした。な
お、図示していないが、集積回路チップ３０６やワイヤ
３０９などを含むリードフレーム３０１上部を、モール
ド樹脂で覆い隠すようにしてもよい。このように、回路
形成部などをモールド樹脂で封止することで、混成集積
回路の信頼性を向上させることができる。Also in the third embodiment, the connection of a fixed potential such as ground to each integrated circuit chip 306 is performed by a through connection formed in a through hole passing through the lower insulating layer 302 and the interlayer insulating layer 304. The operation is performed through the part 311 and through the island 301a. That is, the fixed potential terminal such as the ground of the integrated circuit chip 306, the predetermined electrode of the second wiring layer 305, and the through connection portion 3.
11-island 301a. Although not shown, the upper portion of the lead frame 301 including the integrated circuit chip 306 and the wires 309 may be covered with a mold resin. As described above, by sealing the circuit forming portion and the like with the mold resin, the reliability of the hybrid integrated circuit can be improved.

【００１８】このように、混載する集積回路チップそれ
ぞれへの固定電位の接続をアイランド３０１ａを介して
行うようにした。この結果、たとえば、第１配線層３０
３や第２配線層３０５などの配線層において、接地や電
源電位などの固定電位接続のための配線を引き回す必要
がなくなる。この結果、たとえば、第１配線層３０３や
第２配線層３０５においては、接地などの固定電位接続
のため以外の配線のための領域をより多くとれるように
なり、混載する集積回路チップの数をより多くすること
が可能となる。As described above, the connection of the fixed potential to each of the integrated circuit chips to be mixed is performed through the island 301a. As a result, for example, the first wiring layer 30
In a wiring layer such as the third wiring layer 305 and the second wiring layer 305, it is not necessary to lay out wiring for connection of a fixed potential such as ground or power supply potential. As a result, for example, in the first wiring layer 303 and the second wiring layer 305, a larger area for wiring other than for fixed potential connection such as grounding can be taken, and the number of integrated circuit chips to be mixed is reduced. It is possible to do more.

【００１９】なお、上記実施の形態３では、リードフレ
ーム３０１の片面に集積回路チップなどを混載するよう
にしたが、前述した実施の形態２と同様に、リードフレ
ームの両面に集積回路チップを混載するようにしてもよ
い。すなわち、図３（ｃ）に示すように、アイランド３
０１ａの裏面にも、下部絶縁層３０２ａを介して第１配
線層３０３ａを形成し、また、第１配線層３０３ａの上
にも層間絶縁層３０４ａを介して第２配線層３０５ａを
形成し、この第２配線層３０５ａの所定のパタン上に、
前述したアイランド３０１ａ表面上と同様に、集積回路
チップ３０６ａや抵抗やコンデンサなどの単一チップ３
０７ａを配置するようにしてもよい。In the third embodiment, the integrated circuit chips and the like are mixedly mounted on one side of the lead frame 301. However, similar to the second embodiment, the integrated circuit chips are mixedly mounted on both sides of the lead frame. You may make it. That is, as shown in FIG.
A first wiring layer 303a is also formed on the back surface of the first wiring layer 301a via a lower insulating layer 302a, and a second wiring layer 305a is also formed on the first wiring layer 303a via an interlayer insulating layer 304a. On a predetermined pattern of the second wiring layer 305a,
As with the surface of the island 301a, the single chip 3 such as the integrated circuit chip 306a or the resistor or the capacitor is used.
07a may be arranged.

【００２０】そして、第１配線層３０３ａと第２配線層
３０５ａとは、層間絶縁層３０４ａを貫通するビア内に
形成された貫通接続部３０８ａを介して所定の箇所で接
続し、また、集積回路チップ３０６ａおよび単一チップ
３０７ａは、ワイヤ３０９により第２配線層３０５ａの
電極に接続すればよい。また、また、第１配線層３０３
ａにおいては、リード３０１ｂ上にまで延在している下
部絶縁層３０２ａにおけるビア内に形成された貫通接続
部３２０ａにより、所定のリード３０１ｂに接続する。
そして、各集積回路チップ３０６ａへの接地などの固定
電位の接続を、下部絶縁層３０２ａおよび層間絶縁層３
０４ａを貫通するスルーホール内に形成された貫通接続
部３１１ａを介し、そして、アイランド３０１ａを介し
て行うようにすればよい。The first wiring layer 303a and the second wiring layer 305a are connected to each other at a predetermined location via a through connection portion 308a formed in a via penetrating the interlayer insulating layer 304a. The chip 306a and the single chip 307a may be connected to the electrodes of the second wiring layer 305a by wires 309. Also, the first wiring layer 303
In a, a connection is made to a predetermined lead 301b by a through connection portion 320a formed in a via in the lower insulating layer 302a extending over the lead 301b.
Then, connection of a fixed potential such as ground to each integrated circuit chip 306a is performed by the lower insulating layer 302a and the interlayer insulating layer 3a.
What is necessary is just to make it through the through-connection part 311a formed in the through-hole which penetrates 04a, and the island 301a.

【００２１】実施の形態４ 次に、この発明の第４の実施の形態について説明する。
図４は、この実施の形態４における混成集積回路の概略
的な構成を示す斜視図（ａ）および断面図（ｂ），
（ｃ）である。なお、（ｂ）は（ａ）のＡＡ’断面、
（ｃ）は（ａ）のＢＢ’断面である。この実施の形態４
の混成集積回路について説明すると、まず、金属板から
構成されたリードフレーム４０１のアイランド４０１ａ
上に、下部絶縁層４０２を介して第１配線層４０３が形
成されている。また、第１配線層４０３の上には、層間
絶縁層４０４を介して第２配線層４０５が形成され、こ
の第２配線層４０５の所定のパタン上に、集積回路チッ
プ４０６や抵抗やコンデンサなどの単一チップ４０７が
配置されている。Embodiment 4 Next, a fourth embodiment of the present invention will be described.
FIG. 4 is a perspective view (a) and a sectional view (b) showing a schematic configuration of a hybrid integrated circuit according to the fourth embodiment.
(C). (B) is an AA ′ section of (a),
(C) is a BB 'section of (a). Embodiment 4
First, an island 401a of a lead frame 401 made of a metal plate will be described.
A first wiring layer 403 is formed thereon with a lower insulating layer 402 interposed therebetween. On the first wiring layer 403, a second wiring layer 405 is formed via an interlayer insulating layer 404. On a predetermined pattern of the second wiring layer 405, an integrated circuit chip 406, a resistor, a capacitor, or the like is formed. Of single chips 407 are arranged.

【００２２】そして、第１配線層４０３と第２配線層４
０５とは、層間絶縁層４０４を貫通するビア内に形成さ
れた貫通接続部４０８を介して所定の箇所で接続してい
る。また、集積回路チップ４０６および単一チップ４０
７が、第２配線層４０５の電極に接続している。ここ
で、集積回路チップ４０６は、バンプ４０９ａにより接
続させるようにした。そして、それらで回路が構成され
ているようにした。また、この実施の形態４の混成集積
回路においては、第２配線層４０５がアイランド４０１
ａ周辺にまで延在した箇所で、下部絶縁層４０２および
層間絶縁層４０４を貫通するスルーホールに形成された
貫通接続部４０９により、端子４１０に接続させるよう
にした。この端子４１０は、アイランド４０１ａとは絶
縁膜４１０ａで絶縁分離して配置している。Then, the first wiring layer 403 and the second wiring layer 4
05 is connected at a predetermined position via a through connection portion 408 formed in a via penetrating through the interlayer insulating layer 404. Also, the integrated circuit chip 406 and the single chip 40
7 is connected to the electrode of the second wiring layer 405. Here, the integrated circuit chip 406 is connected by the bump 409a. Then, a circuit was configured with them. In the hybrid integrated circuit according to the fourth embodiment, the second wiring layer 405 is
A portion extending to the periphery of “a” is connected to the terminal 410 by a through connection portion 409 formed in a through hole penetrating the lower insulating layer 402 and the interlayer insulating layer 404. The terminal 410 is disposed so as to be insulated and separated from the island 401a by an insulating film 410a.

【００２３】そして、この実施の形態４では、各集積回
路チップ４０６への接地等の固定電位の接続を、下部絶
縁層４０２および層間絶縁層４０４を貫通するスルーホ
ール内に形成された貫通接続部４１１を介し、そしてア
イランド４０１ａを介して行うようにした。すなわち、
集積回路チップ４０６の接地などの固定電位端子−第２
配線層４０５の所定の電極−貫通接続部４１１−アイラ
ンド４０１ａと接続するようにした。このように、混載
する集積回路チップそれぞれへの固定電位への接続をア
イランド４０１ａを介して行うようにした。この結果、
たとえば、第１配線層４０３や第２配線層４０５などの
配線層において、接地や電源電位などの固定電位接続の
ための配線を引き回す必要がなくなる。この結果、たと
えば、第１配線層４０３や第２配線層４０５において
は、固定電位接続以外の配線領域をより多くとれるよう
になり、混載する集積回路チップの数をより多くするこ
とが可能となる。In the fourth embodiment, the connection of a fixed potential such as ground to each integrated circuit chip 406 is established by a through connection portion formed in a through hole passing through the lower insulating layer 402 and the interlayer insulating layer 404. 411 and through the island 401a. That is,
Fixed potential terminal such as ground of integrated circuit chip 406-second
The wiring layer 405 was connected to a predetermined electrode-through connection portion 411-island 401a. As described above, the connection to the fixed potential of each of the integrated circuit chips to be mixed is performed through the island 401a. As a result,
For example, in a wiring layer such as the first wiring layer 403 and the second wiring layer 405, it is not necessary to route wiring for connection of a fixed potential such as ground or power supply potential. As a result, for example, in the first wiring layer 403 and the second wiring layer 405, more wiring areas other than the fixed potential connection can be obtained, and the number of integrated circuit chips to be mounted can be increased. .

【００２４】また、この実施の形態４では、上述したよ
うに、リードフレーム４０１のアイランド４０１ａの領
域に、アイランド４０１ａとは絶縁分離されて配置され
た端子４１０を備えるようにした。すなわち、この実施
の形態４によれば、端子４１０に形成したボール状のバ
ンプにより、リードフレーム４０１裏面における実装が
可能となり、ＭＣＭの実装面積の縮小がはかれる。ま
た、端子４１０は、リードフレーム４０１とは全く分離
された状態で形成しているので、この実施の形態４のＭ
ＣＭを製造する過程で、リードフレーム４０１がフレー
ムより切り離されていない状態でも、テスターによるチ
ェックを行うことが可能となる。Further, in the fourth embodiment, as described above, the terminal 410 is provided in the region of the island 401a of the lead frame 401 so as to be insulated and separated from the island 401a. That is, according to the fourth embodiment, mounting on the back surface of the lead frame 401 becomes possible by the ball-shaped bumps formed on the terminals 410, and the mounting area of the MCM can be reduced. Further, since the terminal 410 is formed in a state completely separated from the lead frame 401, the M
In the process of manufacturing the CM, even if the lead frame 401 is not separated from the frame, the check can be performed by the tester.

【００２５】実施の形態５ 次に、この発明の第５の実施の形態について説明する。
図５は、この実施の形態５における混成集積回路の概略
的な構成を示す斜視図（ａ）および断面図（ｂ）であ
る。この実施の形態５においては、上述した実施の形態
４のＭＣＭ（混成集積回路）２つを、チップ配置面を向
かい合わせに配置したものである。この実施の形態５の
混成集積回路について説明すると、まず、上記実施の形
態４とほぼ同様の構成のＭＣＭ５００と、端子部分をの
ばした状態のＭＣＭ５５０とから構成されている。Embodiment 5 Next, a fifth embodiment of the present invention will be described.
FIG. 5 is a perspective view (a) and a sectional view (b) showing a schematic configuration of a hybrid integrated circuit according to the fifth embodiment. In the fifth embodiment, two MCMs (hybrid integrated circuits) of the fourth embodiment described above are arranged with the chip arrangement surfaces facing each other. The hybrid integrated circuit according to the fifth embodiment will be described. First, an MCM 500 having substantially the same configuration as that of the fourth embodiment and an MCM 550 with a terminal portion extended are provided.

【００２６】そのＭＣＭ５００は、まず、金属板から構
成されたアイランド５０１ａ上に、下部絶縁層５０２を
介して第１配線層５０３が形成されているようにした。
また、第１配線層５０３の上には、層間絶縁層５０４を
介して第２配線層５０５が形成され、この第２配線層５
０５の所定のパタン上に、集積回路チップ５０６や抵抗
やコンデンサなどの単一チップ５０７が配置されている
状態とした。そして、第１配線層５０３と第２配線層５
０５とは、層間絶縁層５０４を貫通するビア内に形成さ
れた貫通接続部５０８を介して所定の箇所で接続した。
また、集積回路チップ５０６および単一チップ５０７
は、第２配線層５０５の電極に接続した。ここで、集積
回路チップ５０６は、バンプ５０９ａにより接続するよ
うにした。そして、それらで回路が構成されているよう
にした。In the MCM 500, first, a first wiring layer 503 is formed on an island 501a made of a metal plate via a lower insulating layer 502.
A second wiring layer 505 is formed on the first wiring layer 503 with an interlayer insulating layer 504 interposed therebetween.
The integrated circuit chip 506 and the single chip 507 such as a resistor and a capacitor are arranged on the predetermined pattern 05. Then, the first wiring layer 503 and the second wiring layer 5
05 was connected at a predetermined position via a through connection portion 508 formed in a via penetrating the interlayer insulating layer 504.
Also, an integrated circuit chip 506 and a single chip 507
Was connected to the electrode of the second wiring layer 505. Here, the integrated circuit chips 506 are connected by bumps 509a. Then, a circuit was configured with them.

【００２７】また、このＭＣＭ５００は、第２配線層５
０５がアイランド５０１ａ周辺にまで延在した箇所で、
下部絶縁層５０２および層間絶縁層５０４を貫通するス
ルーホールに形成された貫通接続部５０９により、第２
配線層５０５を端子５１０に接続させている。この端子
５１０は、リードフレーム５０１のアイランド５０１ａ
面にアイランド５０１ａとは、絶縁膜５１０ａで絶縁分
離して配置している。以上のことは、前述した実施の形
態４とほぼ同様である。Further, the MCM 500 includes a second wiring layer 5
05 extends to around the island 501a,
The through connection portion 509 formed in a through hole penetrating the lower insulating layer 502 and the interlayer insulating layer 504 allows the second connection.
The wiring layer 505 is connected to the terminal 510. The terminal 510 is connected to the island 501a of the lead frame 501.
On the surface, the island 501a is insulated and separated by an insulating film 510a. The above is almost the same as the fourth embodiment.

【００２８】一方、ＭＣＭ５５０は、金属板から構成さ
れたアイランド５５１ａ上に、下部絶縁層５５２を介し
て第１配線層５５３が形成されている。また、第１配線
層５５３の上には、層間絶縁層５５４を介して第２配線
層５５５が形成され、この第２配線層５５５の所定のパ
タン上に、集積回路チップ５５６や抵抗やコンデンサな
どの単一チップ５５７が配置されている。そして、第１
配線層５５３と第２配線層５５５とは、層間絶縁層５５
４を貫通するビア内に形成された貫通接続部５５８を介
して所定の箇所で接続した。また、集積回路チップ５５
６および単一チップ５５７が、第２配線層５５５の電極
に接続している状態とした。ここで、集積回路チップ５
５６は、バンプ５５９ａにより接続している。そして、
それらで回路が構成されているようにした。On the other hand, in the MCM 550, a first wiring layer 553 is formed on an island 551a formed of a metal plate via a lower insulating layer 552. On the first wiring layer 553, a second wiring layer 555 is formed via an interlayer insulating layer 554. On a predetermined pattern of the second wiring layer 555, an integrated circuit chip 556, a resistor, a capacitor, or the like is formed. Of single chips 557 are arranged. And the first
The wiring layer 553 and the second wiring layer 555 are
4 at a predetermined location via a through connection portion 558 formed in a via penetrating through the via hole. Also, the integrated circuit chip 55
6 and the single chip 557 are connected to the electrodes of the second wiring layer 555. Here, the integrated circuit chip 5
56 are connected by bumps 559a. And
The circuit was made up of them.

【００２９】また、このＭＣＭ５５０は、第２配線層５
５５がアイランド５５１ａ周辺にまで延在した箇所で、
下部絶縁層５５２および層間絶縁層５５４を貫通するス
ルーホールに形成された貫通接続部５５９により、第２
配線層５５５を引き出し端子５６０に接続させている。
この引き出し端子５６０は、リードフレーム５５１のア
イランド５５１ａ面に、アイランド５５１ａとは絶縁膜
５６０ａで絶縁分離して配置している。Further, the MCM 550 is provided in the second wiring layer 5.
55 extends to the vicinity of the island 551a,
The through connection portion 559 formed in the through hole penetrating the lower insulating layer 552 and the interlayer insulating layer 554 makes the second
The wiring layer 555 is connected to the lead terminal 560.
The lead terminal 560 is arranged on the surface of the island 551a of the lead frame 551 so as to be insulated and separated from the island 551a by an insulating film 560a.

【００３０】そして、この実施の形態５では、集積回路
チップ５０６への固定電位の接続を、下部絶縁層５０２
および層間絶縁層５０４を貫通するスルーホール内に形
成された貫通接続部５１１を介し、そしてアイランド５
０１ａを介して行う用にした。すなわち、集積回路チッ
プ５０６の接地などの固定電位端子−第２配線層５０５
の所定の電極−貫通接続部５１１−アイランド５０１ａ
と接続するようにした。また、同様に、集積回路チップ
５５６への固定電位の接続を、下部絶縁層５５２および
層間絶縁層５５４を貫通するスルーホール内に形成され
た貫通接続部５６１を介し、そしてアイランド５５１ａ
を介して行うようにした。すなわち、集積回路チップ５
５６の接地などの固定電位端子−第２配線層５５５の所
定の電極−貫通接続部５６１−アイランド５５１ａと接
続するようにした。In the fifth embodiment, the connection of the fixed potential to the integrated circuit chip 506 is performed by the lower insulating layer 502.
Through a through connection portion 511 formed in a through hole penetrating through the interlayer insulating layer 504;
01a. That is, the fixed potential terminal such as the ground of the integrated circuit chip 506 -the second wiring layer 505
Predetermined electrode-through connection portion 511-island 501a
To be connected. Similarly, a fixed potential is connected to the integrated circuit chip 556 via a through connection portion 561 formed in a through hole penetrating the lower insulating layer 552 and the interlayer insulating layer 554, and the island 551a.
Was made to go through. That is, the integrated circuit chip 5
56, a fixed potential terminal such as ground, a predetermined electrode of the second wiring layer 555, a through connection portion 561, and an island 551a.

【００３１】このように、混載する集積回路チップそれ
ぞれからの接地等の固定電位の接続を、アイランド５０
１ａおよびアイランド５５１ａを介して行うにようにし
た。このため、たとえば、第１配線層５０３や第２配線
層５０５などの配線層において、接地等の固定電位接続
のための配線を引き回す必要がなくなる。この結果、た
とえば、第１配線層５０３や第２配線層５０５，並び
に、第１配線層５５３や第２配線層５５５においては、
固定電位接続のため以外の配線のための領域をより多く
とれるようになり、混載する集積回路チップの数をより
多くすることが可能となる。As described above, the connection of the fixed potential such as the ground from each of the integrated circuit chips to be mounted is established by the island 50.
1a and the island 551a. For this reason, for example, in the wiring layers such as the first wiring layer 503 and the second wiring layer 505, it is not necessary to route wiring for fixed potential connection such as grounding. As a result, for example, in the first wiring layer 503, the second wiring layer 505, and the first wiring layer 553 and the second wiring layer 555,
It is possible to increase the area for wiring other than for the fixed potential connection, and to increase the number of integrated circuit chips to be mounted.

【００３２】また、この実施の形態５では、上述したよ
うに、まず、リードフレーム５０１のアイランド５０１
ａ裏面に、アイランド５０１ａとは絶縁分離されて配置
された端子５１０を備えるようにした。また、リードフ
レーム５５１のアイランド５５１ａ裏面に、アイランド
５５１ａとは絶縁分離されて配置された引き出し端子５
６０を備えるようにした。また、それぞれを集積回路チ
ップ配置面を対向させて近設し、樹脂５３０でモールド
して封止するようにした。そして、引き出し端子５６０
はリードフレーム５０１の裏面にまで引き出し、引き出
し端子５６０の端部と端子５１０とが、リードフレーム
５０１裏面でそろって露出した状態とした。この結果、
この実施の形態５によれば、端子５１０および引き出し
端子５６０端部に形成したボール状のバンプにより、リ
ードフレーム５０１裏面における実装が可能となり、Ｍ
ＣＭの実装面積の縮小がはかれる。In the fifth embodiment, as described above, first, the island 501 of the lead frame 501 is provided.
The terminal 510 is provided on the back surface of the terminal a so as to be insulated and separated from the island 501a. In addition, on the back surface of the island 551a of the lead frame 551, the lead-out terminal 5 disposed insulated and separated from the island 551a is provided.
60. In addition, the respective components are arranged close to each other with the integrated circuit chip arrangement surfaces facing each other, and are molded and sealed with a resin 530. Then, the lead terminal 560
Is drawn out to the back surface of the lead frame 501 so that the end of the lead terminal 560 and the terminal 510 are uniformly exposed on the back surface of the lead frame 501. As a result,
According to the fifth embodiment, the ball-shaped bumps formed at the ends of the terminal 510 and the lead-out terminal 560 enable mounting on the back surface of the lead frame 501.
The mounting area of the CM can be reduced.

【００３３】[0033]

【発明の効果】以上説明したように、この発明では、金
属からなる基板と、この基板の表面上に絶縁層を介して
形成された配線層からなる複数の配線と、配線層上に配
置されて所定の配線と接続端子が接続された集積回路チ
ップと、基板周辺に基板と絶縁分離されて配置され所定
の配線に接続された複数の端子とを備えた混成集積回路
において、絶縁層に接続端子が接続された所定の配線か
ら基板に接続する貫通接続部を備え、この貫通接続部お
よび基板を介して接続端子が接続された所定の配線に固
定電位が接続されているようにした。また、金属からな
る基板と、この基板表面上に配線を含む配線層と絶縁層
が交互に複数積層された多層配線構造体が構成され、最
上層の配線層上に配置されて多層配線構造体の最上層の
所定の配線と接続端子が接続された集積回路チップと、
基板周辺に基板と絶縁分離されて配置されて多層配線構
造体の所定の配線に接続された複数の端子とを備えた混
成集積回路において、複数の絶縁層に接続端子が接続さ
れた所定の配線から基板に接続する貫通接続部を備え、
この貫通接続部および基板を介して接続端子が接続され
た所定の配線に固定電位が接続されているようにした。
従って、基板が固定電位の端子となるので、たとえば、
集積回路チップの配置領域のすぐ下に貫通接続部を備え
れば、配線層において固定電位のための配線を形成する
必要がなくなる。この結果、この発明によれば、配線層
の集積度を向上させることができ、結果として、ＭＣＭ
の集積度をより向上させることが可能となる。As described above, according to the present invention, a metal substrate, a plurality of wiring layers formed on a surface of the substrate via an insulating layer, and a plurality of wiring layers arranged on the wiring layer are provided. an integrated circuit chip connecting terminal connected to a predetermined wiring Te, is arranged to be substrate and the insulating isolation around the substrate a predetermined
And a plurality of terminals connected to the wirings, wherein a through connection portion is provided that connects to the substrate from a predetermined wiring having the connection terminals connected to the insulating layer. The fixed potential is connected to a predetermined wiring to which the connection terminal is connected via the substrate. Also, a substrate made of metal, and a wiring layer including wiring and an insulating layer on the surface of the substrate
Are alternately stacked to form a multilayer wiring structure.
The uppermost layer of the multilayer wiring structure is arranged on the upper wiring layer.
An integrated circuit chip to which predetermined wiring and connection terminals are connected,
A multi-layer wiring structure is placed around the board, insulated and separated from the board.
In a hybrid integrated circuit having a plurality of terminals connected to predetermined wiring of a structure, connection terminals are connected to a plurality of insulating layers.
Provided with a through connection portion connecting from the predetermined wiring to the substrate,
The connection terminal is connected via the through connection portion and the substrate.
The fixed potential is connected to the predetermined wiring .
Therefore, since the substrate becomes a fixed potential terminal, for example,
Providing the through connection portion immediately below the area where the integrated circuit chip is disposed eliminates the need to form a wiring for a fixed potential in the wiring layer. As a result, according to the present invention, the degree of integration of the wiring layer can be improved.
Can be further improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 この発明の第１の実施の形態における混成集
積回路の概略的な構成を示す斜視図および断面図であ
る。FIG. 1 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to a first embodiment of the present invention.

【図２】 この発明の第２の実施の形態における混成集
積回路の概略的な構成を示す斜視図および断面図であ
る。FIGS. 2A and 2B are a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to a second embodiment of the present invention.

【図３】 この発明の第３の実施の形態における混成集
積回路の概略的な構成を示す斜視図および断面図であ
る。FIGS. 3A and 3B are a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to a third embodiment of the present invention.

【図４】 この発明の第４の実施の形態における混成集
積回路の概略的な構成を示す斜視図および断面図であ
る。FIG. 4 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to a fourth embodiment of the present invention.

【図５】 この発明の第５の実施の形態における混成集
積回路の概略的な構成を示す斜視図および断面図であ
る。FIG. 5 is a perspective view and a sectional view showing a schematic configuration of a hybrid integrated circuit according to a fifth embodiment of the present invention.

【図６】 従来よりあるＭＣＭの構成を示す断面図であ
る。FIG. 6 is a cross-sectional view showing a configuration of a conventional MCM.

【符号の説明】[Explanation of symbols]

１０１…リードフレーム、１０１ａ…アイランド、１０
１ｂ…リード、１０２…下部絶縁層、１０３…第１配線
層、１０４…層間絶縁層、１０５…第２配線層、１０６
…集積回路チップ、１０７…単一チップ、１０８…貫通
接続部、１０９ａ，１０９ｂ…ワイヤ、１１０…貫通接
続部。101: Lead frame, 101a: Island, 10
1b Lead, 102 lower insulating layer, 103 first wiring layer, 104 interlayer insulating layer, 105 second wiring layer, 106
... Integrated circuit chip, 107 ... Single chip, 108 ... Through connection part, 109a, 109b ... Wire, 110 ... Through connection part.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/04 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 25/04

Claims (9)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 金属からなる基板と、この基板の表面上
に絶縁層を介して形成された配線層からなる複数の配線
と、前記配線層上に配置されて所定の前記配線と接続端
子が接続された集積回路チップと、前記基板周辺に前記
基板と絶縁分離されて配置され所定の前記配線に接続さ
れた複数の端子とを備えた混成集積回路において、 前記絶縁層に前記接続端子が接続された所定の配線から
前記基板に接続する貫通接続部を備え、 この貫通接続部および前記基板を介して前記接続端子が
接続された所定の配線に固定電位が接続されたことを特
徴とする混成集積回路。1. A a substrate made of a metal, a plurality of wirings <br/> consisting wiring layer formed through an insulating layer on the surface of the substrate, is disposed on the wiring layer on a predetermined of said wiring And connection end
An integrated circuit chip child has been connected, in hybrid integrated circuit comprising a plurality of terminals connected to the arranged predetermined said wiring the substrate and are insulated and isolated to the substrate around the connection terminal to the insulating layer Is provided with a through connection portion that connects to the substrate from a predetermined wiring to which the connection terminal is connected through the through connection portion and the substrate.
A hybrid integrated circuit, wherein a fixed potential is connected to a connected predetermined wiring . 【請求項２】 請求項１記載の混成集積回路において、 前記貫通接続部は、前記集積回路チップ下に配置されて
いることを特徴とする混成集積回路。2. The hybrid integrated circuit according to claim 1, wherein said feed-through portion is disposed below said integrated circuit chip. 【請求項３】 請求項１または２記載の混成集積回路に
おいて、前記配線を含む配線層と前記絶縁膜とが交互に 複数積層
されて多層配線構造体が構成され、この多層配線構造体
上に前記集積回路チップが配置されていることを特徴と
する混成集積回路。3. A hybrid integrated circuit according to claim 1 or 2, wherein the wiring layer including the wiring insulation and the membrane are alternately stacked is configured multilayer wiring structure, the multilayer wiring structure <br />. The hybrid integrated circuit, wherein the integrated circuit chip is disposed thereon. 【請求項４】 前記金属からなる基板の表面に加えて前
記基板の裏面にも請求項１乃至３のいずれか１項の構造
を有することを特徴とする混成集積回路。 4. The method according to claim 1, further comprising the step of :
The structure according to claim 1, also on the back surface of the substrate.
Hybrid integrated circuit, characterized in that it comprises a. 【請求項５】 請求項１乃至３のいずれか１項に記載の
混成集積回路において、 前 記基板２組が前記集積回路チップ搭載面で対向配置さ
れたことを特徴とする混成集積回路。5. A hybrid integrated circuit according to any one of claims 1 to 3, hybrid integrated circuits before Symbol substrate two sets, characterized in that oppositely arranged in the integrated circuit chip mounting surface. 【請求項６】 金属からなる基板と、この基板表面上に
配線を含む配線層と絶縁膜が交互に複数積層された多層
配線構造体が構成され、最上層の前記配線層上に配置さ
れて前記多層配線構造体の最上層の所定の配線と接続端
子が接続された集積回路チップと、前記基板周辺に前記
基板と絶縁分離されて配置され前記多層配線構造体の所
定の前記配線に接続された複数の端子とを備えた混成集
積回路において、 前記複数の絶縁層に前記接続端子が接続された所定の配
線から前記基板に接続する貫通接続部を備え、 この貫通接続部および前記基板を介して前記接続端子が
接続された所定の配線に固定電位が接続されたことを特
徴とする混成集積回路。6. A substrate made of a metal and a surface of the substrate
Multilayer in which multiple wiring layers including wiring and insulating films are alternately stacked
A wiring structure is configured and disposed on the uppermost wiring layer.
A predetermined wiring and a connection terminal of the uppermost layer of the multilayer wiring structure.
An integrated circuit chip child has been connected, in hybrid integrated circuit comprising a plurality of terminals connected to predetermined said wiring of said the substrate around the substrate and are arranged to be insulated and separated the multilayer interconnection structure, the A predetermined arrangement in which the connection terminals are connected to a plurality of insulating layers.
A through connection portions to be connected from the line to the substrate, said connection terminals through the through connection and the substrate
A hybrid integrated circuit, wherein a fixed potential is connected to a connected predetermined wiring . 【請求項７】 請求項１乃至６のいずれか１項に記載の
混成集積回路において、 前記端子はボンディング線を介して前記複数の配線の所
定箇所に接続されたことを特徴とする混成集積回路。7. The hybrid integrated circuit according to any one of claims 1 to 6, wherein the terminal is a hybrid integrated circuit, characterized in that it is connected to a predetermined portion of said plurality of wires through a bonding wire . 【請求項８】 請求項１乃至７のいずれか１項に記載の
混成集積回路において、 前記端子は、前記基板と離間して、前記基板に接する絶
縁層に接触して形成されたことを特徴とする混成集積回
路。8. A hybrid integrated circuit according to any one of claims 1 to 7, wherein the terminal is characterized in that apart from the said substrate, which is formed in contact with the insulating layer in contact with the substrate A hybrid integrated circuit. 【請求項９】 請求項８記載の混成集積回路において、 前記端子と前記基板とは、絶縁膜を介して離間している
ことを特徴とする混成集積回路。9. The hybrid integrated circuit according to claim 8, wherein said terminal and said substrate are separated via an insulating film.
JP27181598A 1998-09-25 1998-09-25 Hybrid integrated circuit Expired - Fee Related JP3171172B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP27181598A JP3171172B2 (en) 1998-09-25 1998-09-25 Hybrid integrated circuit
US09/401,128 US6340839B1 (en) 1998-09-25 1999-09-22 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27181598A JP3171172B2 (en) 1998-09-25 1998-09-25 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JP2000101015A JP2000101015A (en) 2000-04-07
JP3171172B2 true JP3171172B2 (en) 2001-05-28

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ID=17505241

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (2)

Country Link
US (1) US6340839B1 (en)
JP (1) JP3171172B2 (en)

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