JPH01140652A - Three-dimensional semiconductor device - Google Patents

Abstract

PURPOSE:To enable high density structure and high speed operation of a chip element, by bonding a semiconductor chip of arbitrary shape on which circuits elements are formed to a lower semiconductor chip region, and connecting circuit elements in the lower semiconductor chip region and circuit elements on the upper semiconductor chip by using electrode, via a chip side surface. CONSTITUTION:When the respective resistors R1-R3 of the respective IC chips 104-106 of a hybrid IC are made to correspond with the respective resistors R1-R3 of the respective IC chip 104-106, and each pad or the like is connected via side surface wirings 108, these become equivalent to each other. Further, by bonding the respective IC chips 104-106, and integrating them in a unified body, from technological concept viewpoint, an IC chip composed of three-layers can be formed, thereby enabling high density structure and high speed operation of a chip element.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement in a three-dimensional semiconductor device having a multilayer structure of semiconductor single crystal layers on which circuit elements are formed.

<Prior Art> In recent years, there has been a strong trend toward miniaturization, systemization, thinness, and weight reduction of electronic devices, and there is a strong demand for higher density of electronic components that constitute the devices. Hybrid ICs are a powerful electronic component for making electronic devices smaller, systematized, thinner, and lighter.

Normally, in a hybrid IC, as shown in FIG. chip 104,
105, 106 are die-bonded, wire pound 10
7 etc., one pad of each IC 104, 105, 106 is connected to the substrate wire 102.

<Problems to be solved by the invention> However, in conventional hybrid ICs, etc., passive elements 10 such as respective resistors are placed on the substrate 10Σ.
3 and active elements 10J', 104.degree. 105 such as ICs are arranged in a planar manner, so it is difficult to increase the density of the elements and there is a limit to miniaturization.

(2) The board 101 is considerably larger than the IC chips 104, 105, 106, etc., and the wiring is often printed, etc., and the line width is wide, so a large amount of material costs are required to construct the entire board 101. It is.

(3) Printing requires high-temperature processes such as a firing process, which requires a lot of electricity, heat, and power costs.

(4) Producing and configuring 102 lines on the substrate 101,
The wiring length becomes long, making it difficult to increase speed.

(5) Since there are many connection points such as wire bonds and the connection is mechanical, there are problems with reliability and the number of man-hours is large, resulting in high costs.

It had the following problems.

The present invention has been devised in view of the above points, and an object of the present invention is to provide a three-dimensional semiconductor device that eliminates the above-mentioned conventional drawbacks.

<Means to solve the problem> The above purpose? In order to achieve this, the three-dimensional semiconductor device of the present invention includes a lower layer semiconductor chip on which a circuit element is formed, an upper layer semiconductor chip on which a circuit element is formed and provided on the lower layer semiconductor chip via an adhesive layer, and the above-mentioned three-dimensional semiconductor device. The semiconductor device is configured to include a conductor layer that connects the electrodes of the upper layer semiconductor chip and the electrodes of the lower layer semiconductor chip through the side surface of the upper layer semiconductor chip.

That is, in the three-dimensional semiconductor device according to the present invention, circuit elements are separately formed in an upper layer of a lower semiconductor chip region in which circuit elements are formed. On top of that, at least one semiconductor chip is bonded, and the circuit element formed in the lower layer semiconductor chip region and the circuit element formed on the upper layer semiconductor chip are connected to the electrode layer through the side surface of the semiconductor chip. contact 1
The method is characterized in that when the father layer semiconductor chip is bonded to the lower layer semiconductor chip region, the lower layer semiconductor region is configured to be contained within the wafer.

<Function> The technical concept of the present invention is that each resistor R1 to R3 of each IC chip 104, 105° 106 of the hybrid IC shown in FIG. 12 is connected to each IC chip 104 shown in FIG.
, 105, 106, and the IC
12 and FIG. 10 become equivalent if the pads and the like are connected via the side wiring 108 of the chip. Further, the IC chips 104, 105, and 106 shown in FIG. 10 are bonded together to form an IC chip consisting of three layers shown in FIG. 11, which is integrated from a technical concept.

As a result, the hybrid IC shown in FIG. 12 and the multiplexed IC shown in FIG. 11 are equivalent.

Hereinafter, a specific method of manufacturing a multiplexed semiconductor chip according to the present invention will be explained.

The formation of circuit elements for each of the lower and upper layer semiconductor chips and, if necessary, the formation of passive elements such as multilayer wiring and resistors on each semiconductor chip are performed in the same process as that used for manufacturing ordinary two-dimensional semiconductor integrated circuits. Let's do it.

First, a groove is formed to a predetermined depth at the chip boundary from the upper side of the semiconductor wafer on which circuit elements or multilayer wiring bodies and passive elements such as resistors are formed if necessary, and the side surfaces of the groove are
After coating with an insulating film such as i02, a medical base is formed on the front side, and smoothing is performed from the back side with trenches of a predetermined thickness, and each chip is separated by a groove. After that, cut the protective substrate and press
Divide into each chip.

Next, the M layer is attached to the surface side of the lower layer semiconductor chip region included in the wafer on which circuit elements or, if necessary, passive elements such as multilayer wiring bodies and resistors are formed, or to one or both sides of the upper layer semiconductor chip. is formed, and the upper layer semiconductor chip is attracted to a predetermined position in the lower layer semiconductor chip area under predetermined conditions such as pressure and temperature.

After removing the protective base layer that is no longer needed, the upper and lower semiconductor chips are completely removed through the side surface of the upper semiconductor chip using a thin film technique such as evaporation, photoetching, plating, selective etching, etc. Connect using a predetermined electrode pattern. After that, after applying a prescribed treatment as necessary to the upper layer semiconductor chip, it is used as a lower layer semiconductor region, and circuit elements are further incorporated in the upper layer, and the above process is repeated for the ``twisted'' upper layer semiconductor chip! A three-dimensional semiconductor device having 73 or more layers can be manufactured.

<Embodiment> Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

EMBODIMENT OF THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

First, Figure 1 shows the state of the -th layer semiconductor wafer.
MOSFETs and bipolar elements are incorporated into the single crystal silicon 1 by a known method of forming a normal two-dimensional semiconductor integrated circuit, and then an insulating film 2 is coated thereon, and a third layer wiring body 3 in a predetermined pattern is formed. and then an insulating film 4 is formed thereon.
, a predetermined pattern of a thin film resistor 5, an insulating film 6, a second layer wiring body 7, and a surface protection insulating film 8 are formed, and the chip boundary portion 9 is entirely formed.

More specifically, first of all, what is the known ion implantation technology, thermal diffusion technology, etc. for single crystal silicon 1? MOS FETs and bipolar elements are incorporated using the usual manufacturing method of the two-dimensional integrated circuit used. The insulating film 2 is made of SiO□, SiN, or the like, and is formed by thermal oxidation or the like when the device is assembled, or by low-temperature vapor phase growth, plasma CVD, or the like if necessary. The wiring body 3 is made of Al.

Mo+W, WSi2. The insulating film 2 is made of a conductive film such as T i S i2, and after opening a window in the insulating film 2 by photo-etching or selective etching as necessary, a conductive film is formed on the entire surface of the wafer by low-pressure CVD, electron beam evaporation, puttering, etc. After forming, a predetermined pattern is produced using photoetching technology and selective etching technology.

The insulating film 4 on the wiring body 3 is made of Sioz, SiN, etc., and is formed by low-temperature vapor deposition, low-pressure CVD, or the like.

The thin film resistor 5 is made of NiCr, Cr5iO, etc., and is coated on the entire surface of the wafer with a desired thickness by sputtering, electron beam evaporation, etc. at a predetermined base temperature on the insulating film 4, and then subjected to photoetching, selective etching, etc. to form a predetermined pattern.

Thereafter, stabilization treatment is performed at a predetermined temperature and time as necessary.

6 is a protective film for the resistor 5 and an insulating film for the multilayer wiring body, and is made of SiOZ, SiN, etc., and is formed by low-temperature vapor deposition, low-pressure CVD, etc. do. Thereafter, the insulating film 4.6 on the wiring body 3 and the insulating film 6 on the resistor 5 are removed in a predetermined pattern by photoetching, technology, selective etching technology, etc., and after opening a window, the insulation film 4.6 on the wiring body 3 is removed. 5i02. Si
An insulating film 8'f made of N or the like is formed. Thereafter, the portions of the wiring body 3 corresponding to the pad portions and the insulating film 4°6.8 on the chip boundary portion 9 are successively removed by photoetching, selective etching, etc., to prepare the first layer of the wood embodiment.

FIG. 2 shows a wafer for a second-layer chip, and assumes that a normal two-dimensional semiconductor integrated circuit is formed on the single-crystal silicon 10 in the same way as the first-layer evaporator (with MOSFETs and bipolar elements incorporated therein). is coated with an insulating film 11, a predetermined pattern of wiring bodies 12 is entirely formed thereon, a protective insulating film 13 is formed thereon, and a groove 14 at the chip boundary is formed.
, and further covers the upper part of the groove 14, etc. Insulation 11 1
5.

The insulating films 11 and 13 are made of Sioz, SiN2, etc., and the wiring body 12 is made of A6, Mo, W, WS i2.

The insulating films 2, 4, 6, etc. in FIG. It is produced in the same manner as in the case of forming the gate line body 3.7. The groove 14 is made to a predetermined depth by mechanical processing such as dicing or isodirectional etching using il''l:HF, HNO3, and the depth is about 0 to 200 μm. The insulating film 15 covers the side surfaces of the groove 14, and is made of 5iOz, SiN.
It is made in the same manner as the insulating film 13 and the like.

Thereafter, as shown in FIG. 3, the single crystal silicon 10 is bonded to a holding base 17 made of glass or the like with wax 16, and %H is applied from the back side by mechanical methods such as lapping and polishing.

N a Kame H+ A predetermined 1 part in which each chip is separated by a groove 14 by a chemical method using an etchant such as fluoro-nitric acid.
! Smooth finish on the female.

Next, the holding substrate 17 is cut at a position corresponding to the groove 14 by dicing or the like, and after separating into each chip, the good chip area A of the first layer single crystal silicon 1 is separated into good quality chips as shown in FIG. An adhesive layer 18 is formed at a predetermined position using epoxy, acrylic, polyimide, etc. under conditions such as predetermined temperature and pressure, and the adhesive layer 18 is bonded. At this time, single crystal silicon 1
There is no need to bond a good chip to the 8 parts of the defective chip area. Thereafter, the wax 16 and the holding substrate 17 are removed by a predetermined method, and the adhesive layer 18 is re-hardened under predetermined conditions if necessary, and then the insulating films 13 and 15 are formed by photoetching, selective etching, etc., if necessary. After opening windows in a predetermined pattern, T1Ni film, CrCu film, AlN film are continuously formed under predetermined conditions by electron beam evaporation, resistance heating evaporation, etc.
After forming a multiple metal film 19 such as an i-film on the entire surface of the wafer, selective Au plating is performed in a predetermined pattern using photoetching technology to form an Au plating film 20, and this film 20 is used as a mask to remove unnecessary multilayer metal films. The heavy metal layer film 19 is removed by etching or the like to obtain a form as shown in FIG. At this time, there is a step on the wafer due to the single crystal silicon 10, etc., but because it is thin, photoetching technology, vapor deposition technology 9, selective plating technology, etc. can be applied without difficulty.

FIG. 6 is a completed cross-sectional view of this embodiment, and FIG. 7 is a completed (preliminary) view. The figure shows the state in which two chips of single crystal silicon with integrated elements 4 are glued together, and then the chip border 90 is diced and separated into each chip.One chip is made of single crystal silicon 21
．． 5i02° Insulating film 22 made of SiN or the like. ACMo,
W.

WS i2. A 12-wire body 23 made of a conductor such as T iS i2, a protective insulating film 24 made of SiO2, SiN, etc.
, an insulating film 25 made of Si02, SiN, etc., covers the side surfaces of the chip, and is bonded with an adhesive layer 26 made of resin such as epoxy, acrylic, polyimide, etc., and then a layer of TiN, Cr, Cu, etc. is placed at a predetermined position. A multilayer metal film 27 and an Au metal layer 28 form a pad or wiring on the chip.

The other chip includes a single crystal silicon 29 incorporating elements, an insulating film 30 . Insulating film 31. 4) 4 is formed by insulating film 321 etc., and adhesive m3
3. After gluing by 3, multiple metals 1 and 34. This shows a state in which wiring made of Au plating 35 is formed.

In this case as well, monocrystalline silicon 21.
It can be constructed by bonding single crystal silicon 29.

In this example, a three-dimensional semiconductor device desired by the present invention was obtained.

When fabricating with the device of this embodiment, good chips were sequentially bonded to the good parts on the first layer of single crystal 1, and a large number of chips could be handled like a wafer patch process, so it was possible to fabricate efficiently. .

In addition, in this example, the wiring on the chip after bonding the chip was fabricated by vapor deposition and Au electrolytic plating, but the fabrication method is not limited to this. It is obvious that various methods such as , printing, etc. can be used, and materials etc. can also be modified in various ways.

In this example, we have described the case where the resistor, which is a passive element, is formed only on the 1st and A-th silicon, but it is also clear that it is possible to form a passive element such as a resistor on a chip of any layer. .

Example (2) In Example (2), the case where the end face of the single crystal silicon chip to be pasted was vertical was described.

In this example ■, silicon (100) is used as the crystal to be pasted.
A case will be described in which the end face of the chip has an oblique shape, there is no disconnection in the electrode metal film connecting the chips, and it can be easily manufactured.

FIG. 8 shows a completed schematic diagram of this embodiment, mainly consisting of a first layer single crystal silicon 36, a chip-shaped second layer single crystal silicon 37 bonded thereon, and a fJ is composed of the third layer single crystal silicon 38, single crystal silicon 39, electrode pad 40, and the chip m41 mentioned above that connects them.

In the case of Example I, as shown in FIG. 1, a concave groove 14 was formed by dicing, etc., and each chip was separated by smoothing the back surface, but in non-Example, a mask made of a predetermined metal film, etc. was fully utilized. After that, anisotropic etching was performed twice using NaOH5 or KOH to completely form a V-shaped groove, and each chip was separated by smoothing the back surface. The sides of the silicon 38,39 chip could be sloped.

Except for the above steps, the procedure was the same as in Example ■.
A three-dimensional semiconductor device as shown in FIG. 8 can be formed.

In this example, since the side surface of the chip to be pasted is sloped, steps such as photo-etching can be easily carried out, and there is no disconnection of the wiring 41, resulting in an improvement in yield.

Example ■ In Examples ■ and ■, the case where the upper chip to be pasted is smaller than the lower chip was described.

In this embodiment, a case will be described in which the upper and lower chips to be pasted have the same size and shape, or the end faces are the same.

FIG. 9 shows a part of a completed schematic diagram of this embodiment, showing a chip-shaped first layer single crystal silicon 42 incorporating an element, and pad portions 43, 431 on the single crystal silicon 42.
, a chip-shaped second layer (100) single crystal silicon 44 incorporating an element, holes 45, 451, top portions 46, 461 of the single crystal silicon 44, and pad portions 46, 46.
Wiring body 47° 4 connecting 1 and pad portions 43, 431
71, a third layer (100) single crystal silicon 48 incorporating an element, a hole 49, a pad portion 50, a wiring body 51 connecting the pad portion 50 and the pad portion 46, and the like.

In the case of Example 2, as shown in FIG. 2, a concave groove 14 was formed by dicing, etc., and each chip was separated by back surface smoothing.
The holes 45 and 451 of No. 4 were formed using a metal mask with a predetermined pattern before forming grooves corresponding to the concave grooves 14 of Example I.
7 V by anisotropic etching with KOH and NaOH
After forming the 45° 451-shaped hole, the groove 14 in Fig. 2 is formed.
A groove corresponding to the size is formed, and each chip is separated by smoothing from the back side.

Further, the side surface of the third layer single crystal silicon 48 has a sloped shape, but as explained in Example 2, the portion corresponding to the groove 14 in FIG. 2 of Example I is formed in a predetermined pattern. K.O.
V-shaped grooves created by anisotropic etching with H or NaOH? Then, each chip is separated by smoothing from the back side.

This waiter 49 is formed at the same time as a predetermined pattern is formed when forming the V-shaped groove.

The steps other than the above are the same as those of Example I, and by sequentially passing through all the steps, a desired three-dimensional semiconductor device @ as shown in FIG. 9 in Example M can be obtained.

In FIG. 9 of this embodiment, the holes 45, 451 and 49 all had sloped side walls formed by anisotropic etching with alkali, but holes with vertical walls were formed using an etching solution such as hydrofluoric nitric acid. There's nothing wrong with saying that.

In Examples r, n, and m, a triple LSI was used, but it is clear that the number of stages of chips to be pasted, as well as the number and shape of chips to be pasted, can be arbitrarily determined.

In addition, the side wall of the chip that forms the wiring that connects and reads the upper layer chip and the lower layer chip has a vertical shape in Example 2 and an inclined shape in Examples 2 and 2, but it can have a vertical and slanted shape as necessary. It is clear that it can be made using

Further, in Examples r, n, and m, the case where only silicon was used as the material was described, but the present invention is not limited to this, and it is also possible to use 111V group semiconductors such as GaAs. Needless to say.

<Effects of the Invention> As described above, in the three-dimensional semiconductor device according to the present invention, a semiconductor chip of an arbitrary shape on which a circuit element is formed is bonded to a lower semiconductor chip region, and the side surface of the chip is bonded to a semiconductor chip of an arbitrary shape on which a circuit element is formed. Since it is a fat structure in which the circuit elements of the lower layer semiconductor chip and the circuit elements of the upper layer semiconductor chip are connected by electrodes, it is equivalent to a hybrid IC, etc., in which semiconductor chips, etc. are arranged on a two-dimensional substrate, etc. It can be done. Furthermore, it is possible to achieve a higher density of chip elements than ever before, making it possible to achieve high speeds.

In addition, unlike hybrid ICs, there is no need for large substrates and substrate wiring on the substrate, resulting in a significant reduction in material costs, and because chip bonding and other processes can be performed at low temperatures, there is no adverse effect on the chip's element characteristics VC. Moreover, it is possible to reduce power and heating costs during its production.

Furthermore, since the number of mechanical connection points such as wire pounds is reduced, good reliability can be obtained. Furthermore, multiple chips can be mounted on the same chip, which simplifies the design and increases the density of chip elements. It can be further promoted.

In addition, this three-dimensional semiconductor device can be fabricated by sequentially attaching chips from the second layer to the non-defective chip portion of the wafer containing the -i-th chip, so it is possible to fabricate a large number of chips at once. Wafers can be processed in batches, reducing labor costs.

[Brief explanation of the drawing]

1 to 5 are longitudinal cross-sectional partial front views showing the manufacturing process of a device according to an embodiment of the present invention, FIG. 6 is a vertical cross-sectional partial front view of a device according to an embodiment of the invention, and FIG. A diagram showing a completed concept of a device according to one embodiment of the present invention, FIG. 8 is a diagram showing a completed concept of another embodiment device of the present invention, and FIG. 9 is a diagram showing a completed concept of a device according to still another embodiment of the present invention. FIG. 10 and FIG. 11 are diagrams for explaining the present invention, and FIG. 12 is a diagram showing an example of the configuration of a conventional device. 1.10.21.29...Single crystal silicon, 18.2
6.33... Adhesive layer, 5... Thin film resistor, 2.4
．． 6.8.11.13, 15.22, 24°25.30
, 31.32... Insulating film, 3.7°12.23...
・Wiring body, 19,27.34...Multiple metal film.

Claims (1)

[Claims] 1. A lower semiconductor chip on which a circuit element is formed, an upper semiconductor chip on which a circuit element is formed and provided on the lower semiconductor chip via an adhesive layer, and an electrode of the upper semiconductor chip. A three-dimensional semiconductor device comprising: and a conductor layer that connects an electrode of a lower semiconductor chip through a side surface of the upper semiconductor chip.