JPH08125120A - Semiconductor device and production thereof - Google Patents

Abstract

PURPOSE: To obtain a highly reliable three-dimensional LSI having extremely high integration density and production method thereof. CONSTITUTION: First and second LSIs arranged vertically are interconnected through planar surface and rear connection surface terminals 1, 11. In order to planarize the connection surfaces of the surface and rear connection surface terminals 1, 11, a wafer having silicon on insulator structure is employed. Since a bump projecting from the surface is not required, concentration of stress at the joint is relaxed and thermal resistance thereat is reduced, resulting in a three-dimensional LSI having extremely high reliability at the joint.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device suitable for realizing a three-dimensional LSI having an extremely high integration density and high reliability, and the semiconductor device. The present invention relates to a method for manufacturing a semiconductor device, which can easily form a semiconductor device with high accuracy.

[0002]

2. Description of the Related Art The structure of a conventional three-dimensional LSI is Japanese Patent Publication No.
-47980. That is, in the above-mentioned conventional three-dimensional LSI, as shown in FIG. 2, the inter-element insulating film 8 is formed on the silicon substrate 12 via the insulating film 6, and the opening provided in the inter-element insulating film 8 is formed. A first transistor having a single crystal semiconductor film 15 on which a gate oxide film 6, a gate 7 and a source / drain 10 are formed is formed in the portion, and a first LSI including the first transistor is formed. Has been done.

Similarly, above the first LSI, a gate oxide film 6, a gate 7 and a source / drain 10 are formed in the opening of the inter-element insulating film 8 formed on the insulating film 9. A second transistor having the single crystal semiconductor film 15 is formed, and a second LSI including this second transistor is configured. A wiring 3 is connected to the source / drain 10 of each of the first and second transistors, and a surface insulating film 5 covering the wiring 3 is further provided.
Are formed.

The surface through hole 2 is formed in the surface insulating film 5.
Is formed, the conventional pad 13 is connected to the upper surface of the wiring 3 connected to the first transistor through the terminal 3 ′ formed in the surface through hole 2, and
Connection pins 14 are formed on the upper surface of the conventional pad 13.

The connection pin 14 is connected to the back surface of the wiring 3 connected to the second transistor, and thus the first and second transistors are connected to the conventional pad 13 and the connection pin 14. Connected to each other via.

[0006]

In the above conventional structure,
The connection pins 14 are high bumps that vertically project upward from the surface of the first LSI formed below.
If such high bumps are present, a large gap is generated between the adjacent connection pins 14 as shown in FIG.

However, since the second LSI is a thin film LSI and the thin film LSI is formed by thinning various materials having different thermal expansion coefficients through a process of 1,000 ° C. or more, The presence of such a large void tends to cause strain due to thermal expansion in various places, and also causes the connection pin 14, the pad 13, and the terminal 3 '.
Since the connection area between the two is small, local stress is generated in the heat cycle after the connection is made and cracks are likely to occur. Further, since the contact area is small, the contact resistance is large and the operation is likely to be unstable, and the existence of the voids increases the thermal resistance and the temperature rises, which makes it difficult to achieve high integration. was there.

An object of the present invention is to solve the above-mentioned conventional problems, to manufacture a three-dimensional LSI having extremely high integration density and high reliability, and a semiconductor device capable of easily forming the three-dimensional LSI. Is to provide a method.

[0009]

In order to achieve the above object, the present invention provides a plurality of planar surface connection surface terminals on the upper surface of the first LSI and on the back surface of the second LSI, respectively. The back surface connection surface terminals are provided and are connected to face each other, and the front surface connection surface terminal and the back surface connection surface terminal are electrically connected to the wirings of the first and second transistors, respectively.

On the front surface of the first LSI and the back surface of the second LSI, the front surface connection surface terminals and the rear surface connection surface terminals which are adjacent to each other are separated from each other by a thin groove-like void, and are separated from each other. Each of the front surface connection surface terminals is electrically connected to each of the rear surface connection surface terminals arranged above and facing each other.

The front surface connection surface terminal is electrically connected to the upper surface of the wiring of the first transistor, while the back surface connection surface terminal is electrically connected to the back surface of the wiring of the second transistor. It As a result, the first and second
The LSI is electrically connected appropriately through the front surface connection surface terminal and the rear surface connection surface terminal.

[0012]

In the conventional semiconductor device shown in FIG. 2, the planar front surface connecting surface terminal and back surface connecting surface terminal are connected to face each other. The projecting connection pin 14 is no longer required, and the large gap that existed between adjacent connection pins 14 does not exist. Therefore, even though the thin film LSI is formed into a thin film by using various materials having different thermal expansion coefficients through the process of 1,000 ° C. or higher, the strain due to the thermal expansion hardly occurs.

Further, since the planar front surface and back surface connection surface terminals are used for connecting the first and second transistors, the connection area is sufficiently large. Therefore, in the thermal cycle after the connection is formed, not only is it difficult for cracks to occur due to the occurrence of local stress, but also the contact resistance is small and the contact resistance is not unstable. Furthermore, since there is no space between the connecting pins, the thermal resistance is small and the temperature rise is small, so that an ultra-high density memory with extremely high integration density can be realized.

[0014]

【Example】

<Embodiment 1> FIG. 1 is a sectional view showing an embodiment in which two layers of LSIs are laminated. The surface connection surface terminal 1 made of a gold (Au) film formed on the upper surface of the first transistor arranged below is connected to the surface connection surface terminal 1 of the second transistor arranged above.
It is connected to the back surface connection surface terminal 11 made of a gold film formed on the back surface. Since the front surface connection surface terminal 1 and the rear surface connection surface terminal 11 are both flat, the connection between them is a surface connection, and the contact area is extremely large.

Since the insulating film 9 and the single crystal silicon film 15 constitute a silicon-on-insulator structure, the back surface of the insulating film 9 is extremely flat. Since the back surface connection terminal 11 is formed on the back surface of such an extremely flat insulating film 9 and further subjected to chemical mechanical polishing, the surface thereof becomes extremely flat, and the back surface connection terminal 1 and Good surface connection can be easily realized.

The first and second transistors were obtained by forming the gate 7, the gate oxide film 6 and the like using a normal semiconductor process. The respective transistors are insulated and separated from each other by the insulating film 9 and the inter-element insulating film 8, and the source and drain 10 formed at both ends of the single crystal silicon film 15 of each transistor have wiring lines 3 as shown in FIG. Are connected respectively.

The wirings 3 of the first and second LSIs are connected to the surface connection surface terminals 1 through a conductive film filled in the surface through holes 2 formed in the surface insulating film 5 and arranged on the upper side. The wiring 3 of the formed second LSI is further connected to the back surface connection surface terminal 11 via a conductive film filling the back surface through hole 4.

In the first LSI arranged in the lower part, the silicon substrate 12 remains, but in the second LSI arranged in the upper part, the silicon substrate is removed to form a thin film LSI. In addition, as described above, the silicon-on by the insulating film 9 and the semiconductor film 15 of the second LSI.
The insulator structure is formed, and the back surface connecting surface terminal 1 is formed.
Since No. 1 is formed on the insulating film 9 forming the above silicon-on-insulator structure, the surface is extremely flat.

Next, the shapes of the front surface connecting surface terminal 1 and the rear surface connecting surface terminal 11 will be described. The front surface connecting surface terminal 1 and the rear surface connecting surface terminal 11 are the second L arranged above.
It is a terminal for electrically connecting the SI and the first LSI arranged below. Conventional connection terminals are formed and used only on the front surface (upper surface) of the LSI, but in the present invention, 3
Formed on the back surface and the top surface of the second and first LSIs stacked one above the other in the three-dimensional LSI,
It is used to connect these first and second LSIs to each other.

Conventionally, when the surface of a bump is joined to a projecting terminal because the surface is not sufficiently flattened, the tip of the bump can be deformed to uniformly connect a plurality of terminals. I've been told. However, since the present invention realizes an extremely flat surface, it is possible to carry out uniform surface bonding in a wide area. This is the same as the fact that two mirror-finished surfaces can be evenly bonded together when forming a bonded wafer. The shape and dimensions of this connecting surface terminal can be appropriately selected according to the position and density of the output terminal of the LSI.
Also, by arranging the back surface connection surface terminals 11 as close as possible and reducing the gap between the adjacent connection surface terminals, highly reliable connection becomes possible.

Next, the manufacturing process of this embodiment will be described with reference to FIGS. First, as shown in FIG. 3A, an insulating film 9 made of a silicon oxide film and a single crystal silicon film 15 were laminated on a single crystal silicon substrate 12 to form a silicon-on-insulator wafer structure. . The single crystal silicon film 15 was formed by laminating a separately prepared single crystal silicon substrate on the insulating film 9 and then etching the single crystal silicon substrate to reduce its thickness. At this time, only chemical etching may be performed, but etching may be performed after mechanical grinding. The insulating film 9 is a film that insulates the transistor and also acts as an etching stopper when the LSI is thinned in a later step.

Next, as shown in FIG. 3B, the silicon film 15 is processed into a predetermined shape by using a known photo-etching, and then the source / drain 10 is formed by using a known ion implantation method. Then, a silicon oxide film was formed on the entire surface by using a well-known CVD method, unnecessary portions were removed, and an inter-element insulating film 8 exposing the silicon film 15 through the opening was formed.

The gate oxide film 6, the gate 7 and the source and drain 10 are formed by the usual manufacturing method to form the first transistor, and then the wirings connected to the source and drain 10 of the first transistor, respectively. 3 was formed, and a surface insulating film 5 for insulating the surface was further formed on the entire surface.

At this stage, as shown in FIG. 3B, the surface of the surface insulating film 5 is not flat due to the influence of the step of the wiring 3. Therefore, even if the connection connection surface terminal 1 is formed on the surface insulating film 5 in this state, a step remains and unevenness on the surface prevents uniform connection over the entire surface, resulting in incomplete connection. A large number of parts are generated and the yield is significantly reduced.

In such a state, it is impossible to realize a three-dimensional LSI. Therefore, as shown in FIG. 3C, the surface insulating film 5 is chemically mechanically polished to flatten the surface. In this chemical mechanical polishing, the surface of the surface insulating film 5 is first chemically treated to soften the surface and then mechanically polished to planarize the surface. I was able to

As shown in FIG. 3D, after the surface through hole 2 is formed on the surface insulating film 5 whose surface is flattened by a known selective etching method, the surface through hole 2 is formed. After filling, a gold film extending on the surface of the surface insulating film 8 was formed, and unnecessary portions were removed to form the surface connection surface terminal 1.

Next, using a second silicon substrate (not shown, which corresponds to the silicon substrate 12 in FIGS. 3A to 3D) separately prepared, the above-described FIGS. 3A to 3D are used.
3D to form the same structure as shown in FIG. 3D, and then, as shown in FIG. 4A, the second silicon substrate was removed by a well-known wet etching. . At this time, since the etching rate of silicon dioxide forming the insulating film 9 is significantly lower than the etching rate of silicon, the insulating film 9 acts as an etching stopper and does not adversely affect the first transistor, and is extremely high. It was possible to remove the second silicon substrate with high accuracy and perform thinning.

Polishing may be used instead of the above etching for removing the second silicon substrate. Also in this case, since the polishing speeds of silicon dioxide and silicon are remarkably different from each other, the insulating film 9 acts as a stopper for polishing, and the second silicon substrate can be protected without adversely affecting the first transistor. It could be removed with high accuracy.

When polishing is used for surface flattening or removal of a silicon substrate, a damage layer due to polishing may occur up to a depth of about 50 microns, and in the past, the throughput was greatly reduced and the cost was increased. Was causing However, according to the present invention, since the insulating film 9 is interposed between the second silicon substrate and the transistor, there is no fear that the above-mentioned damaged layer will adversely affect, and it is extremely easy to form a uniform thin film. I was able to.

Next, as shown in FIG. 4B, predetermined portions of the insulating film 9 and the inter-element insulating film 8 are etched,
After forming the through hole 17 reaching the back side of the wiring 3,
As shown in FIG. 4C, after depositing gold on the entire surface, unnecessary portions are removed, the through holes 17 are filled, and the back surface connection surface terminals 18 extending on the back surface of the insulating film 9 are formed. Was formed.

As shown in FIG. 4D, after the front surface connection surface terminal 1 and the back surface connection surface terminal 18 are opposed to each other and aligned, the front surface connection surface terminal 1 and the back surface connection surface terminal 18 are aligned. The surface of was cleaned by sputtering using argon (Ar) ions or the like, and the facing surfaces of the front surface connecting surface terminal 1 and the rear surface connecting surface terminal 18 were closely contacted and connected. The front surface connecting surface terminal 1 and the rear surface connecting surface terminal 18 are formed by sputtering the argon ions or the like.
Becomes an extremely clean activation surface, and since the surfaces of the two connecting surface terminals 1 and 13 are extremely flat, when the two are brought close to and brought into close contact with each other, the atoms of both diffuse into each other and form a boundary. Became indistinct and became bulky, and both were strongly connected to each other by such solid phase diffusion. Moreover, since it is not necessary to apply high temperature or high pressure at the time of connection, there is no fear of residual stress due to heat or pressure, and extremely strong and highly reliable connection was realized.

According to the present invention, a highly reliable three-dimensional LS
In order to form I, the first thin film LSI and the second thin film L
Each SI has a planar connecting surface terminal, and each connecting surface terminal is electrically separated from each other by being divided into a plurality of regions by a thin groove-shaped void portion. These thin groove-shaped voids are formed by connecting surface terminals for electrically connecting the first and second thin film LSIs arranged above and below and the first and second thin film LSIs arranged above and below. It is formed so as to surround each of the connection surface terminals that are not electrically connected. Since these narrow groove-shaped voids have a width larger than the alignment accuracy of the first and second thin film LSIs arranged above and below, the above-mentioned regions of the connection surface terminals which are separated from each other are short-circuited to each other. There is no fear of it. Moreover, since the width of the void is smaller than the width of the regions separated from each other, the connection surface terminals can be arranged in a spread pattern, and the bonding surface can be flattened over a wide range. Highly reliable and low cost connection is now possible.

Further, as described above, the second LSI is thinned by using the wafer having the silicon-on-insulator structure, and further, the silicon substrate is removed by the chemical mechanical polishing method. The surface of the insulating film 9 is extremely flat, and the surface of the back surface connection surface terminal 18 formed thereon is also extremely flat, and a stable thin film LSI can be formed. In addition, since the surfaces of the planar connection surface terminals are activated by sputtering with argon ions or the like prior to connecting them to each other, solid-phase diffusion bonding is easily performed and highly reliable bonding is achieved. Was realized. Further, as another connection method, by interposing an anisotropic adhesive between the front surface connection surface terminal 1 and the rear surface connection surface terminal 18 which face each other, conduction in the vertical direction and insulation in the horizontal direction are possible at the same time. It is possible to form a connection suitable for a three-dimensional LSI.

<Embodiment 2> The above-mentioned first LSI and second L
As described above, the plurality of planar connection surface terminals of the SI are separated from each other by the thin groove-shaped void portions, and are electrically independent. A memory LSI in which a plurality of LSIs are stacked via such a planar connection surface terminal
The semiconductor device formed by connecting the above to a semiconductor chip having a larger plane area has a very wide range of applications and is extremely useful for expanding various industries.

For example, as shown in FIG. 5, a plurality of thin film LSIs 19 are stacked via connection surface terminals 20 to form a three-dimensional L.
SI21 was formed (FIG. 5 shows the case where eight layers of thin film LSIs are stacked). As the thin film LSI, various LSIs such as a memory, a logic or an analog can be used, and a passive component such as a coil, a resistor or a capacitance may be used. L like this
Since it is sufficiently possible that the thickness of one layer of SI and components is about 10 μm, for example, even if 100 layers of LSIs and components are stacked to form a three-dimensional LSI, the thickness is only 1 This is only about a millimeter, which is a value that cannot be realized by the conventional semiconductor device, and various functional modules can be realized in an extremely compact manner by being fused and connected to other chips. For example, FIG.
As shown in FIG.
It is placed on I22, and a large number of terminals (not shown) connect between the two. The large chip LSI 22 has a microprocessor 23, and the whole is mounted on a substrate 24. Since a module much smaller than the conventional one was realized, it was possible to replace the current tape-shaped cassette memory with a solid-state memory, and an extremely compact camera could be realized. It can be used for various purposes. Also,
A large-scale computer system having a large-capacity cache memory and a main memory and requiring a magnetic disk as a two-dimensional memory can be replaced by the three-dimensional LSI according to the present invention to reduce power consumption efficiency and wiring delay. Power and performance are greatly improved, including drastic improvement in time, which is extremely useful for saving energy in the system. In the above embodiment, the gold film is used as the connection surface terminal, but the invention is not limited to gold, and various metals other than gold can be used. In addition, various materials that have been conventionally used can be used for the conductive film filling the back surface through hole and the wiring connected to the source / drain.

[0036]

As is apparent from the above description, according to the present invention, the bumps, which have been indispensable in the past, are no longer required, and the large gaps between the connection pins 14, which always existed in the past, do not exist. Therefore, when forming a thin film LSI, 1,0
Even if a thin film is formed through a process at a temperature of 00 ° C. or higher, distortion due to thermal expansion does not occur. Furthermore, since the connection area is sufficiently large, cracks due to the occurrence of local stress due to the thermal cycle after connection formation are less likely to occur, and the contact area is large so that the contact resistance is small and the resistance value does not become unstable. It has many features such as low thermal resistance, which is suitable for improving integration density, and is extremely useful for realizing ultra high density memory.

[Brief description of drawings]

FIG. 1 is a sectional view and a plan view showing an embodiment of the present invention,

FIG. 2 is a cross-sectional view showing the structure of a conventional semiconductor device,

FIG. 3 is a process chart showing an embodiment of the present invention,

FIG. 4 is a process chart showing an embodiment of the present invention,

FIG. 5 is a sectional view showing a second embodiment of the present invention,

FIG. 6 is a diagram showing a second embodiment of the present invention.

[Explanation of symbols]

1 ... Surface connection surface terminal, 2 ... Surface through hole, 3 ...
Wiring, 4 ... Back surface through hole, 5 ... Surface insulating film, 6
... gate oxide film, 7 ... gate, 8 ... inter-element insulating film,
Reference numeral 9 ... Insulating film, 10 ... Source / drain, 11 ... Back surface connecting surface terminal, 12 ... Silicon substrate, 13 ... Conventional connection surface terminal, 14 ... Connection pin, 15 ... Single crystal silicon film, 1
7-back surface through hole, 18-back surface connecting surface terminal, 19
... Thin film LSI, 20 ... Connection surface terminal, 21 ... Three-dimensional LS
I, 22 ... Large chip LSI, 23 ... Microprocessor, 24 ... Substrate, 25 ... Groove-shaped void portion.

Claims (13)

[Claims] 1. A flat surface connection surface terminal formed on an upper surface of a first integrated circuit, comprising a plurality of integrated circuits formed by stacking one on top of the other, and on the first integrated circuit. The planar back surface connection surface terminals formed on the back surface of the second integrated circuit arranged are connected to face each other, and the first integrated circuit and the second integrated circuit are connected to the front surface. A semiconductor device electrically connected to each other via a surface terminal and the back surface connection surface terminal. 2. The semiconductor device according to claim 1, wherein the front surface connection surface terminal and the back surface connection surface terminal are separated into a plurality of regions by thin groove-shaped voids, respectively. 3. The second and first integrated circuits arranged above and below the desired region are electrically connected to each other via the desired separated region. The semiconductor device according to claim 1 or 2. 4. The other of the separated regions is the second and the first regions, respectively, which are arranged above and below the region.
4. The semiconductor device according to claim 3, wherein the semiconductor device is interposed between the portions of the integrated circuit which are not electrically connected to each other. 5. The width of the groove-like void is larger than the alignment accuracy when the front surface connection surface terminal and the back surface connection surface terminal are arranged to face each other, and the front surface connection surface terminal and the back surface connection are provided. 5. The semiconductor device according to claim 1, wherein the width is smaller than the width of the area of the surface terminal. 6. The second surface connection surface terminal electrically connected to the second integrated circuit is formed on the upper surface of the second integrated circuit. 6. The semiconductor device according to any one of items 5 to 5. 7. A MOS transistor is formed in the first integrated circuit, and a source and a drain of the MOS transistor are electrically connected to the surface connection surface terminal formed on the integrated circuit through a wiring. 7. The semiconductor device according to claim 1, wherein the semiconductor devices are electrically connected. 8. A second M formed on the second integrated circuit.
The OS transistor is formed on an insulating film formed by stacking on the back surface connection terminal, and wirings connected to the source and the drain of the second MOS transistor are formed on the insulating film and the insulating film. 7. The back surface connecting surface film is electrically connected through a conductor film filled in a back surface through hole provided through the isolation insulating film formed by stacking the back surface connecting film. 8. The semiconductor device according to any one of 1 to 7. 9. A method of manufacturing a semiconductor device including the following steps. A step of stacking and forming an insulating film and a single crystal semiconductor film on a semiconductor substrate; after removing an unnecessary portion of the single crystal semiconductor film, a desired transistor in the single crystal semiconductor film, and an insulating film for separation surrounding the transistor And a step of forming a wiring connected to the transistor and extending on the isolation insulating film, a step of forming a surface insulating film on the entire surface and then flattening the surface of the surface insulating film, and a step of penetrating the surface insulating film. Filling the inside of the contact hole with a conductive substance after forming the contact hole, and a planar surface separated from each other into a plurality of regions by groove-shaped voids on the surface insulating film and the conductive substance. A step of forming a connection surface terminal, a step of laminating and forming a second insulating film and a second single crystal semiconductor film on a second semiconductor substrate, the second single crystal semiconductor After removing an unnecessary portion of the film, the second transistor, the second insulating film surrounding the second transistor, and the second transistor connected to the second transistor are formed over the second single crystal semiconductor film. A step of forming a second wiring; a step of removing the second single crystal semiconductor substrate to expose a back surface of the second insulating film; a step of forming the second insulating film and the second insulating film for separation; A step of forming a through hole penetrating through and reaching the back surface of the second wiring; filling the inside of the through hole with a conductive film, and connecting the second wiring and the back surface connection surface terminal through the conductive film. A step of forming electrically connected planar back surface connection terminals, and a step of connecting the front surface connection terminals and the back surface connection surface terminals to each other. 10. After the step of forming the second wiring,
The method for manufacturing a semiconductor device according to claim 9, wherein the following steps are added. A step of flattening the surface of the second surface insulating film after forming the second surface insulating film on the entire surface; forming a contact hole penetrating the second surface insulating film; Filling with a second conductive material, on the second surface insulating film and the second conductive material,
A step of forming planar second surface connection terminals separated from each other in a plurality of regions by groove-shaped voids. 11. The step of connecting the front surface connection terminal and the back surface connection surface terminal so as to face each other is performed after the surfaces of the front surface connection terminal and the back surface connection surface terminal have been previously cleaned by irradiation with ions. The method of manufacturing a semiconductor device according to claim 9, wherein 12. The method of manufacturing a semiconductor device according to claim 11, wherein the ions are ions of an inert element. 13. The method of manufacturing a semiconductor device according to claim 9, wherein the step of flattening the surface of the surface insulating film is performed by a chemical mechanical polishing method.