JP2529087B2 - Method of manufacturing thermally matched IC chip device - Google Patents

Method of manufacturing thermally matched IC chip device

Info

Publication number
JP2529087B2
JP2529087B2 JP5308362A JP30836293A JP2529087B2 JP 2529087 B2 JP2529087 B2 JP 2529087B2 JP 5308362 A JP5308362 A JP 5308362A JP 30836293 A JP30836293 A JP 30836293A JP 2529087 B2 JP2529087 B2 JP 2529087B2
Authority
JP
Japan
Prior art keywords
chip
substrate
thermal expansion
wiring board
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP5308362A
Other languages
Japanese (ja)
Other versions
JPH077042A (en
Inventor
ロナルド・エル・ウイリアムズ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of JPH077042A publication Critical patent/JPH077042A/en
Application granted granted Critical
Publication of JP2529087B2 publication Critical patent/JP2529087B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、プリント配線板へＩＣ
チップをフリップチップ接着する熱整合されたＩＣチッ
プ装置の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to an IC for a printed wiring board.
The present invention relates to a method of manufacturing a thermally aligned IC chip device in which chips are flip-chip bonded.

【０００２】[0002]

【従来の技術】セラミックプリント回路板への集積回路
（ＩＣ）チップのフリップチップ接着は、例えば自動車
用の複雑な電子装置において使用されている一般的な技
術である。それは、チップから入力および出力ピンの除
去を可能にし、チップ上の対応している接着パッドと配
線板の間のはんだ接着によって回路板に電気的および機
械的に取付けられる。この方法におけるフリップ接着
は、文献（例えば、1990年Van Nostrand Reinhold 社発
行のTummala 氏らによる「Microelectronics Packaging
Handbook 」第 366乃至 376頁、446 乃至 447頁）に記
載されている。入力および出力ピンを介して回路板に接
続される別々にパッケージされたＩＣチップと比較する
と、フリップチップ取付けは一般に相互接続インダクタ
ンスおよびキャパシタンスを低下させることによって回
路特性を改良し、装置のコストを減少させる。Flip-chip bonding of integrated circuit (IC) chips to ceramic printed circuit boards is a common technique used in complex electronic devices, for example in automobiles. It allows the removal of input and output pins from the chip and is electrically and mechanically attached to the circuit board by solder bonding between corresponding bond pads on the chip and the wiring board. Flip bonding in this manner is described in the literature (eg, "Microelectronics Packaging by Tummala et al., Van Nostrand Reinhold, 1990").
Handbook ", pages 366-376, 446-447). Compared to separately packaged IC chips that are connected to a circuit board via input and output pins, flip-chip mounting generally improves circuit characteristics by reducing interconnect inductance and capacitance, reducing device cost. Let

【０００３】セラミック回路板は、チップが接着される
表面上の金属化された相互接続ネットワークを含む。そ
れらは、エポキシあるいはフェノール樹脂およびガラス
繊維布積層から構成され、銅の配線によって配線板内に
形成される電気的相互接続ネットワークを有するプリン
ト配線板（ＰＷＢ）よりも高価である。はんだメッキさ
れた接着パッドはプリント配線板表面上に供給され、内
部相互接続ネットワークに接続される。Ceramic circuit boards include a metallized interconnect network on the surface to which the chips are bonded. They are more expensive than Printed Wiring Boards (PWBs), which are composed of epoxy or phenolic resin and fiberglass cloth laminates and have an electrical interconnection network formed in the wiring board by copper wiring. Solder plated bond pads are provided on the printed wiring board surface and connected to the internal interconnect network.

【０００４】[0004]

【発明が解決しようとする課題】プリント配線板を使用
して、パッケージに収容されＩＣチップから外に伸びて
いるリードワイヤをプリント配線板の接着パッドに接着
してＩＣチップを取り付ける構造は広範囲に使用されて
いる。しかしながら、プリント配線板はセラミック回路
板より安価であり、それらの相互接続能力においてさら
に多用途であるにもかかわらず、プリント配線板にＩＣ
チップをフリップチップ取付け技術により取付ける方法
は実用されていない。これは、チップ（典型的にシリコ
ン）とプリント配線板の間の熱膨張係数の大きい不整合
のためである。シリコンは約２．５乃至３．５ｐｐｍ／
℃の熱膨脹係数を有し、典型的なプリント配線板の熱膨
脹係数はその約８倍である。したがって、１．２５ｃｍ
のシリコンダイは１７０℃から２０℃までの熱の偏位の
ため約５ミクロン収縮するが、ダイが接着される同じ位
置のプリント配線板は約４０ミクロン収縮する。その状
況は図１のａおよびｂに示されており、シリコンあるい
は砒化ガリウムチップ２は一連のはんだ「バンプ」接続
６によってプリント配線板４にフリップチップ取付けさ
れている。図１のａはダイ間の最初の接続を示し、図１
のｂは１７０℃から２０℃のような構造の顕著な冷却後
の状況を誇張された形態で示している。プリント配線板
４はチップ２よりも著しく縮小されており、プリント配
線板４上のはんだバンプ６の部分をチップ２上のバンプ
の両端部よりも接近するように移動させる。これはバン
プにわれ目を生じさせ、チップとプリント配線板の間の
電気的および、または機械的接続に対する分断を生じ
る。There is a wide range of structures in which a printed wiring board is used to attach a lead wire housed in a package and extending out from the IC chip to an adhesive pad of the printed wiring board to mount the IC chip. in use. However, printed wiring boards are less expensive than ceramic circuit boards and, despite being more versatile in their interconnecting capabilities, they can be integrated into ICs.
The method of mounting the chip by the flip chip mounting technique is not in practical use. This is due to the large thermal expansion coefficient mismatch between the chip (typically silicon) and the printed wiring board. Silicon is about 2.5 to 3.5 ppm /
It has a coefficient of thermal expansion of ° C, and the coefficient of thermal expansion of a typical printed wiring board is about eight times that. Therefore, 1.25 cm
The silicon die shrinks about 5 microns due to the heat excursion from 170 ° C to 20 ° C, while the printed wiring board in the same location where the die is bonded shrinks about 40 microns. The situation is illustrated in FIGS. 1a and 1b, where a silicon or gallium arsenide chip 2 is flip chip mounted to a printed wiring board 4 by a series of solder "bump" connections 6. Figure 1a shows the first connection between the dies,
B shows in exaggerated form the situation after significant cooling of the structure at 170 ° C to 20 ° C. The printed wiring board 4 is significantly smaller than the chip 2, and the solder bumps 6 on the printed wiring board 4 are moved so as to be closer to each other than both ends of the bumps on the chip 2. This causes the bumps to become dull and creates a break in the electrical and / or mechanical connection between the chip and the printed wiring board.

【０００５】シリコンチップとセラミック配線板の間に
も熱膨脹係数の不整合が存在するが、それはプリント配
線板よりも厳しくない。セラミック配線板は通常シリコ
ンの熱膨脹係数の約２倍の熱膨脹係数を有し、小さいＩ
Ｃチップのフリップチップ取付けを可能にする配線板を
形成する。このように、チップ装置の２つの最も経済的
な技術であるプリント配線板の使用とフリップチップ取
付けとを組み合わせて使用することができないためその
他の高価な技術を使用しなければならない。There is also a thermal expansion coefficient mismatch between the silicon chip and the ceramic wiring board, but it is less severe than in printed wiring boards. A ceramic wiring board usually has a coefficient of thermal expansion about twice that of silicon and has a small I
Form a wiring board that allows flip-chip attachment of C-chips. Thus, other expensive techniques must be used because the two most economical techniques for chip devices, the use of printed wiring boards and flip-chip mounting, cannot be used in combination.

【０００６】本発明の目的は、従来熱応力のため不可能
であった互いに異なる熱膨脹係数を有するＩＣチップと
プリント配線板とのフリップチップ取付けを確実に行う
ことのできるプリント配線板にフリップチップ取付けに
より接着されたＩＣチップ装置を製造する方法を提供す
ることである。An object of the present invention is to perform flip-chip mounting on a printed wiring board capable of reliably performing flip-chip mounting on an IC chip and a printed wiring board having different coefficients of thermal expansion, which has been impossible in the past due to thermal stress. To provide a method of manufacturing an IC chip device bonded by the method.

【０００７】[0007]

【課題を解決するための手段】この目的は、所定の熱膨
脹範囲にわたってフリップチップ接着の過度の応力を避
けるためにＩＣを支持する薄い半導体層をプリント配線
板の熱膨脹係数に十分に近い熱膨脹係数を有するチップ
基板に接着することによって達成される。ＩＣ半導体層
は、チップ基板の熱膨脹係数を実質的に呈するように十
分に薄くされ、プリント配線板との実効的な熱膨脹係数
の不整合を実質的に減少する。SUMMARY OF THE INVENTION The purpose of this invention is to provide a thin semiconductor layer supporting an IC with a coefficient of thermal expansion sufficiently close to that of a printed wiring board to avoid excessive stress of flip chip bonding over a predetermined thermal expansion range. It is achieved by adhering to a chip substrate having. The IC semiconductor layer is sufficiently thin to substantially exhibit the coefficient of thermal expansion of the chip substrate, substantially reducing the effective coefficient of thermal expansion mismatch with the printed wiring board.

【０００８】本発明の製造方法は、半導体基板と、この
半導体基板上に設けられ、表面領域にＩＣが形成されて
いる半導体薄層とを有するウェーハを使用し、ウェーハ
のＩＣの設けられている側の表面をキャリアに一時的に
接着し、キャリアに接着されているウェーハから半導体
基板を除去し、ＩＣチップを形成するためにチップ基板
にウェーハの残りの部分およびキャリアをその半導体層
側において接着し、その後キャリアを除去し、ＩＣチッ
プをプリント配線板にフリップチップ接着する工程を含
み、半導体層は、チップ基板に接着された状態でこのチ
ップ基板の熱膨脹係数に近似した熱膨脹係数となるよう
にチップ基板に比較してはるかに薄い厚さを有してお
り、プリント配線板の熱膨脹係数は、半導体材料のチッ
プがチップ基板を接着されない状態においてプリント配
線板上にフリップチップ取付けされるときには予め定め
られた温度範囲において不所望なレベルのフリップチッ
プ接着応力を生成する程度に半導体材料の熱膨脹係数と
異なる熱膨脹係数であり、チップ基板は予め定められた
温度範囲において不所望のレベルの応力を避けるために
プリント配線板の熱膨脹係数とほぼ同様の熱膨脹係数を
有していることを特徴とする。The manufacturing method of the present invention uses a wafer having a semiconductor substrate and a semiconductor thin layer provided on the semiconductor substrate and having an IC formed in the surface region, and the wafer IC is provided. Side surface is temporarily adhered to the carrier, the semiconductor substrate is removed from the wafer adhered to the carrier, and the rest of the wafer and the carrier are adhered to the chip substrate on the semiconductor layer side to form an IC chip. Then, the carrier is removed, and the IC chip is flip-chip bonded to the printed wiring board so that the semiconductor layer has a coefficient of thermal expansion similar to that of the chip substrate when bonded to the chip substrate. It has a much smaller thickness than the chip substrate, and the coefficient of thermal expansion of the printed wiring board is such that the chip made of semiconductor material contacts the chip substrate. When it is flip-chip mounted on a printed wiring board in a state where it is not, the coefficient of thermal expansion is different from that of the semiconductor material to the extent that an undesired level of flip-chip adhesive stress is generated in a predetermined temperature range. It is characterized by having a coefficient of thermal expansion substantially similar to that of the printed wiring board in order to avoid an undesired level of stress in a predetermined temperature range.

【０００９】チップ基板はプリント配線板と同じタイプ
の材料から形成され、厳密に整合された熱膨脹係数を与
えることが好ましい。ＩＣ半導体層は半導体層と同程度
の厚さの接着材料の層によってチップ基板に接着される
ことが好ましく、接着は絶縁層が使用される場合にはこ
の絶縁層を介して実行される。絶縁層は、チップ基板の
熱膨脹係数に実質的に等しくなるように十分に薄くさ
れ、製造処理中の半導体基板の除去のためのエッチング
停止部として利用することができる。プリント配線板上
にＩＣチップをフリップチップ取付けで取付けることに
よって、フリップチップ取付け技術およびプリント配線
板技術の両方の利点を組合わせることが可能になり、非
常に経済的な回路装置を得ることができる。The chip substrate is preferably formed from the same type of material as the printed wiring board and provides a closely matched coefficient of thermal expansion. The IC semiconductor layer is preferably adhered to the chip substrate by means of a layer of adhesive material of comparable thickness to the semiconductor layer, the adhesion being carried out through the insulating layer, if an insulating layer is used. The insulating layer is thin enough to be substantially equal to the coefficient of thermal expansion of the chip substrate and can serve as an etch stop for removal of the semiconductor substrate during the manufacturing process. By mounting the IC chip on the printed wiring board by flip-chip mounting, it is possible to combine the advantages of both flip-chip mounting technology and printed wiring board technology, and a very economical circuit device can be obtained. .

【００１０】[0010]

【実施例】本発明のその他の特性および利点は、添付図
面と共に以下の詳細な説明から当業者に明らかとなるで
あろう。本発明の製造方法においては図２のａに示され
ているような通常のＩＣ接着ウェーハ８が使用される。
典型的に５２５ミクロンの厚さの半導体基板10から成る
ウェーハには薄い絶縁ＳｉＯ2 層12が接着され、ＩＣを
支持する薄い半導体層14はこの絶縁層12に接着される。
砒化ガリウムあるいは燐化インジウムのような多数の異
なる種類の半導体材料は本発明によって使用されること
ができるが、ＩＣ層14および基板10は典型的にシリコン
であり、以下の説明ではこれらの素子がシリコンで構成
されているものと仮定する。ＳｉＯ2 層は、２，４およ
び１０ミクロンの厚さのものが現在ＩＣ層14に使用され
ているが、典型的に２ミクロンの厚さである。絶縁層12
の存在は、通常以下説明する製造工程の最後の段階でエ
ッチング止めとして作用するが、本発明に不可欠なもの
ではなく除去されることができる。Other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. In the manufacturing method of the present invention, a normal IC bonded wafer 8 as shown in FIG. 2A is used.
A thin insulating SiO 2 layer 12 is adhered to the wafer, which typically consists of a semiconductor substrate 10 of 525 micron thickness, and a thin semiconductor layer 14 supporting the IC is adhered to this insulating layer 12.
Although a number of different types of semiconductor materials such as gallium arsenide or indium phosphide can be used in accordance with the present invention, IC layer 14 and substrate 10 are typically silicon, and these elements will be referred to in the following description. It is assumed that it is composed of silicon. The SiO 2 layer is typically 2 microns thick, although thicknesses of 2, 4 and 10 microns are currently used for IC layer 14. Insulation layer 12
The presence of .usually acts as an etch stop at the final stage of the manufacturing process described below, but is not essential to the invention and can be removed.

【００１１】本発明によれば、半導体基板10はその後接
着ウェーハから除去され、残りの素子はＩＣ層14がフリ
ップチップ取付けされるプリント配線板に対して非常に
近接した熱膨脹係数整合を有する異なる基板に接着され
る。ＩＣ層14（および使用される場合は絶縁層12）を非
常に薄く保持し、非常に厚い基板に接着することによっ
て、ＩＣ層は厚い基板の熱膨脹係数を実質的に呈するよ
うに形成されることができる。第２の熱膨脹係数を有す
る非常に厚い材料と第１の熱膨脹係数を有する非常に薄
い材料の積層は、既知の現象であり、文献（1953年のMc
Graw-Hill 氏による「The Collected Papers of Stephe
n P. Timoshenko 」第 403乃至 421頁）に記載されてい
る。本発明は、ＩＣ基板14の実効的な熱膨脹係数を変え
るためにこの効果を使用するので、フリップチップ取付
けを可能にするために十分にプリント配線板の熱膨脹係
数と整合する。In accordance with the present invention, the semiconductor substrate 10 is then removed from the bonded wafer and the remaining components are different substrates having a coefficient of thermal expansion match very close to the printed wiring board on which the IC layer 14 is flip chip mounted. Glued to. By holding IC layer 14 (and insulating layer 12 if used) very thin and bonding it to a very thick substrate, the IC layer is formed to substantially exhibit the coefficient of thermal expansion of the thick substrate. You can Lamination of a very thick material with a second coefficient of thermal expansion and a very thin material with a first coefficient of thermal expansion is a known phenomenon, see (1953 Mc
"The Collected Papers of Stephe" by Graw-Hill
n P. Timoshenko ", pp. 403-421). The present invention uses this effect to change the effective coefficient of thermal expansion of the IC substrate 14, so it is well matched to the coefficient of thermal expansion of the printed wiring board to allow flip chip attachment.

【００１２】図２のｂに示されるように、接着ウェーハ
は、次の処理を容易にするために一時的にキャリア16に
接着される。ウェーハはサファイアが適当な材料である
キャリア16に取付けワックス層18によって一時的に接着
される。図２のｃに示される次のステップにおいて、ウ
ェーハ基板10はエッチングして除去される。６０℃の水
酸化カリウムが適当なエッチング剤である。ＳｉＯ2 層
12は、ＩＣ層14を保護するためのエッチング止めとして
作用する。As shown in FIG. 2b, the bonded wafer is temporarily bonded to the carrier 16 to facilitate subsequent processing. The wafer is attached to a carrier 16 of sapphire by a suitable material and temporarily adhered by a layer of wax 18. In the next step, shown in Figure 2c, the wafer substrate 10 is etched away. Potassium hydroxide at 60 ° C is a suitable etchant. SiO 2 layer
12 acts as an etch stop to protect IC layer 14.

【００１３】図３のａに示されるように、装置のＩＣ側
は、最終的な完成されたチップのベースとして作用する
恒久的な基板20に接着される。最終チップとフリップチ
ップが取付けられるプリント配線板の間の熱膨脹係数の
差を実質的に除去するため、プリント配線板に使用され
る材料と同じ材料がチップ基板20にも使用される。しか
しながら、正確な熱膨脹係数整合はフリップチップの取
付けには必要でなく、エポキシガラスのようなプリント
配線板の熱膨脹係数とほぼ同様の熱膨脹係数を有する別
の材料もチップ基板20に使用されることができる。大抵
の目的には、近接した整合が寸法の大きなチップには必
要であるが、約２：１までの熱膨脹係数の差は十分良好
な結果を与える。As shown in FIG. 3a, the IC side of the device is bonded to a permanent substrate 20 which acts as the base for the final completed chip. The same material used for the printed wiring board is also used for the chip substrate 20 to substantially eliminate the difference in coefficient of thermal expansion between the final chip and the printed wiring board to which the flip chip is attached. However, precise coefficient of thermal expansion matching is not required for flip chip attachment, and another material having a coefficient of thermal expansion similar to that of a printed wiring board, such as epoxy glass, may be used for the chip substrate 20. it can. For most purposes close proximity matching is required for large size chips, but differences in coefficient of thermal expansion up to about 2: 1 give reasonably good results.

【００１４】図３のａに示されるように、ＩＣ層14は、
エマーソンカミングズ型３７７の液体エポキシのような
エポキシ層22によってチップ基板20に固定されることが
好ましい。熱接着のような別の取付け手段も使用される
が、好ましくない。エポキシ層22は全体の熱膨脹係数が
チップ基板20の熱膨脹係数とほぼ同様になるように十分
に薄いものでなければならず、ＩＣ層14の熱膨脹係数と
同様の厚さを有することが好ましい。エポキシによる作
用を簡単にするため、エポキシとＩＣ層の両方の厚さは
通常約１０ミクロンであり、少なくともそれらの個々の
厚さは基板20の熱膨脹係数によって制御されるそれらの
実効的な熱膨脹係数を保持するために約２５ミクロンを
超えてはならない。チップ基板20自体の厚さは、それに
取付けられる薄い素子の熱膨脹係数を制御するのに十分
に厚いかぎり非常に柔軟であり、約５００ミクロンの厚
さが典型的である。As shown in FIG. 3a, the IC layer 14 is
It is preferably secured to the chip substrate 20 by an epoxy layer 22 such as Emerson Cummings type 377 liquid epoxy. Other attachment means such as heat bonding are also used but are not preferred. The epoxy layer 22 should be sufficiently thin so that the overall coefficient of thermal expansion is about the same as the coefficient of thermal expansion of the chip substrate 20, and preferably has a thickness similar to that of the IC layer 14. To simplify the action of the epoxy, the thickness of both the epoxy and the IC layer is typically about 10 microns, at least their individual thicknesses being controlled by their effective coefficient of thermal expansion, which is controlled by the coefficient of thermal expansion of the substrate 20. Should not exceed approximately 25 microns. The thickness of the chip substrate 20 itself is very flexible as long as it is thick enough to control the coefficient of thermal expansion of the thin elements attached to it, typically about 500 microns thick.

【００１５】図３のｂに示されるチップ製造の最終ステ
ップにおいて、一時的キャリア16はワックス層18を溶融
することによって除去される。ワックスを約９５℃の温
度まで加熱することが一般にこの目的に適当である。完
成されたチップ24は製造処理の開始と同じＩＣを有する
が、接着されたウェーハ８ではもとのシリコン基板10は
それより高い熱膨脹係数を有するチップ基板20と置換さ
れている。In the final step of chip manufacture, shown in FIG. 3b, the temporary carrier 16 is removed by melting the wax layer 18. Heating the wax to a temperature of about 95 ° C. is generally suitable for this purpose. The finished chip 24 has the same IC as at the beginning of the manufacturing process, but in the bonded wafer 8 the original silicon substrate 10 has been replaced with a chip substrate 20 having a higher coefficient of thermal expansion.

【００１６】プリント配線板26への完成されたチップ24
の取付けは、図３のｃに示されている。チップはＩＣ側
がプリント配線板に向って下方に面するように位置さ
れ、はんだ、導電性エポキシ、あるいはインジウム「バ
ンプ」28ａ，28ｂはチップをプリント配線板に機械的お
よび電気的に接続するために通常の方法で設けられ、図
３のｃにはその２個のみが示されているが、付加的なフ
リップチップ接着が通常行われる。本発明によって提供
されるチップおよびプリント配線板の熱膨脹係数の整合
に関して、フリップチップ接続は設計温度範囲において
は確実である。Finished chip 24 to printed wiring board 26
The mounting of is shown in Figure 3c. The chip is positioned so that the IC side faces downwards toward the printed wiring board, and solder, conductive epoxy, or indium "bumps" 28a, 28b are used to mechanically and electrically connect the chip to the printed wiring board. Additional flip-chip bonding is normally done, although it is provided in a conventional manner, only two of which are shown in Figure 3c. Regarding the matching of the coefficient of thermal expansion of the chip and the printed wiring board provided by the present invention, the flip chip connection is reliable in the design temperature range.

【００１７】本発明の特定の実施例が示され説明されて
いるが、多数の変更および別の実施例は当業者によって
行われるであろう。それ故、本発明は特許請求の範囲に
よってのみ限定されるものである。While particular embodiments of the present invention have been shown and described, numerous modifications and alternative embodiments will occur to those skilled in the art. Therefore, the invention is limited only by the claims.

【図面の簡単な説明】[Brief description of drawings]

【図１】従来の熱不整合の問題を説明するプリント配線
板上のＩＣダイのフリップチップ取付け構造の正面図。FIG. 1 is a front view of a flip-chip mounting structure of an IC die on a printed wiring board, which illustrates a conventional problem of thermal mismatch.

【図２】プリント配線板と熱整合されるＩＣチップの製
造における連続するステップを示す断面図。FIG. 2 is a cross-sectional view showing successive steps in the manufacture of an IC chip that is thermally matched to a printed wiring board.

【図３】プリント配線板と熱整合されるＩＣチップの製
造およびフリップチップ取付けにおける連続するステッ
プを示す断面図。FIG. 3 is a cross-sectional view showing successive steps in manufacturing and flip-chip mounting an IC chip that is thermally matched to a printed wiring board.

【符号の説明】[Explanation of symbols]

14 …ＩＣ半導体層，26…プリント配線板。 14 ... IC semiconductor layer, 26 ... Printed wiring board.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体基板と、この半導体基板上に設け
られ、表面領域にＩＣが形成されている半導体薄層とを
有するウェーハを使用し、 前記ウェーハのＩＣの設けられている側の表面をキャリ
アに一時的に接着し、前記キャリアに接着されている 前記ウェーハから半導体
基板を除去し、 ＩＣチップを形成するためにチップ基板に前記ウェーハ
の残りの部分およびキャリアをその半導体層側において
接着し、 前記キャリアを除去し、 前記ＩＣチップをプリント配線板にフリップチップ接着
する工程を含み、 前記半導体層は、前記チップ基板に接着された状態でこ
のチップ基板の熱膨脹係数に近似した熱膨脹係数となる
ように前記チップ基板に比較してはるかに薄い厚さを有
しており、前記 プリント配線板の熱膨脹係数は、前記半導体材料の
チップが前記チップ基板を接着されない状態において前
記プリント配線板上にフリップチップ取付けされるとき
には予め定められた温度範囲において不所望なレベルの
フリップチップ接着応力を生成する程度に前記半導体材
料の熱膨脹係数と異なる熱膨脹係数であり、 前記チップ基板は前記予め定められた温度範囲において
前記不所望のレベルの応力を避けるために前記プリント
配線板の熱膨脹係数とほぼ同様の熱膨脹係数を有してい
ることを特徴とする熱整合されたＩＣチップ装置の製造
方法。1. A semiconductor substrate and a semiconductor substrate provided on the semiconductor substrate.
And a thin semiconductor layer having an IC formed in the surface region.
In order to form an IC chip, a wafer having the same is used , the surface of the wafer on which the IC is provided is temporarily adhered to a carrier, and the semiconductor substrate is removed from the wafer adhered to the carrier. Bonding the remaining portion of the wafer and a carrier to a chip substrate on the semiconductor layer side, removing the carrier, and flip-chip bonding the IC chip to a printed wiring board, wherein the semiconductor layer is the chip substrate. When glued to
Have a much has thin thickness compared thermal expansion coefficient close to the thermal expansion coefficient of the chip substrate with such a so that the chip substrate
And has a thermal expansion coefficient of the printed wiring board, the <br/> when the chip of the semiconductor material is flip-chip mounted to the front <br/> Symbol printed wiring board in a state which is not bonded to the chip substrate Ri said thermal expansion coefficient der different from the thermal expansion coefficient of the semiconductor material to an extent to produce an undesired level of flip chip bonding stress in a predetermined temperature range, the chip substrate is the undesirable in the temperature range of the predetermined A method for manufacturing a heat-matched IC chip device, which has a coefficient of thermal expansion substantially similar to that of the printed wiring board in order to avoid the stress at the level of 1. 【請求項２】 前記チップ基板は前記プリント配線板の
材料と実質上同一の材料で形成されている請求項１記載
の方法。Wherein said chip substrate The method of claim 1, wherein formed of a material substantially the same material of the printed wiring board. 【請求項３】 前記ウェーハが前記半導体層と前記半導
体基板の間の薄い絶縁層を備え、前記ウェーハおよびキ
ャリアを前記チップ基板に接着する工程において前記半
導体層が前記絶縁層を介して前記チップ基板に接着さ
れ、前記絶縁層はチップ基板の熱膨脹係数に近似した熱
膨脹係数となるように前記チップ基板に 比較してはるか
に薄くされている請求項１記載の方法。3. The wafer comprises a thin insulating layer between the semiconductor layer and the semiconductor substrate, and the step of adhering the wafer and carrier to the chip substrate comprises:
The conductor layer is adhered to the chip substrate through the insulating layer, and the insulating layer has a thermal expansion coefficient close to that of the chip substrate.
Compared to the chip substrate , the coefficient of expansion is much higher.
Thinned method of claim 1 are in.
JP5308362A 1992-12-08 1993-12-08 Method of manufacturing thermally matched IC chip device Expired - Fee Related JP2529087B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98804592A 1992-12-08 1992-12-08
US988045 1992-12-08

Publications (2)

Publication Number Publication Date
JPH077042A JPH077042A (en) 1995-01-10
JP2529087B2 true JP2529087B2 (en) 1996-08-28

Family

ID=25533797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5308362A Expired - Fee Related JP2529087B2 (en) 1992-12-08 1993-12-08 Method of manufacturing thermally matched IC chip device

Country Status (2)

Country Link
JP (1) JP2529087B2 (en)
GB (1) GB2276977B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2825083B2 (en) * 1996-08-20 1998-11-18 日本電気株式会社 Semiconductor element mounting structure
US5868887A (en) * 1996-11-08 1999-02-09 W. L. Gore & Associates, Inc. Method for minimizing warp and die stress in the production of an electronic assembly
JP3037229B2 (en) 1997-10-23 2000-04-24 新潟日本電気株式会社 Bare chip mounting method and mounting device
US6320754B1 (en) * 1999-08-06 2001-11-20 Agilent Technologies, Inc. Apparatus for the reduction of interfacial stress caused by differential thermal expansion in an integrated circuit package
US6291884B1 (en) * 1999-11-09 2001-09-18 Amkor Technology, Inc. Chip-size semiconductor packages

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS634635A (en) * 1986-06-25 1988-01-09 Hitachi Ltd Semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same

Also Published As

Publication number Publication date
JPH077042A (en) 1995-01-10
GB2276977A (en) 1994-10-12
GB2276977B (en) 1996-09-18
GB9325072D0 (en) 1994-02-02

Similar Documents

Publication Publication Date Title
US7186586B2 (en) Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP3677429B2 (en) Method of manufacturing flip chip type semiconductor device
US7034401B2 (en) Packaging substrates for integrated circuits and soldering methods
US5273940A (en) Multiple chip package with thinned semiconductor chips
US6717252B2 (en) Semiconductor device
JP2001217386A (en) Semiconductor device, method of manufacturing the same, and electronic equipment
JP2001135663A (en) Semiconductor device and its manufacturing method
CN110911364A (en) Embedded die package with integrated ceramic substrate
JP2529087B2 (en) Method of manufacturing thermally matched IC chip device
US5966803A (en) Ball grid array having no through holes or via interconnections
TW202141718A (en) Semiconductor module and manufacturing method of the same
JPH06333962A (en) Semiconductor chip module
JPS62122258A (en) Multiple-chip package
KR19980058412A (en) Multilayer Multi-chip Module Semiconductor Device and Manufacturing Method Thereof
KR101008534B1 (en) Power semiconductor mudule package and method for fabricating the same
JP2001332685A (en) Method for manufacturing semiconductor device
JP2002252309A (en) Structure and method for packaging semiconductor chip
JPH118250A (en) Semiconductor integrated circuit device and manufacture of the same
KR20000011643A (en) Device and method for connecting two electronic components
JP2713879B2 (en) Multi-chip package with direct electrical connection between internal leads and board bonding pads
WO2023079678A1 (en) Semiconductor device and production method therefor
JPH0462457B2 (en)
WO2000019531A1 (en) Backside electrical contact structure for a module having an exposed backside
JP2001176940A (en) Method for manufacturing semiconductor module
JP3249263B2 (en) Semiconductor package and manufacturing method thereof

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees