WO2000019531A1 - Backside electrical contact structure for a module having an exposed backside - Google Patents

Backside electrical contact structure for a module having an exposed backside Download PDF

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Publication number
WO2000019531A1
WO2000019531A1 PCT/US1999/019084 US9919084W WO0019531A1 WO 2000019531 A1 WO2000019531 A1 WO 2000019531A1 US 9919084 W US9919084 W US 9919084W WO 0019531 A1 WO0019531 A1 WO 0019531A1
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WO
WIPO (PCT)
Prior art keywords
module
planar upper
planar
backside
integrated circuit
Prior art date
Application number
PCT/US1999/019084
Other languages
French (fr)
Inventor
Hassan S. Hashemi
Original Assignee
Conexant Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems, Inc. filed Critical Conexant Systems, Inc.
Publication of WO2000019531A1 publication Critical patent/WO2000019531A1/en

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Definitions

  • the present invention generally relates to electronic packaging, and more particularly, to a backside (i.e., non-device side) structure for a module having an exposed backside.
  • a backside i.e., non-device side
  • the structure that supports the semiconductor device (i.e., chip) and provides the necessary I/O interconnections is commonly referred to as an electronic package.
  • the electronic package is designed to provide structural support, environmental protection, and dissipation of device generated heat.
  • the package provides the connections for signal lines leading onto and out of the semiconductor device, including wire lines to support I/O and varying potentials for power and ground. These connections must be made at each level of a packaging hierarchy and as this hierarchy is traversed, scaling or space transformation must be provided in order to compensate for the increasing circuit and wire line pitch.
  • the packaging hierarchy is usually divided into three levels.
  • the first level is the module, which is comprised of the integrated circuit (IC) chip bonded to a substrate or chip carrier.
  • the second level is the module on a card, and the third level is the card on a mother board.
  • the packaging hierarchy is structured such that the wire lines at each successive level increase to provide the necessary scaling from the small line spacing of the IC chip at the first level to the much larger wire lines at the third level leading to an external device.
  • the module may be formed utilizing a variety of processes.
  • One method that has continued to increase in popularity is flip-chip bonding. This method generally involves the formation of very small solder balls on the device side of the substrate followed by placement of the solder balls onto the carrier .
  • the contact of the solder balls with the carrier and the subsequent application of heat results in the solder balls melting onto an array of metal pads on the surface of the carrier.
  • the liquid solder assists in the alignment of the chip and the carrier, and the chip is electrically, mechanically, and thermally connected to the carrier to form the module.
  • flip-chip bonding and the resulting flip-chip module provides significant advantages that includes minimizing the distance between the electrical contacts of the IC chip and the electrical contacts of the carrier such that path inductance is reduced, the resulting module does have some disadvantages, including an exposed non-device side of the chip (i.e., backside) and a lack of mechanical or electrical coupling to the carrier.
  • IC Integrated Circuit
  • GaAs Gallium Arsenide
  • Si Silicon
  • RF Radio Frequency
  • a bias to the backside is desirable, and in the case of an NMOS process, a backside bias is typically preferred.
  • some analog designs benefit from a distribution of any potential that is applied to the backside substrate, and shielding of an exposed substrate from Electromagnetic Induction (EMI) and Electromagnetic Conduction (EMC) improves mechanical protection.
  • EMI Electromagnetic Induction
  • EMC Electromagnetic Conduction
  • distribution of heat while providing a suitable surface for thermal enhancement is generally advantageous to most IC operations.
  • the present invention may be utilized for, but is not limited to, equalization of the potential of an exposed substrate, improvement of device shielding and mechanical protection, and distribution of device generated heat while presenting a suitable surface for additional thermal enhancement.
  • a module in accordance with a preferred embodiment of the present invention, includes an integrated circuit chip having a first planar upper surface and a first planar lower surface having a first plurality of electrical contacts disposed thereon.
  • the module also has an interconnect substrate having a second planar upper surface abutting the first planar lower surface, with the second planar upper surface having a second plurality of electrical contacts disposed thereon that are electrically connected to selected electrical contacts of the first plurality of electrical contacts.
  • a backside structure is provided that connects the first planar upper surface of the integrated circuit chip and the second planar upper surface of the interconnect substrate.
  • FIG. 1 is a flip-chip module provided with a backside structure according to a preferred embodiment of the present invention.
  • FIG. 2 is an alternate embodiment of a flip-chip module provided with a backside structure according to a preferred embodiment of the present invention.
  • a module 20 according to a preferred embodiment of the present invention is shown that includes an Integrated Circuit (IC) chip 22 having a first planar upper surface or backside (i.e., non-device side) 24 and a first planar lower surface 26, an interconnect substrate or chip carrier 28 having a second planar upper surface 30 abutting the first planar lower surface 26, and a backside structure 32.
  • IC Integrated Circuit
  • the IC chip 22 has a plurality of electrical contacts (not shown) on the first planar lower surface 26 that are electrically connected, for example by solder joints or any other suitable connector, to selected electrical contacts on the second planar upper surface 30 of the chip carrier 28.
  • the IC chip 22 is generally created on a suitable substrate material upon which or within which semiconductor devices may be formed and the backside 24 of the chip 22 is provided with a suitable back material scheme 38 which may include a conductive material such as gold (Au), gold (Au) flash, or any other suitable material.
  • Suitable materials for the substrate include, for example, group IV semiconductors (i.e., Si, Ge, and SiGe), group 11 l-V semiconductors (i.e., GaAs, InAs, and AIGaAs), and other less-conventional materials, such as SiC, diamond, and sapphire.
  • the substrate may include single crystal material, or may have one or more polycrystalline or amorphous epitaxial layers formed on a suitable base material.
  • the epitaxial layer is generally oxidized and etched using dry etching or wet etching techniques to form a mask pattern in the oxide, thereby exposing an area for doping. The exposed areas are subsequently doped, followed by metallization and patterning to form desired electronic components, and metal evaporation and etching are performed to produce circuits and interconnections therebetween.
  • the chip carrier 28 to which the IC chip 22 connected is typically an organic (i.e., laminate) or non-organic (i.e., ceramic) circuit board that is adapted for interconnection with additional components of an electronic assembly (not shown) and is often made of materials such as aluminum oxide (AI 2 O 3 ), aluminum nitride (AIN), beryllium oxide (BeO), and the like. However, a wide variety of materials and compositions of materials may be utilized.
  • the interconnection by the chip carrier 28 is generally provided by a wiring structure produced by thin-film technology.
  • the IC chip 22 is connected to the carrier 28 using flip-chip bonding, stud bumping, organic flip-chip methods, or the like.
  • Flip-chip bonding involves depositing solder at multiple locations on the first planar lower surface 26 of the IC chip 22 corresponding to selected electrical contacts of the IC chip 22.
  • the first planar lower surface 26 is heated such that the deposited solder is melted and very small solder balls 34 are formed.
  • the first planar lower surface 26 having the solder balls 34 is placed on the second planar upper surface 30 of the chip carrier 28 such that the electrical contacts of the carrier 28 abut selected solder balls 34.
  • solder balls 34 are aligned and connected with the electrical contacts of the carrier 28, heat is applied to reflow the solder bumps 34, thereby metallurgically and electrically bonding the IC chip 22 and the carrier 28 to form the module 20.
  • an underfill material 36 may be provided between the first planar lower surface 26 and the second planar upper surface 30 to provide electrical isolation between the contacts and allow the structure to withstand additional wire bonding temperatures without reflowing the solder balls.
  • connection material 40 which may be an epoxy, metallurgical adhesive, or the like, is deposited on the back material scheme 38 which has been placed on the backside 24 as previously indicated.
  • connection material 40 may be a conductive epoxy such as Ablebond 84-ILMIT epoxy or Eutectic Solder (63 Sn/37 Pb).
  • the connection material 40 is disposed between the backside structure 32 and the backside 24 of the IC chip 22 in order to assist in the connection of the backside structure 32 to the backside 24 of the IC chip 22.
  • a backside structure 42 that includes a lid 44, first interconnect 42 and second interconnect 46.
  • the lid 42 is connected to the first planar upper surface 24 and the second planar upper surface 30 of the chip carrier 28. More particularly, the lid 42 is adhesively or metallurgically bonded to the first planar upper surface 24 utilizing the connection material 40 and the lid 42 is connected to the second planar upper surface 30 of the chip carrier 28 with the first interconnect 44 and second interconnect 46 that are secured to a first bond pad 48 on the second planar upper surface 30 and a second bond pad 50 on the second planar upper surface 30, respectively. While two or more interconnects may be used to connect the lid 42 to the chip carrier 28, a single interconnect will suffice.
  • the lid 42, first interconnect 44 and second interconnect 46 may be formed of any number of materials or compounds that are selected based upon the desired functionality of the backside structure 32.
  • the lid 42 is to be used as a component in a biasing structure, Aluminum (Al), Copper (Cu), or Steel may be utilized.
  • the lid 42, first interconnect 44 and second interconnect 46 may be initially formed as a unitary component.
  • first interconnect 44, second interconnect 46, first bond pad 48 and second bond pad 50 may be formed of any number of materials or compounds selected based upon the desired functionality of the backside structure 32.
  • Copper (Cu) with potential plating like Nickel/Gold (Ni/Au), Nickel/[ ]/Gold (Ni/Pd/Au), or Copper (Cu) with an organic protector to limit oxidation, or the like, may be used to form the bond pads 48,50.
  • the backside structure 32 may be configured to perform any number of functions, including, but not limited to biasing the substrate forming the backside 24 (i.e., a biasing structure), shielding for active circuits of the module 20 (i.e., a shielding structure), environmentally or mechanically protecting the backside 24 (i.e., a protection structure), distributing circuit generated heat emanating from the backside 24 (i.e., a heat distribution structure), or providing a suitable surface for additional thermal enhancements of the module 20 (i.e., a thermal enhancement structure).
  • biasing the substrate forming the backside 24 i.e., a biasing structure
  • shielding for active circuits of the module 20 i.e., a shielding structure
  • environmentally or mechanically protecting the backside 24 i.e., a protection structure
  • distributing circuit generated heat emanating from the backside 24 i.e., a heat distribution structure
  • providing a suitable surface for additional thermal enhancements of the module 20 i.e., a thermal enhancement
  • the backside structure 32 forms the biasing structure that provides a conductive path from the electrical contacts (not shown) associated with the first bond pad 48 and second bond pad 50 to the backside 24 of the IC chip 22.
  • the first bonding pad 48 and second bonding pad 50 may be connected to a voltage plane or rail (not shown) or ground plane or rail (not shown) in the chip carrier 28. This allows the application of a voltage potential or ground to the backside 24 that is supplied by an electrical contact of the chip carrier 28 such that the backside 24 of the IC chip 22 is biased to a desired voltage or ground.
  • the size (i.e., area) of the backside structure 32 may be selected such that a substantial portion of the backside 24 may be covered by the backside structure 32. Therefore, application of a voltage or ground to the backside structure 32 may be used to equalize the potential across the substrate forming the backside 24.
  • the shape, materials used, and configuration of the backside structure 32 may be varied to accomplish the previously mentioned tasks and many additional functions.
  • FIG. 2 an alternate embodiment is shown for providing a backside structure that may be utilized in order to provide a bias to the exposed backside 24 of the IC chip 22.
  • the following description will be directed to an alternate backside 32 structure of the previously described module 20 of FIG. 1 with like numerals designating like elements.
  • the backside structure 32 includes a first wire 52 and a second wire 54 that are connected from the back metal 38 to the first bond pad 48 and second bond pad 50 on the second planar upper surface 30 of the chip carrier 28, respectively.
  • the first wire 52 and second wire 54 are formed using wire bonding techniques involving thermal compression bonding that includes, for example, Au ball or wedge bonding.
  • thermal compression bonding that includes, for example, Au ball or wedge bonding.
  • many methods are available for wire bonding and the foregoing should not be interpreted to limit the invention to the wire bonding examples that are presented for illustrative purposes.
  • first wire 52 and second wire 54 electrically couple the backside 24 and the electrical contacts of the chip carrier 28 associated with the first bond pad 48 and second bond pad 50.
  • a single wire or more than two wires may be used to electrically connect the backside 24 to a power source or ground presented at the first bond pad 48 or second bond pad 50. Irrespective of the wire numbers or bond pad sources provided to the backside 24, a conductive path is created by which the backside may be biased to a desired potential, including ground.
  • a backside structure may be provided for a module having an exposed backside.
  • This backside structure is available for biasing the backside of an IC substrate, including the means by which to equalize the potential of the IC substrate.
  • the backside structure may be configured to provide device shielding, mechanical protection, environmental protection, heat dissipation, and a suitable surface for additional thermal enhancements.
  • the applications of this invention are vast and many variations are available.
  • the above descriptions are preferred exemplary embodiments only, and are not intended to be limiting in any way.
  • Various modifications, substitutions, and other applications of the embodiments discussed herein may be made without departing from the spirit and the scope of the invention as set forth in the appended claims.

Abstract

A module is provided that includes an integrated circuit chip having a first planar upper surface and a first planar lower surface having a first plurality of electrical contacts disposed thereon. The module also has an interconnect substrate having a second planar upper surface abutting the first planar lower surface, with the second planar upper surface having a second plurality of electrical contacts disposed thereon and electrically connected to selected electrical contacts of the first plurality of electrical contacts. A backside structure is provided that connects the first planar upper surface of the integrated circuit chip and the second planar upper surface of the interconnect substrate.

Description

BACKSIDE ELECTRICAL CONTACT STRUCTURE FOR A MODULE HAVING AN EXPOSED BACKSIDE
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to electronic packaging, and more particularly, to a backside (i.e., non-device side) structure for a module having an exposed backside.
2. Background Art and Technical Problems
The microelectronics industry has continued to make significant semiconductor advances in semiconductor device technology. These achievements are producing silicon-based integrated circuits with increased circuit densities and elevated rates of operation. However, as circuit density and speed are improved, corresponding progress must be made with the structure that supports the semiconductor device and provides the necessary input/output (I/O) interconnections.
The structure that supports the semiconductor device (i.e., chip) and provides the necessary I/O interconnections is commonly referred to as an electronic package. The electronic package is designed to provide structural support, environmental protection, and dissipation of device generated heat. Furthermore, the package provides the connections for signal lines leading onto and out of the semiconductor device, including wire lines to support I/O and varying potentials for power and ground. These connections must be made at each level of a packaging hierarchy and as this hierarchy is traversed, scaling or space transformation must be provided in order to compensate for the increasing circuit and wire line pitch.
The packaging hierarchy is usually divided into three levels. The first level is the module, which is comprised of the integrated circuit (IC) chip bonded to a substrate or chip carrier. The second level is the module on a card, and the third level is the card on a mother board. The packaging hierarchy is structured such that the wire lines at each successive level increase to provide the necessary scaling from the small line spacing of the IC chip at the first level to the much larger wire lines at the third level leading to an external device. The module may be formed utilizing a variety of processes. One method that has continued to increase in popularity is flip-chip bonding. This method generally involves the formation of very small solder balls on the device side of the substrate followed by placement of the solder balls onto the carrier . The contact of the solder balls with the carrier and the subsequent application of heat results in the solder balls melting onto an array of metal pads on the surface of the carrier. The liquid solder assists in the alignment of the chip and the carrier, and the chip is electrically, mechanically, and thermally connected to the carrier to form the module. While flip-chip bonding and the resulting flip-chip module provides significant advantages that includes minimizing the distance between the electrical contacts of the IC chip and the electrical contacts of the carrier such that path inductance is reduced, the resulting module does have some disadvantages, including an exposed non-device side of the chip (i.e., backside) and a lack of mechanical or electrical coupling to the carrier.
For certain Integrated Circuit (IC) devices, such as Gallium Arsenide (GaAs) or Silicon (Si) Radio Frequency (RF) devices, a bias to the backside is desirable, and in the case of an NMOS process, a backside bias is typically preferred. Furthermore, some analog designs benefit from a distribution of any potential that is applied to the backside substrate, and shielding of an exposed substrate from Electromagnetic Induction (EMI) and Electromagnetic Conduction (EMC) improves mechanical protection. In addition, distribution of heat while providing a suitable surface for thermal enhancement is generally advantageous to most IC operations. However, if the first level of the packaging hierarchy is a flip-chip module or the device is packaged in a Chip-Scale Package (CSP) format, or any other format having an exposed non-device side, these aforementioned attributes and features are unavailable. In view of the foregoing, it is one aspect of the present invention to provide a backside structure for a module having an exposed non-device side, including, but not limited to, flip-chip or CSP modules. Accordingly, the present invention may be utilized for, but is not limited to, equalization of the potential of an exposed substrate, improvement of device shielding and mechanical protection, and distribution of device generated heat while presenting a suitable surface for additional thermal enhancement. SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a module is provided that includes an integrated circuit chip having a first planar upper surface and a first planar lower surface having a first plurality of electrical contacts disposed thereon. The module also has an interconnect substrate having a second planar upper surface abutting the first planar lower surface, with the second planar upper surface having a second plurality of electrical contacts disposed thereon that are electrically connected to selected electrical contacts of the first plurality of electrical contacts. A backside structure is provided that connects the first planar upper surface of the integrated circuit chip and the second planar upper surface of the interconnect substrate.
BRIEF DESCRIPTION OF THE DRAWINGS Additional aspects of the present invention will become evident to one skilled in the art upon reviewing the non-limiting embodiments described in the specification and the claims taken in conjunction with the accompanying figures, wherein like numerals designate like elements, and:
FIG. 1 is a flip-chip module provided with a backside structure according to a preferred embodiment of the present invention; and
FIG. 2 is an alternate embodiment of a flip-chip module provided with a backside structure according to a preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS The ensuing descriptions are preferred exemplary embodiments only, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the ensuing descriptions will provide those skilled in the art with a convenient road map for implementing a preferred embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in the preferred embodiments without departing from the spirit and scope of the invention as set forth in the appended claims. Referring now to FIG. 1 , a module 20 according to a preferred embodiment of the present invention is shown that includes an Integrated Circuit (IC) chip 22 having a first planar upper surface or backside (i.e., non-device side) 24 and a first planar lower surface 26, an interconnect substrate or chip carrier 28 having a second planar upper surface 30 abutting the first planar lower surface 26, and a backside structure 32.
More particularly, the IC chip 22 has a plurality of electrical contacts (not shown) on the first planar lower surface 26 that are electrically connected, for example by solder joints or any other suitable connector, to selected electrical contacts on the second planar upper surface 30 of the chip carrier 28. The IC chip 22 is generally created on a suitable substrate material upon which or within which semiconductor devices may be formed and the backside 24 of the chip 22 is provided with a suitable back material scheme 38 which may include a conductive material such as gold (Au), gold (Au) flash, or any other suitable material.
Suitable materials for the substrate include, for example, group IV semiconductors (i.e., Si, Ge, and SiGe), group 11 l-V semiconductors (i.e., GaAs, InAs, and AIGaAs), and other less-conventional materials, such as SiC, diamond, and sapphire. The substrate may include single crystal material, or may have one or more polycrystalline or amorphous epitaxial layers formed on a suitable base material. The epitaxial layer is generally oxidized and etched using dry etching or wet etching techniques to form a mask pattern in the oxide, thereby exposing an area for doping. The exposed areas are subsequently doped, followed by metallization and patterning to form desired electronic components, and metal evaporation and etching are performed to produce circuits and interconnections therebetween.
The chip carrier 28 to which the IC chip 22 connected is typically an organic (i.e., laminate) or non-organic (i.e., ceramic) circuit board that is adapted for interconnection with additional components of an electronic assembly (not shown) and is often made of materials such as aluminum oxide (AI2O3), aluminum nitride (AIN), beryllium oxide (BeO), and the like. However, a wide variety of materials and compositions of materials may be utilized. The interconnection by the chip carrier 28 is generally provided by a wiring structure produced by thin-film technology.
In this description, the IC chip 22 is connected to the carrier 28 using flip-chip bonding, stud bumping, organic flip-chip methods, or the like. However, the invention is applicable to numerous module configurations in which the backside of the substrate is exposed. Flip-chip bonding involves depositing solder at multiple locations on the first planar lower surface 26 of the IC chip 22 corresponding to selected electrical contacts of the IC chip 22. The first planar lower surface 26 is heated such that the deposited solder is melted and very small solder balls 34 are formed. The first planar lower surface 26 having the solder balls 34 is placed on the second planar upper surface 30 of the chip carrier 28 such that the electrical contacts of the carrier 28 abut selected solder balls 34. Once the solder balls 34 are aligned and connected with the electrical contacts of the carrier 28, heat is applied to reflow the solder bumps 34, thereby metallurgically and electrically bonding the IC chip 22 and the carrier 28 to form the module 20. Furthermore, if desired, an underfill material 36 may be provided between the first planar lower surface 26 and the second planar upper surface 30 to provide electrical isolation between the contacts and allow the structure to withstand additional wire bonding temperatures without reflowing the solder balls.
Once the IC chip 22 is connected to carrier 28, a connection material 40, which may be an epoxy, metallurgical adhesive, or the like, is deposited on the back material scheme 38 which has been placed on the backside 24 as previously indicated. For example, connection material 40 may be a conductive epoxy such as Ablebond 84-ILMIT epoxy or Eutectic Solder (63 Sn/37 Pb). The connection material 40 is disposed between the backside structure 32 and the backside 24 of the IC chip 22 in order to assist in the connection of the backside structure 32 to the backside 24 of the IC chip 22.
With continued reference to FIG. 1 , a backside structure 42 is shown that includes a lid 44, first interconnect 42 and second interconnect 46. The lid 42 is connected to the first planar upper surface 24 and the second planar upper surface 30 of the chip carrier 28. More particularly, the lid 42 is adhesively or metallurgically bonded to the first planar upper surface 24 utilizing the connection material 40 and the lid 42 is connected to the second planar upper surface 30 of the chip carrier 28 with the first interconnect 44 and second interconnect 46 that are secured to a first bond pad 48 on the second planar upper surface 30 and a second bond pad 50 on the second planar upper surface 30, respectively. While two or more interconnects may be used to connect the lid 42 to the chip carrier 28, a single interconnect will suffice.
The lid 42, first interconnect 44 and second interconnect 46 may be formed of any number of materials or compounds that are selected based upon the desired functionality of the backside structure 32. For example, if the lid 42 is to be used as a component in a biasing structure, Aluminum (Al), Copper (Cu), or Steel may be utilized. Furthermore, the lid 42, first interconnect 44 and second interconnect 46 may be initially formed as a unitary component. In addition, as with the lid 42, first interconnect 44, second interconnect 46, first bond pad 48 and second bond pad 50 may be formed of any number of materials or compounds selected based upon the desired functionality of the backside structure 32. For example, if the backside structure is to provide backside biasing as will be subsequently described, Copper (Cu) with potential plating like Nickel/Gold (Ni/Au), Nickel/[ ]/Gold (Ni/Pd/Au), or Copper (Cu) with an organic protector to limit oxidation, or the like, may be used to form the bond pads 48,50.
As can be appreciated from the foregoing description, the backside structure 32 may be configured to perform any number of functions, including, but not limited to biasing the substrate forming the backside 24 (i.e., a biasing structure), shielding for active circuits of the module 20 (i.e., a shielding structure), environmentally or mechanically protecting the backside 24 (i.e., a protection structure), distributing circuit generated heat emanating from the backside 24 (i.e., a heat distribution structure), or providing a suitable surface for additional thermal enhancements of the module 20 (i.e., a thermal enhancement structure). For example, if the backside structure 32 is to provide a biasing of the substrate or backside 24, the backside structure 32 forms the biasing structure that provides a conductive path from the electrical contacts (not shown) associated with the first bond pad 48 and second bond pad 50 to the backside 24 of the IC chip 22. Additionally, the first bonding pad 48 and second bonding pad 50 may be connected to a voltage plane or rail (not shown) or ground plane or rail (not shown) in the chip carrier 28. This allows the application of a voltage potential or ground to the backside 24 that is supplied by an electrical contact of the chip carrier 28 such that the backside 24 of the IC chip 22 is biased to a desired voltage or ground. Furthermore, the size (i.e., area) of the backside structure 32, and in this example the biasing structure, may be selected such that a substantial portion of the backside 24 may be covered by the backside structure 32. Therefore, application of a voltage or ground to the backside structure 32 may be used to equalize the potential across the substrate forming the backside 24. As this example demonstrates, the shape, materials used, and configuration of the backside structure 32 may be varied to accomplish the previously mentioned tasks and many additional functions.
Referring now to FIG. 2, an alternate embodiment is shown for providing a backside structure that may be utilized in order to provide a bias to the exposed backside 24 of the IC chip 22. In order to maintain clarity and simplicity, the following description will be directed to an alternate backside 32 structure of the previously described module 20 of FIG. 1 with like numerals designating like elements.
As can be seen in FIG. 2, the backside structure 32 includes a first wire 52 and a second wire 54 that are connected from the back metal 38 to the first bond pad 48 and second bond pad 50 on the second planar upper surface 30 of the chip carrier 28, respectively. In this description, the first wire 52 and second wire 54 are formed using wire bonding techniques involving thermal compression bonding that includes, for example, Au ball or wedge bonding. However, many methods are available for wire bonding and the foregoing should not be interpreted to limit the invention to the wire bonding examples that are presented for illustrative purposes.
As can be appreciated, the first wire 52 and second wire 54 electrically couple the backside 24 and the electrical contacts of the chip carrier 28 associated with the first bond pad 48 and second bond pad 50. Alternatively, a single wire or more than two wires may be used to electrically connect the backside 24 to a power source or ground presented at the first bond pad 48 or second bond pad 50. Irrespective of the wire numbers or bond pad sources provided to the backside 24, a conductive path is created by which the backside may be biased to a desired potential, including ground.
From the foregoing, it can be seen that a backside structure may be provided for a module having an exposed backside. This backside structure is available for biasing the backside of an IC substrate, including the means by which to equalize the potential of the IC substrate. Furthermore, the backside structure may be configured to provide device shielding, mechanical protection, environmental protection, heat dissipation, and a suitable surface for additional thermal enhancements. However, the applications of this invention are vast and many variations are available. In addition, it will be understood that the above descriptions are preferred exemplary embodiments only, and are not intended to be limiting in any way. Various modifications, substitutions, and other applications of the embodiments discussed herein may be made without departing from the spirit and the scope of the invention as set forth in the appended claims.

Claims

1. A module of an electronic package, comprising: an integrated circuit chip having a first planar upper surface and a first planar lower surface, said first planar lower surface having a first plurality of electrical contacts disposed thereon; an interconnect substrate having a second planar upper surface abutting said first planar lower surface, said second planar upper surface having a second plurality of electrical contacts disposed thereon that are electrically connected to selected electrical contacts of said first plurality of electrical contacts; and a backside structure connecting said first planar upper surface of said integrated circuit chip and said second planar upper surface of said interconnect substrate.
2. The module of claim 1 , wherein said backside structure comprises a lid and a first interconnect, said first interconnect connected to said lid and said second planar upper surface of said interconnect substrate.
3. The module of claim 2, wherein said backside structure further comprises a second interconnect, said second interconnect connected to said lid and said second planar upper surface of said interconnect substrate.
4. The module of claim 2, further comprising a first bond pad on said second planar upper surface of said interconnect substrate, said first bond pad receiving said first interconnect.
5. The module of claim 4, further comprising a second bond pad on said second planar upper surface of said interconnect substrate, said second bond pad receiving said second interconnect.
6. The module of claim 2, wherein said lid and said first interconnect are formed as a contiguous component.
7. The module of claim 1 , wherein said backside structure comprises a first wire connected to said first planar upper surface of said integrated circuit chip and said second planar upper surface of said interconnect substrate.
8. The module of claim 7, wherein said backside structure comprises a second wire connected to said first planar upper surface of said integrated circuit chip and said second planar upper surface of said interconnect substrate.
9. The module of claim 1 , said module further comprising a connection material disposed between said backside structure and said first upper surface of said integrated chip.
10. The module of claim 9, wherein said connection material is an epoxy.
11. The module of claim 9, wherein said connection material is a metallurgical adhesive.
12. The module of claim 1 , wherein said backside structure is configured to form a biasing structure.
13. The module of claim 1 , wherein said backside structure is configured to form a shielding structure.
14. The module of claim 1 , wherein said backside structure is configured to form a protection structure.
15. The module of claim 1 , wherein said backside structure is configured to form a heat distribution structure.
16. The module of claim 1 , wherein said backside structure is configured to form a thermal enhancement structure.
17. A method of forming a module of an electronic package, comprising the steps of:
(a) producing an integrated circuit chip having a first planar upper surface and a first planar lower surface, said first planar lower surface having a first plurality of electrical contacts disposed thereon;
(b) abutting an interconnect substrate having a second planar upper surface with said first planar lower surface, said second planar upper surface having a second plurality of electrical contacts disposed thereon and electrically connected to selected electrical contacts of said first plurality of electrical contacts; and
(c) connecting said first planar upper surface of said integrated circuit chip and said second planar upper surface of said interconnect substrate with a backside structure.
18. The method of claim 17, further comprising the step of depositing a connection material on said first planar upper surface of said integrated circuit chip.
19. The method of claim 17, further comprising the step of configuring said backside structure in order to provide a bias to said first planar upper surface of said integrated circuit chip.
20. A method of forming a flip-chip module, comprising the steps of:
(a) depositing solder at a plurality of locations on a first planar lower surface of an integrated circuit chip; (b) heating said first planar surface of said integrated circuit chip such that said solder at said plurality of locations on said first planar surface of said integrated circuit chip is melted and a plurality of solder bumps are formed;
(c) abutting said plurality of solder bumps with a plurality of electrical contacts disposed on a planar surface of an interconnect substrate; (d) reflowing said plurality of solder bumps so as to metallurgically and electrically bond said integrated circuit chip to said interconnect substrate; and (e) connecting said first planar upper surface of said integrated circuit chip and a second planar upper surface of said interconnect substrate with a backside structure.
PCT/US1999/019084 1998-09-29 1999-08-23 Backside electrical contact structure for a module having an exposed backside WO2000019531A1 (en)

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