JP2001176940A - Method for manufacturing semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a wafer burn-in without decreasing the number of installed chips per wafer. SOLUTION: In a method for manufacturing a semiconductor module in which (a) a projecting electrode 4 is formed on an electrode of each undivided chip 2 formed in a semiconductor wafer 1; (b) a connection terminal is formed at a position against the projecting electrode 4 on a surface of a substrate 5, and a terminal of a power supply, GND, an input signal and a data I/O is formed in a peripheral region, an external connection terminal is formed on a back surface of the substrate, respectively, and a wiring is led out from the connection terminal and is connected to the terminals of the power supply, GND, input signal and data I/O, respectively, and the semiconductor wafer 1 is flip-chip-connected to the substrate 5 via an anisotropic conductive material; (c) the connected semiconductor wafer 1 and substrate 5 are subjected to burn-in; and (d) the semiconductor wafer 1 and substrate 5 are diced, and the wiring on the surface of the substrate 5 is cut out to be electrically independent and also to be divided into respective chips 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a burn-in compatible semiconductor module, and more particularly, to a method of manufacturing a burn-in compatible semiconductor module capable of performing burn-in in a wafer state.

[0002]

2. Description of the Related Art Usually, when a semiconductor module is manufactured,
As a screening step, a temperature and a voltage stress are applied to accelerate the stress, and burn-in is performed to remove an initial defective product. Generally, burn-in methods include individual burn-in in which a semiconductor chip or module is mounted on a socket or the like, and wafer burn-in performed in units of wafers. A method for safely and simultaneously burning in a large number of undivided chips when applying burn-in by applying an electrical stress in the state of a semiconductor wafer has been proposed in, for example, JP-A-6-69298.

According to this method, as shown in FIG.
In the semiconductor wafer 21, wiring is drawn out from the bonding pads of a large number of undivided chips 22 formed on the semiconductor wafer 21 to the separation region 23, and the same kind of drawn out wiring is connected together, Are connected to the burn-in power supply terminal 24, the GND terminal 25, the input terminal 26, and the input / output terminal 27, respectively.
By applying a burn-in voltage to each chip 22 at the same time, burn-in can be performed.

Further, another burn-in method for applying an electric stress in a semiconductor wafer state is disclosed in, for example, Japanese Patent Laid-Open No. 6-5 / 1994.
677 discloses this. According to this method, as shown in FIG. 4, passive elements such as a resistor 33, a capacitor 34, and a fuse 35 are formed in a region other than the undivided chips 32 on the semiconductor wafer 31, and each passive element is By being formed on the power supply dedicated pad 36 via the wiring, an external probe is brought into mechanical contact with the power supply dedicated pad 36, thereby simultaneously burning in each chip 32 at the wafer stage. Becomes possible. Further, even if a short circuit occurs between the power supplies in the chip 32, the fuse 35 operates and the current supply to the chip 32 is cut off. Further, by inserting a capacitor between the power supply terminal and the GND terminal or connecting a resistor to a power supply dedicated pad, a safety function acting as a chip protection element in burn-in can be ensured.

[0005]

However, in the wafer shown in FIG. 3, since wiring for burn-in is provided on the separation region 23 of each chip 22, the separation region 2 is usually used.
There is a problem in that it is difficult to install an electrical property evaluation element for process management in wafer manufacturing, which is installed on the wafer 3.
Further, when this electric characteristic evaluation element is formed in the chip 22, there is a problem that the chip size becomes large and the chip unit price rises.

In the wafer shown in FIG. 4, burn-in is performed by mechanically bringing the probe into contact with the power supply dedicated pad 36. However, since the power supply dedicated pad 36 is small, it is caused by bias application. As a result, thermal expansion of the wafer occurs, and the probe used is displaced from the power supply dedicated pad 36 to cause a contact failure.
Further, it is necessary to secure an area where the passive elements are provided on the wafer and a wiring area between each chip and the passive elements, which causes a problem that the number of chips per wafer is reduced.

[0007]

According to the present invention, (a)
Forming a protruding electrode on an electrode of each undivided chip formed on the semiconductor wafer; and (b) connecting a terminal on the surface of the substrate at a position facing the protruding electrode; A GND terminal, an input signal terminal, and a data input / output terminal are formed, and an external connection terminal is formed on the back surface of the substrate. (C) burn-in the flip-chip connected semiconductor wafer and the substrate; and (d) burn-in the flip-chip connected semiconductor wafer and the substrate. Dicing the chip-connected semiconductor wafer and substrate,
A method for manufacturing a corresponding semiconductor module, comprising the steps of: cutting a wiring formed on the surface of the substrate so as to be electrically independent and dividing the chip into respective chips.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, first, in step (a), protruding electrodes are formed on the electrodes of each undivided chip formed on a semiconductor wafer. The semiconductor wafer used in the present invention is not particularly limited as long as it is normally used for a semiconductor memory device. For example, an elemental semiconductor such as silicon and germanium, and GaAs
and compound semiconductors such as s, InGaAs, and ZnSe. Among them, silicon is preferred. The chips formed on the semiconductor wafer in this step are in an undivided state, for example, those formed by combining semiconductor elements such as transistors and capacitors, circuits, insulating films, wiring layers, and the like, or so-called multilayers. Various types such as those having a wiring structure are exemplified. The electrodes arranged on the surface of the chip may be electrodes constituting a semiconductor element, wirings, electrodes connected to the wirings, or the like.

The protruding electrodes formed on the electrodes are usually called bumps. For example, solder, gold, platinum, silver,
It can be formed of a metal such as copper and aluminum; a high melting point metal such as titanium, tantalum and tungsten alone or an alloy. Among them, a material that can easily form a ball by electric discharge and heat treatment, specifically, gold, solder, and the like are preferable. The thickness of the protruding electrode is not particularly limited, and may be, for example, about 20 to 40 μm.

[0010] The protruding electrode can be formed by a known method. For example, in the case of a gold bump, a ball bonding method is generally used, and a spherical ball formed at the tip of the gold wire is pressed onto the semiconductor electrode portion by sparking the gold wire using a wire bonder. In this state, there is a method in which ultrasonic vibration is applied to the capillary to generate a crack in the gold wire portion near the ball, and then the gold wire is pulled up to form a bump.
In the case of a solder bump, a method of selectively forming solder plating on a semiconductor electrode by a plating method or the like, and then performing a heat treatment exceeding the melting point of solder to melt the solder plating and form a ball bump by surface tension. Is mentioned. Furthermore, there is a method in which the above conductive material is formed in a film shape on the entire surface of a semiconductor wafer by sputtering, vapor deposition, or the like, and the conductive material is patterned by photolithography and etching steps so as to be disposed on the chip electrodes. Can be

In the step (b), first, connection terminals are provided at positions facing the protruding electrodes on the surface of the substrate, and power supply terminals, GND terminals, input signal terminals, and data input / output terminals are provided at peripheral regions on the surface of the substrate. Then, external connection terminals are respectively formed on the back surface of the substrate.

The substrate used in the present invention is not particularly limited as long as it is an insulating substrate, and examples thereof include glass, resins such as glass fiber reinforced epoxy resin, epoxy resin and polyimide resin, and ceramics. . Among them, glass fiber reinforced epoxy resin, polyimide resin, ceramic and the like are preferable. Although the thickness of the substrate is not particularly limited, for example, about 0.2 to 1.6 mm is appropriate. The substrate is connected to a position on the surface corresponding to the protruding electrode so that when the semiconductor wafer is bonded to the substrate, the substrate can be connected to the protruding electrode formed on the chip of the semiconductor wafer. Form terminals. In addition, a power supply terminal, a GND terminal, an input signal terminal, and a data input / output terminal are formed in a peripheral area where the chip is not formed on the surface. These connection terminals, power supply terminals, GND terminals, input signal terminals, and data input / output terminals can be formed individually or at the same time, for example, by using the above-described conductive material by the same method as the formation of the bumps. it can.

Further, external connection terminals are formed on the back surface of the substrate. The external connection terminal can also be formed by the same method as described above. At this time, the external connection terminal is electrically connected to the connection terminal on the front side via a wiring in the substrate and a through hole for electrically connecting both surfaces by plating or a through hole in which a conductive paste is embedded. For example, in the case of a glass fiber reinforced epoxy resin-based substrate, H
In general, a method is generally used in which a through hole is provided by NC processing or laser processing, a through hole for electrically connecting both surfaces is formed by plating, and a front and back pattern is formed by a photolithography and etching process. The external connection terminal is a power supply terminal, a GND terminal,
It is formed at the same time as the formation of the input signal terminal and the data input / output terminal, and is electrically connected to the connection terminal on the front surface via a through hole by wiring in the substrate.

Next, wires are drawn out from the connection terminals and connected to a power supply terminal, a GND terminal, an input signal terminal, and a data input / output terminal. The drawing of the wiring and the connection between each terminal and the wiring can be performed by a method known in the art. The wiring drawn from the connection terminal of each undivided chip may be individually connected to a power supply terminal, a GND terminal, an input signal terminal, and a data input / output terminal, or may be of the same type (wiring connected to the same terminal). ) May be connected in common and connected to the power supply terminal, the GND terminal, the input signal terminal, and the data input / output terminal, or, for example, only the wiring connected to at least one of the terminals, for example, the data input / output terminal Only the wiring to be performed may be independently pulled out from the undivided chip and connected to this terminal.

Further, passive elements such as resistors, capacitors, and fuses may be formed or mounted after or before forming predetermined terminals on the front or back surface of the substrate, or after flip-chip connection described later. . These passive elements are
It may be formed in any area of the substrate, or may be formed on either the front surface or the back surface, but may be formed on the peripheral region of the substrate and / or on the back surface side (the side on which the external connection terminals are formed) of the substrate. Is preferred. These passive elements include, for example, a fuse connected to a wiring connected to the power supply terminal, a resistor or a capacitor connected between the power supply terminal and the GND terminal, and the like.

Further, in the above step, the step (a)
The steps (b) and (b) need not be performed in the above order, and may be performed in the order of the step (b) and the step (a), or the sub-steps in the step (b) may be performed in any order. Alternatively, step (a) may be performed between any of the sub-steps. Further, the semiconductor wafer and the substrate are flip-chip connected via an anisotropic conductive material. The flip-chip connection needs to be performed so that the protruding electrode of the semiconductor wafer is connected to the connection terminal on the substrate surface side. This connection can be performed by various methods such as solder reflow, ultrasonic bonding, and a method using an anisotropic conductive material.
A method using an anisotropic conductive material such as an anisotropic conductive sheet or an anisotropic conductive paste is preferable. Anisotropic conductive material
Any known products that are commercially available for use in this field can be used without particular limitation.

In the step (c), the connected semiconductor wafer and substrate are burned in. Burn-in method is
This can be performed by applying a predetermined voltage to each terminal. For example, a dynamic burn-in method for operating a burn-in circuit formed in a semiconductor substrate by applying a recommended operating voltage of a semiconductor device between a power supply and GND and applying an input signal from an input signal terminal,
A static burn-in method in which a recommended operating voltage is applied between NDs may be used. If a circuit that returns the burn-in state of the semiconductor device as an electrical signal to the input / output terminals is formed inside the semiconductor device, monitoring of the signal enables judgment of good and defective semiconductors by a burn-in test. Becomes Note that a protruding electrode may be formed on the external connection terminal after the step (c) and before a step (d) described later. The protruding electrodes can be formed individually or simultaneously using the conductive material as described above by a method similar to the method of forming the bumps.

In the step (d), the semiconductor wafer to which the substrate is bonded is diced together with the substrate. The dicing method is not particularly limited, and can be performed by various methods such as a scribe method, a laser method, and a dicing saw method. Thus, the wiring formed on the surface of the substrate can be cut to make it electrically independent and divided into chips. After the step (c) and before a step (d) to be described later, instead of forming a protruding electrode on the external connection terminal, a solder ball or the like is connected to the external connection terminal after dicing to connect the external electrode. CSP may be used.

Hereinafter, a method for manufacturing a semiconductor module according to the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, a plurality of chips 2 are formed, and bumps (not shown) are formed by electroplating or electroless plating on pad electrodes 3 formed on an undivided silicon wafer 1. A projection electrode 4 is formed.

Next, as shown in FIG. 1B, connection terminals 6 are formed at positions facing the bumps 4 on another substrate 5 and wirings inside the substrate 5 are formed on the opposite surface of the substrate 5. To form the external contact terminals 11 electrically connected to the bumps 4. Wirings are drawn out from each connection terminal 6, wirings of the same type are connected together, and wirings connected together are a power supply terminal 7, a GND terminal provided around the substrate 5, as shown in FIG. 8, the input signal terminal 9 and the data input / output terminal 10 are respectively extended and connected. In addition, only the wiring for data input / output signals on the substrate 5 is independently pulled out for each undivided chip, and connected to the data input / output terminal 10 provided around the substrate 5, so that the undivided chips on the wafer can be By the simultaneous burn-in, the judgment signals of the non-defective product and the defective product are obtained independently. Further, a fuse 14 is formed on a wiring connected to the power supply terminal 7 on the substrate 5, and a passive component land 13 such as a capacitor is formed between the power supply terminal 7 and the GND terminal 8. By mounting passive components with solder, safety can be ensured.

Next, as shown in FIG. 1C, the substrate 5 and the silicon wafer 1 are flip-chip connected via an anisotropic conductive sheet or an anisotropic conductive paste 12. At this time, the alignment is performed so that the connection terminals 6 formed on the substrate 5 and the bumps 4 formed on the silicon wafer 1 are connected. By using an anisotropic conductive sheet or an anisotropic conductive paste 12, electrical connection and adhesion can be performed at the same time, so that the process can be simplified.

Subsequently, a burn-in voltage is applied between the power supply terminals 7 and 8, a control signal is applied to the input terminal 9, and the data input / output terminal 10 performs data control to perform burn-in for each wafer. Thereafter, as shown in FIG. 1D, dicing of the chip 2
The common wiring between them is cut and divided into individual semiconductor modules 15 that are electrically independent. As a result, only non-defective products in the burn-in test can be taken out.

[0023]

According to the present invention, by performing steps (a) to (d), it is not necessary to install a burn-in wiring and a circuit dedicated to burn-in on a semiconductor wafer, so that the number of chips installed per wafer is reduced. Without causing the wafer burn-in. In addition, since it is not necessary to install a burn-in wiring in a conventional isolation area on a wafer or to secure an area for installing passive components, an existing semiconductor wafer can be used as it is, thereby reducing manufacturing costs. Becomes possible.

Further, the connection between the substrate on which the wiring and the like are formed and the semiconductor wafer is performed by using an anisotropic conductive material.
Since both electrical connection and bonding can be performed at the same time, the process can be simplified. Furthermore, since the semiconductor module is formed by dicing after wafer burn-in, the subsequent assembly process is not required, and the process can be simplified, and individual modules can be manufactured, and the manufacturing cost can be reduced. it can.

In the case where a protruding electrode is formed on the external connection terminal after the step (c) and before the step (d),
The semiconductor module can be used as a small package using the protruding electrodes as external electrodes. Further, among the wirings drawn out from the connection terminals, when the same kind of wiring is commonly connected to the power supply terminal, the GND terminal, the input signal terminal, and the data input / output terminal, the wiring area occupied on the substrate is reduced. Therefore, the substrate size can be flexibly handled in response to the reduction in the size of the semiconductor chip.

On the other hand, when the wiring connected to the data input / output terminal among the wirings drawn out from the connection terminal is drawn out independently for each undivided chip and connected to the data input / output terminal, the wiring on the wafer Non-defective / defective judgment signals can be obtained independently from each of the undivided chips.
It is possible to select only good products based on the quality determination result after the individual pieces are divided.

In the case where at least one of a fuse and a land on which a passive element can be mounted between the power supply terminal and the GND terminal is further formed on the substrate, a wire connected to the power supply terminal may be used at the time of burn-in. Chip can be avoided, and safety can be ensured. Furthermore, when the substrate is made of glass fiber reinforced epoxy resin, a low-cost module can be manufactured. When this semiconductor module is mounted on a motherboard made of glass fiber reinforced epoxy resin, which is common in the consumer field, a basic method is used. The thermal expansion coefficients between the plate members are substantially equal, the reliability of the joint is ensured, and a highly reliable semiconductor device can be manufactured. When the substrate is made of a polyimide resin, the thickness of the substrate can be reduced to about 0.1 mm or less, so that a thinner module can be manufactured. further,
When the substrate is made of ceramic, the coefficient of thermal expansion is substantially equal to that of the semiconductor chip, so that warpage of the module alone can be reduced, and a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional process drawing of a main part for describing an embodiment of a method for manufacturing a semiconductor module of the present invention.

FIG. 2 is a schematic plan view of a semiconductor module for describing an embodiment of a method for manufacturing a semiconductor module of the present invention.

FIG. 3 is a schematic plan view of a semiconductor wafer for explaining a conventional burn-in method for applying an electrical stress in a semiconductor wafer state.

FIG. 4 is a schematic plan view of a conventional semiconductor wafer compatible with wafer burn-in on which passive components are mounted in a semiconductor wafer state.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Undivided chip 3 Electrode 4 Projection electrode (bump) 5 Substrate 6 Connection terminal 7 Power supply terminal 8 GND terminal 9 Input / output terminal 10 Data input / output terminal 11 External connection terminal 12 Anisotropic conductive adhesive sheet or anisotropic Conductive paste 13 Passive component land 14 Fuse

Claims (6)

[Claims] 1. A step of (a) forming a protruding electrode on an electrode of each undivided chip formed on a semiconductor wafer; and (b) forming a connection terminal on a surface of a substrate at a position facing the protruding electrode. And a power supply terminal, a GND terminal, an input signal terminal, and a data input / output terminal in the peripheral region, and an external connection terminal formed on the back surface of the substrate.
A step of connecting to the D terminal, the input signal terminal, and the data input / output terminal, respectively, and flip-chip connecting the semiconductor wafer and the substrate via an anisotropic conductive material; and (c) the flip-chip connected semiconductor wafer and substrate. And (d) dicing the flip-chip connected semiconductor wafer and the substrate to cut the wiring formed on the surface of the substrate to make them electrically independent and to divide each chip. And a method for manufacturing a corresponding semiconductor module. 2. After step (c) and before step (d),
2. A protruding electrode is further formed on the external connection terminal.
The method described in. 3. The method according to claim 1, wherein in the step (b), of the wirings drawn out from the connection terminals, the same kind of wirings are commonly connected and connected to a power supply terminal, a GND terminal, an input signal terminal, and a data input / output terminal. 3. The method according to 2. 4. In the step (b), among wirings drawn out from the connection terminals, wirings connected to the data input / output terminals are drawn out independently for each undivided chip and connected to the data input / output terminals. The method according to claim 1. 5. The method according to claim 1, wherein, in the step (b), at least one of a fuse and a land on which a passive element can be mounted between the power supply terminal and the GND terminal is further formed on the substrate. Item 5. The method according to any one of Items 1 to 4. 6. The substrate is made of a glass fiber reinforced epoxy resin,
The method according to any one of claims 1 to 5, comprising a polyimide resin or a ceramic.