KR100769204B1 - Semiconductor Package and Manufacture Method The Same - Google Patents

Abstract

An object of the present invention is to provide a semiconductor package manufacturing method that can simplify the semiconductor package manufacturing process using an anisotropic conductive film and a semiconductor package using the same.

 The present invention provides a chip assembly having an anisotropic conductive film attached to a circuit surface of a chip and a conductive bump attached to a metal pad of the circuit surface; The substrate includes a substrate having a hole or a groove formed in a predetermined position, and the first chip assembly is disposed in the hole or the groove of the substrate, and the second chip assembly having the same configuration as that of the first chip assembly is positioned on the upper surface of the substrate. Thus, the semiconductor package is electrically connected to the substrate.

Semiconductor, Package, Anisotropic, Conductive Film, Wafer

Description

Semiconductor Package and Manufacture Method The Same

1 is a schematic cross-sectional view showing a semiconductor package containing a conventional anisotropic conductive film.

Fig. 2 is a sectional view showing the first preferred embodiment of the semiconductor package according to the present invention.

3 is a flow chart briefly showing a method of manufacturing a semiconductor package according to the present invention.

4 and 5 are cross-sectional views illustrating a chip assembly mounted on a smart card as a second embodiment of the semiconductor package according to the present invention;

6 is a sectional view showing a third embodiment of a semiconductor package according to the present invention;

** Description of symbols for the main parts of the drawing **

1: semiconductor chip 3: anisotropic conductive film

4: conductive bump 50: substraight

10: first chip assembly 11: second chip assembly

20: picker 30: adhesive film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package in which two or more semiconductor chips are laminated using the same, which is easy to attach a semiconductor chip to a substrate.

In general, semiconductor packages include resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages. Such semiconductor packages are classified into insert type and surface mount technology (SMT) type according to the mounting method. Representative types include insert type dual in-line package (DIP) and pin grid array (PGA). Typical examples of the mounting type include QFP (Quad Flat Package), PLCC (Plastic Leaded Chip Carrier), CLCC (Ceramic Leaded Chip Carrier), and BGA (Ball Grid Array).

Such a semiconductor package is being developed to be manufactured in a light and simple manner, and also strives to improve productivity by simplifying the process.

In the conventional semiconductor package manufacturing process, when attaching a semiconductor chip to a substrate, there is a process of interposing an anisotropic conductive film between the substrate and the semiconductor chip. The anisotropic conductive film (ACF) is a polymer coated on a plurality of conductive particles having a diameter of approximately 5 μm inside a thin adhesive resin of several tens to several tens of micro units, and is subjected to thermal pressure. When the polymer coated on the conductive kernel is broken by the pressure, the conductive kernels are connected to each other to maintain an energized state.

1 illustrates a semiconductor chip 1 and a substrate 5 attached by the anisotropic conductive film 3.

The semiconductor chip 1 is formed by forming an integrated circuit on one surface of a wafer, grinding the wafer into units and cutting the wafer in units of units so that the surface on which the integrated circuit is installed is connected to the connection pad 5a of the substrate 5. Direct contact.

In more detail, the substrate 5 is a member that serves as a bridge through which an electric signal input and output to and from the semiconductor chip 1 is adopted, which generally employs a printed circuit board (PCB) or a lead frame. ) Will be attached to the motherboard and installed in a packaged state.

The semiconductor chip 1, which is completed in a chip state after backgrinding and sawing the wafer during the semiconductor package manufacturing process, is attached to the substrate 5 as described above. The conductive bumps 4 are interposed so that the connection pads 5a of the substrate and the metal pads 1a of the semiconductor chip 1 can be easily connected to each other.

The conductive bump 4 is a metal material that is melted at a high temperature and solidified at a low temperature. The conductive bump 4 is usually formed of gold (Au), aluminum (Al), copper (Cu), or the like to the metal pad 1a of the semiconductor chip 1. Attach. As the conductive bumps 4 attached as described above come into contact with the connection pads 5a of the substrate 5, the semiconductor chip 1 and the substrate 5 are energized and pass through the reflow chamber in this state. (4) is to be fused.

Conventionally, the semiconductor chip is attached to only the conductive bumps 4 as described above. However, the conductive bumps 4 are separated from the substrate 5 or the semiconductor chip 1 in the process, and thus problems of connection reliability often occur.

In order to prevent this, an anisotropic conductive film (3) is interposed between the semiconductor chip 1 and the substrate 5 provided with the conductive bumps 4 to simultaneously improve electrical connection reliability and adhesion. .

However, although the connection reliability and adhesion between the semiconductor chip 1 and the substrate 5 can be improved by using the anisotropic conductive film 3, the anisotropic conductive film 3 is cut and interposed between the substrates 5. In addition, a number of processes, such as removing the cover of the anisotropic conductive film 3, are added, resulting in problems such as low productivity.

In addition, when two or more semiconductor chips are stacked, a separate encapsulant is used in the related art, so that an anisotropic conductive film and an encapsulant are used in combination, thereby increasing the complexity of the stacked semiconductor package.

The present invention devised to solve the above problems of the prior art can simplify the semiconductor package manufacturing process using an anisotropic conductive film, and to provide a semiconductor package that is easy to stack two or more semiconductor chips. .

In order to achieve the above object, the present invention provides a chip assembly having an anisotropic conductive film attached to a circuit surface of a chip and a conductive bump attached to a metal pad of the circuit surface; The substrate includes a substrate having a hole or a groove formed in a predetermined position, and the first chip assembly is disposed in the hole or the groove of the substrate, and the second chip assembly having the same configuration as that of the first chip assembly is positioned on the upper surface of the substrate. Thus, the semiconductor package is electrically connected to the substrate.

The structure and method of this invention are demonstrated in detail, referring an accompanying drawing. For reference, prior art description of the present invention will refer to the same reference numerals as they are for the parts consistent with the prior art in order to avoid duplication of description.

2 is a cross-sectional view showing a preferred embodiment of a semiconductor package according to the present invention.

Referring to the drawings, a groove 51 is formed in a central portion and a substrate 50 having a thin film pattern formed of a conductive material, a first chip assembly 10 seated and connected to the groove 51, and It consists of a second chip assembly 11 seated on the surface of the substrate 50.

The substrate 50 provides a space on which the semiconductor chips 10a and 11a can be seated, and at the same time, the substrate 50 may serve as an intermediary that can be transmitted to the motherboard by inputting and outputting an electrical signal of the semiconductor chip. The substrate 50 may be used in various ways including a lead frame, but in the present invention, it is preferable to employ a printed circuit board.

The chip assemblies 10 and 11 mounted on the substrate 50 may include semiconductor chips 10a and 11a, conductive bumps 4 attached to circuit surfaces of the semiconductor chips 10a and 11a, It consists of the anisotropic conductive material 3 attached to the whole circuit surface of a semiconductor chip including the said conductive bump 4.

The anisotropic conductive material 3 can be used both an anisotropic conductive film or an anisotropic conductive paste. In the following examples, an anisotropic conductive film 3 was used.

An integrated circuit is formed on one surface of the semiconductor chips 10a and 11a. Such integrated circuits require terminals to be connected to external terminals, which are commonly referred to as metal pads 10b and 11b. The metal pads 10b and 11b are arranged in a line at the edge of the chip or in a line at the center of the chip.

Conductive bumps 4 are provided on the chips 10a and 11a to improve adhesion and secure connection reliability when they are seated on the substrate 50. The conductive bumps 4 are metal grains, which are melted at high temperatures and fixed at low temperatures, and then adhered to the metal pads 10b and 11b of the semiconductor chips 10a and 11a. It is mounted on and attached through the reflow process.

Since the conductive bumps 4 have their own thickness, a space is generated between the substrate 50 surface and the circuit surface of the chip. Since foreign matter may penetrate the space, the encapsulant is filled to prevent foreign matter from penetrating.

In the present invention, the anisotropic conductive film 3 is used as a substitute for the encapsulant, and is attached to the back surface of the semiconductor chip before mounting on the substrate 50. In this manner, the chip assemblies 10 and 11 made of the chips 10a and 11a, the conductive bumps 4, and the anisotropic conductive film 3 are prepared in advance, and then mounted on the substrate 50.

Such a chip assembly 10 (11) is manufactured at the wafer stage. The method is schematically described according to the flowchart of the semiconductor package manufacturing method shown in FIG.

In the first step 100, the conductive bumps 4 are attached to the metal pads 10b and 11b of the wafer circuit surface.

In the second step 200, the anisotropic conductive material 3 is attached to the circuit surface of the wafer. The anisotropic conductive material includes both an anisotropic conductive film and an anisotropic conductive paste.

In the third step 300, the wafer to which the anisotropic conductive material 3 is attached is backgrinded.

In the fourth step 400, the wafers to which the conductive bumps 4 and the anisotropic conductive material 3 are attached are sawed for each chip size to separate the chip assemblies.

The fifth step 500 and the sixth step 600 will be described later.

Characteristic of the present invention is that when the anisotropic conductive film is attached to the wafer in the manufacturing process of the first chip assembly and the second chip assembly is preferably attached at about 80 ℃ ~ 100 ℃.

Through the above process, the chip assembly applied to the present invention is completed.

Referring again to FIG. 2, the first chip assembly 10 manufactured by the method is inserted into a groove 51 of the substrate 50, and a conductive surface is formed on the bottom surface of the groove 51 of the substrate 50. Bond pads 54, which are part of the traces, are provided, and the bond pads 54 are installed at positions corresponding to the bump positions of the chip assembly 10. The bond pads 54 of the substrate 50 and the metal pads 10b of the chip assembly 10 are connected by conductive bumps 4 interposed therebetween and each along the conductive traces of the substrate 50. It leads to the conductive ball 40.

The conductive ball 40 is used as a terminal for connecting to the motherboard when the semiconductor package is mounted on the motherboard or the like.

After the first chip assembly 10 is inserted into the groove 51 of the substrate 50, the second chip assembly 11 is installed on the upper surface of the substrate 50. When the first chip assembly 10 is positioned on the substrate 50, the height of the first chip assembly 10 may be slightly higher than that of the substrate 50. Although the top surface of the chip 10a is higher than the surface of the substrate 50, compensation is possible in the semiconductor package according to the present invention.

As described above, even if the first chip assembly 10 is higher than the surface of the substrate 50, the second chip assembly 11 may be easily stacked as follows. Since the anisotropic conductive film 3 is attached to the circuit surface of the chip and the conductive bumps 4 are attached to the metal pads 11b, the second chip assembly 11 also supports the second chip assembly 11. When the thermocompression bonding is applied to the surface of the 50, the first chip 10a is inserted into the anisotropic conductive film of the paste unless the upper surface of the first chip 10a is higher than the chip circuit surface of the second chip assembly 11. This digging allows the height to remain constant even after mounting up to the second chip assembly 11.                     

At this time, the area of the second chip 11a is larger than that of the first chip 10a. As shown in the figure, the conductive bumps 4 of the second chip 11a are connected to the surface of the substrate 50, so that the distance between the conductive bumps 4 of the second chip 11a is equal to that of the first chip 10a. It must be larger than the length to be easily connected.

Due to the above configuration, even if the surface of the first chip 10a is higher than the surface of the substrate 50, there is no problem in stacking the second chip 11a. In addition, metal grains distributed in the anisotropic conductive film 3 are connected by pressure to strengthen the connection force between the conductive bump 4 and the substrate 50.

4 is a cross-sectional view showing a second embodiment of a semiconductor package according to the present invention.

The semiconductor package of the above embodiment shows a smart card 500, and shows a form in which a semiconductor chip is embedded in the smart card 500. Smart card 500 is a card used as an electronic payment means, a user recognition means is a card that has a semiconductor chip inside to store information and exchange signals.

As shown in the figure, when the semiconductor chip 10a according to the present invention is mounted on the smart card 500, the chip assembly 10 shown in the first embodiment is placed in the hole 510 (see Fig. 5) of the smart card. Insert it. The bottom surface of the hole 510 of the smart card 500 is provided with a bond pad 54 drawn out so that the bond pads 54 are attached to the metal pad 10b of the semiconductor chip 10a. It is attached to and connected with the circuit installed inside the smart card 500.

5 is a cross-sectional view illustrating a form of applying pressure when mounting the semiconductor chip assembly 10 of the smart card 500.

As described above, in order to secure the conductivity of the anisotropic conductive film 3, the chip assembly 10 should be applied with a predetermined pressure after inserting the chip assembly 10 into the hole or the groove 510 of the smart card 500. Referring to the drawings, the picker 20, which picks up the chip assembly 10, presses the chip assembly 10 at a predetermined pressure while inserting the chip assembly 10 into the smart card 500.

6 is a cross-sectional view showing a third embodiment of the semiconductor package according to the present invention.

As shown in the figure, two semiconductor chip assemblies 10 are located in the grooves 51 of the substrate 50, and the number of the chip assemblies 10 may be increased.

Both of the two chip assemblies 10 are chip assemblies according to the present invention to which the anisotropic conductive film 3 is attached, and are formed higher than the surface of the substrate, similarly to the first chip assembly in the first embodiment of FIG. There is no problem in laminating by the anisotropic conductive film of the second chip assembly located on the upper side.

By configuring as described above, three or more semiconductor chips can also be easily stacked.

A manufacturing process of the semiconductor chip will be briefly described. As described with reference to FIG. 3, the method of manufacturing a semiconductor package according to the present invention may be described in detail.

A first step (100) of attaching the conductive bumps (4) to each metal pad (10b) (11b) of the wafer circuit surface;

A second step 200 of attaching the anisotropic conductive material 3 to the circuit surface of the wafer;                     

A third step (300) of backgrinding the wafer to which the anisotropic conductive material (3) is attached;

A fourth step (400) of individualizing the chip assembly by sawing the wafer to which the conductive bumps (4) and the anisotropic conductive material (3) are attached for each chip size as described above;

A fifth step (500) of inserting one or more first chip assemblies into the holes or grooves of the substrate (50) and attaching them with predetermined heat and pressure;

And a sixth step (600) of positioning the second chip assembly to cover the holes or grooves of the substrate (50) and attaching it with a predetermined heat and pressure.

As described above, two or three or more semiconductor chips can be easily stacked through the embodiment of the present invention, and the circuit surface of the chip can be protected without using an encapsulant, and an anisotropic conductive material is used. It is possible to secure the conductive reliability along with the adhesion.

In addition, even if the surface of the chip assembly inserted into the hole or groove of the substrate is higher than the surface of the substrate, the anisotropic conductive material in the form of a paste or film compensates for a predetermined height, thereby reducing the possibility of product defects.

Claims (6)

A chip assembly having an anisotropic conductive film attached to a circuit surface of the chip, and a conductive bump attached to a metal pad of the circuit surface; It includes a substrate formed with a hole or groove in a predetermined place, Wherein the first chip assembly is disposed in the hole or groove of the substrate, and the second chip assembly having the same configuration as the first chip assembly is positioned on the upper surface of the substrate to be electrically connected to the substrate. The method of claim 1, And the second chip assembly has a larger area than the hole or groove of the substrate. The method of claim 1, And at least two first chip assemblies are located in the holes or grooves. The method of claim 1, And the height of the first chip assembly is higher than the height of the substrate. The method of claim 1, And a conductive pattern corresponding to a metal pad of the semiconductor chip is formed on a bottom surface of the hole or groove of the substrate. Attaching a conductive bump to each metal pad of the wafer; Attaching the anisotropic conductive material to the circuit surface of the wafer, but attaching the anisotropic conductive material at 80 ° C. to 100 ° C .; Backgrinding the wafer to which the anisotropic conductive material is attached; Individualizing the chip assembly by sawing the wafer to which the conductive bumps and the anisotropic conductive material are attached as described above; Inserting one or more first chip assemblies into holes or grooves of the substrate and attaching the substrate with predetermined heat and pressure; Positioning the second chip assembly to cover the holes or grooves of the substrate, and attaching the second chip assembly with a predetermined heat and pressure.

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