JPS634635A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS634635A JPS634635A JP61146904A JP14690486A JPS634635A JP S634635 A JPS634635 A JP S634635A JP 61146904 A JP61146904 A JP 61146904A JP 14690486 A JP14690486 A JP 14690486A JP S634635 A JPS634635 A JP S634635A
- Authority
- JP
- Japan
- Prior art keywords
- thermal expansion
- substrate
- expansion coefficient
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 9
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 6
- 238000010030 laminating Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005382 thermal cycling Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、制御された熱膨張係数を有する半導体素子に
関し、特に、熱膨張係数の異なる基板にフェイスダウン
ボンディングによりボンディングするフリップチップの
熱膨張係数差をマツチングさせる技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a controlled coefficient of thermal expansion, and in particular to a semiconductor device having a controlled coefficient of thermal expansion, and particularly to a semiconductor device having a controlled coefficient of thermal expansion. This article relates to technology for matching coefficient differences.
基板に半導体素子（チップ）をボンディングする技術の
一つＫいわゆるＣＣＢ（コンドロールドコラップスボン
ディング）方式がある。これは周知のように、チップの
ボンディングパッドにバンプ（突起電極）を取り付け、
セルファラインの配線基板に接合する技術であり、かか
るＣＣＢ方式により接合されるチップは７リノプチツプ
とよばれている。かかるＣＣＢ方式において、例えば基
板（ペース）にアルミナセラミックにより構成されたも
のを使用し、当該基板（配線基板）上に、Ｓｉチップを
接合する場合、Ｓｉチップの熱膨張係数が一般に３．５
Ｘ１０−６℃−１であるのに対し、上記アルミナ基板の
熱膨張係数は一般に６に１０−’℃−１であり、これら
のものの熱膨張係数の不整合により、ストレスがこれら
チップと基板とを接合しているＣＣＢ接合部にがかり、
該接合部が熱サイクル時破断するということが起こる。One of the techniques for bonding semiconductor elements (chips) to a substrate is the so-called CCB (Contoured Collapse Bonding) method. As is well known, this involves attaching bumps (protruding electrodes) to the bonding pads of the chip.
This is a technique for bonding to a Selfaline wiring board, and chips bonded by this CCB method are called 7Linop chips. In such a CCB method, for example, when a substrate (paste) made of alumina ceramic is used and a Si chip is bonded to the substrate (wiring board), the thermal expansion coefficient of the Si chip is generally 3.5.
x10-6°C-1, whereas the thermal expansion coefficient of the alumina substrate is generally 6 to 10-'°C-1, and due to the mismatch in the thermal expansion coefficients of these materials, stress can be applied to these chips and the substrate. The CCB joint that joins the
It happens that the joint breaks during thermal cycling.
なお、フリップチップに関し述べた文献の例として１９
８０年１月１５日（株）工業調査会発行ｒＩＣ化実装技
術」ｐ８１があり、また、半導体装置部材の熱膨張係数
差に基づ（不良について述べた特許の例として、特開昭
５６−１０４４５８号公報などがある。In addition, as an example of literature that describes flip chips, 19
January 15, 1980, Published by Kogyo Kenkyukai Co., Ltd., IC Mounting Technology, p. 81. There are publications such as No. 104458.
本発明はかかる従来技術の有する欠点を解消し、異なる
熱膨張係数をもつ基板に接合するような場合に、当該基
板の熱膨張係数にマツチングさせることのできる半導体
素子を提供することを目的とし、当該マツチングにより
基板との接合部に破断を生ぜず、したがって、半導体装
置の信頼性を向上させることのできる技術を提供するこ
とを目的とする。The present invention aims to eliminate the drawbacks of the prior art and provide a semiconductor element that can match the thermal expansion coefficient of the substrate when bonded to a substrate having a different thermal expansion coefficient, It is an object of the present invention to provide a technique that does not cause breakage at the bonded portion with the substrate due to the matching, thereby improving the reliability of the semiconductor device.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本ＩＩにおいて開示される発明のうち代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in Book II is as follows.
すなわち、本発明は、半導体素子の接続端子反対側面に
、該素子とは熱膨張係数の異なる、例えば、アルミナ蓄
板のごときものを貼着することにより、当該素子の熱膨
張係数が全体で変ってくるという原理を利用したもので
ある。That is, in the present invention, the thermal expansion coefficient of the semiconductor element can be changed as a whole by attaching something, such as an alumina storage plate, which has a different coefficient of thermal expansion from that of the element to the side opposite to the connection terminal of the semiconductor element. This is based on the principle that
このように、半導体素子の熱膨張係数に変化を与えるこ
とにより、基体との熱膨張係数をマツチングさせること
ができ、これＫよりＣＣＢ接合部ノ、〔実施例〕
−ｌ ・
−次に、本発明を、図面に示す実施例に基づいて説明す
る。In this way, by changing the thermal expansion coefficient of the semiconductor element, it is possible to match the thermal expansion coefficient with that of the substrate. The invention will be described based on embodiments shown in the drawings.
第１図は本発明による半導体素子の全体断面図で、第２
図は同要部断面図、第３図は同全体斜視図である。FIG. 1 is an overall sectional view of a semiconductor device according to the present invention, and FIG.
The figure is a sectional view of the main part, and FIG. 3 is a perspective view of the whole.
これら図にて、１は半導体素子、２はその接続端子、３
は熱膨張制御板、４は接着剤である。In these figures, 1 is a semiconductor element, 2 is its connection terminal, and 3
is a thermal expansion control plate, and 4 is an adhesive.
半導体素子１は次のように構成されている。すなわち、
半導体デバイス５表面が熱酸化膜６により被覆され、該
熱酸化膜６を介して、Ａ４電極配線７が敷設され、さら
に、その上に設けられたデバイス表面保護膜８にあけら
れた電極用窓にＣｒ膜９．Ｃｕ膜１０およびＡｕ膜１１
よりなる多層金属層で電極下地（層）を形成し、Ｓロー
ルｂを用いて半球状のバンプ（突起を極）１２を形成し
ている。The semiconductor element 1 is constructed as follows. That is,
The surface of the semiconductor device 5 is covered with a thermal oxide film 6, an A4 electrode wiring 7 is laid through the thermal oxide film 6, and an electrode window is formed in the device surface protection film 8 provided on top of the A4 electrode wiring 7. Cr film 9. Cu film 10 and Au film 11
An electrode base (layer) is formed from a multilayer metal layer, and semispherical bumps (protrusions as poles) 12 are formed using an S roll b.
該半導体素子１０半田突起電極１２を有する面の反対側
の面に熱膨張制御板３を、接着剤４により貼着する。A thermal expansion control plate 3 is adhered to the surface of the semiconductor element 10 opposite to the surface having the solder protrusion electrodes 12 using an adhesive 4.
半導体素子（チップ）１は、例えばシリコン単結晶基板
から成り、周知の技術によってこのチッ、プ内には多数
の回路素子が形成され、１つの回路機能が与えられてい
る。回路素子の具体例は、例えばＭＯＳ）ランジスタか
ら成り、これらの回路素子によって、例えば論理回路お
よびメモリの回路機能が形成されている。A semiconductor element (chip) 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A concrete example of a circuit element is, for example, a transistor (MOS), and these circuit elements form, for example, a logic circuit and a memory circuit function.
熱膨張制御板３は、当該半導体素子１の熱膨張係数の異
なるものより構成される。The thermal expansion control plate 3 is made of a material having a different coefficient of thermal expansion from that of the semiconductor element 1 .
半導体素子が上記で例示されるように、シリコン（Ｓｉ
）チップの場合の熱膨張係数（α、とする）は−般に３
．５Ｘ１０−’℃−１であり、例えば、これよりも熱膨
張係数の大なるもの罠より熱膨張制御板３を構成する。As the semiconductor device is exemplified above, silicon (Si
) In the case of a chip, the coefficient of thermal expansion (α) is - generally 3
．． For example, the thermal expansion control plate 3 is constructed from a material having a larger coefficient of thermal expansion than this.
基板がアルミナ基板である場合、その熱膨張係数は一般
に６ Ｘ １０−’℃−１であり、熱膨張制御板３をこ
のアルミナ基板と同様の材料により構成してもよい。When the substrate is an alumina substrate, its coefficient of thermal expansion is generally 6 x 10-'°C-1, and the thermal expansion control plate 3 may be made of the same material as the alumina substrate.
半導体素子１０表面にかかる熱膨張制御板３を貼合せる
ことにより、その全体の熱膨張係数に変化を与えること
ができる。By pasting the thermal expansion control plate 3 on the surface of the semiconductor element 10, the overall coefficient of thermal expansion can be changed.
今、半導体素子１の厚みを１．とし、熱膨張制御板３の
熱膨張係数をα２、その厚さをｔ！と丁ると、これらが
合わさった場合の全体の熱膨張係数（α）は次の式で示
される。Now, the thickness of the semiconductor element 1 is set to 1. The thermal expansion coefficient of the thermal expansion control plate 3 is α2, and its thickness is t! Then, the overall coefficient of thermal expansion (α) when these are combined is expressed by the following formula.
１、＋１゜
したがって、上記αが基板の熱膨張係数に近づくように
、熱膨張制御板３を貼着すればよい。1.+1° Therefore, the thermal expansion control plate 3 may be attached so that the above α approaches the coefficient of thermal expansion of the substrate.
熱膨張制御板３の半導体素子１への貼着は、接着剤によ
るほか、共晶合金法、半田付法、ガラス溶融法などによ
っても可能である。The thermal expansion control plate 3 can be attached to the semiconductor element 1 not only by using an adhesive but also by a eutectic alloy method, a soldering method, a glass melting method, or the like.
本発明においては、熱膨張制御板に代えて、同様の機能
をはた丁のであれば、例えば、半導体素子のα、よりも
大なる熱膨張係数を有するような材料例えば石英を、半
導体素子１の接続端子２反対側面に、拡散接合により積
層してもよい。In the present invention, instead of the thermal expansion control plate, a material having a coefficient of thermal expansion larger than α of the semiconductor element, such as quartz, can be used for the semiconductor element 1. It may be laminated on the opposite side of the connection terminal 2 by diffusion bonding.
半導体素子１はチップに限定されずウェハであってもよ
く、第４図に示すごとく、ウェハ１３の第５図は、上記
のごとき、本発明によるコンドロールドアルファフリッ
プチップを使用した半導体装置の要部断面図を示し、同
図に示すように、基板１５上罠、コンドロールドアルフ
ァフリップチップ１６が固着され、基板（ペース）１５
の裏面から垂設された外部ビン１７と突起電極２とは導
体部１８により導通されている。ベース１５上には、キ
ャップ１９が、接合材料２０により取付けられている。The semiconductor element 1 is not limited to a chip but may be a wafer, and as shown in FIG. 4, the wafer 13 in FIG. A sectional view of the main part is shown, and as shown in the same figure, the trap on the substrate 15, the Chondrald Alpha flip chip 16 is fixed, and the substrate (paste) 15 is fixed.
The external vial 17 which is vertically disposed from the back surface of the housing and the protruding electrode 2 are electrically connected to each other through a conductor portion 18 . A cap 19 is attached onto the base 15 with a bonding material 20.
該半導体装置は、同図に示すようにビングリッドアレイ
タイプに構成され、方形の多層セラミックパッケージ１
５の裏面に基盤目様に多数の外部ピン１７がロー付げさ
れている。As shown in the figure, the semiconductor device is configured in a bin grid array type, and includes a rectangular multilayer ceramic package 1.
A large number of external pins 17 are soldered to the back surface of the base plate 5 in the same manner as the base plate.
本発明によれば、半導体素子１の接続端子２の反対面に
熱膨張制御層３を積層することにより、その熱膨張係数
を変化させることができ、熱膨張制御層３の構成材料や
その厚みなど前記式に基づき選定することにより、基板
１５に接合するような場合、基板１５と半導体素子ｌと
の熱膨張係数・遠を減少させることができ、突起電極２
の破断を・、ｊ）
、−・防止することができる。According to the present invention, by laminating the thermal expansion control layer 3 on the opposite surface of the connection terminal 2 of the semiconductor element 1, the thermal expansion coefficient can be changed, and the constituent material of the thermal expansion control layer 3 and its thickness can be changed. By selecting based on the above formula, when bonding to the substrate 15, it is possible to reduce the coefficient of thermal expansion between the substrate 15 and the semiconductor element l, and the protruding electrode 2
It is possible to prevent breakage of .,j),-.
以上本発明者によっ【なされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
本発明による半導体素子はコンドロールドアルファフリ
ップチップとして、熱膨張係数差をマツチングさせる場
合に各種適用できる。The semiconductor device according to the present invention can be used in various applications as a Chondral Alpha flip chip to match differences in thermal expansion coefficients.
本励において開示される発明のうち代表的なものにより
て得られろ効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this study is as follows.
本発明によればＣＣＢ接続部の熱サイクルや基板の反り
などによる破断が防止され、高信頼性の半導体装置を得
ることができ、大型チップのＣＣＤ化をも可能ならしめ
ることができた。According to the present invention, it is possible to prevent breakage of the CCB connection portion due to thermal cycling or warping of the substrate, to obtain a highly reliable semiconductor device, and to make it possible to convert a large chip into a CCD.
第１図は本発明の実施例を示す半導体素子の全体断面図
、
・ノ
、／第２図は同要部断面図、
第３図は同全体斜視図、
第４図は本発明の他の実施例を示す斜視図、第５図は本
発明による半導体素子を用いて成る半導体装置の一例断
面図である。
１・・・半導体素子、２・・・接続端子、３・・・熱膨
張制御板、４・・・接着剤、５・・・半導体デバイス、
６・・・熱酸化膜、７・・・ｌ電極配線、８・・・デバ
イス表面保護膜、９−・Ｃｒ膜、１Ｏ−Ｃｕ膜、１ｌ−
Ａｕ膜、１２・・・半田突起電極、１３・・・ウエノ・
、１４・・・熱膨張制御層、１５・・・基板、１６・・
・コンドロールドアルファフリップチップ、１７・・・
外部ピン、１８・・・導体部、１９・・・キャップ、２
０・・・接合材料。
代理人 弁理士 小 川 勝 男−１、第 １
図
第 ２ 図
、３
第 ３ 図
第 ４ 図Fig. 1 is an overall cross-sectional view of a semiconductor device showing an embodiment of the present invention, /Fig. FIG. 5 is a perspective view showing an embodiment, and a sectional view of an example of a semiconductor device using a semiconductor element according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... Connection terminal, 3... Thermal expansion control board, 4... Adhesive, 5... Semiconductor device,
6... Thermal oxide film, 7... l electrode wiring, 8... device surface protective film, 9-.Cr film, 1O-Cu film, 1l-
Au film, 12... Solder protrusion electrode, 13... Ueno...
, 14... thermal expansion control layer, 15... substrate, 16...
・Condrold Alpha Flip Chip, 17...
External pin, 18... Conductor part, 19... Cap, 2
0...Joining material. Agent: Patent Attorney Katsuo Ogawa-1, 1st
Figures 2, 3, 3, and 4
Claims (1)
によりフェイスダウンボンディングして接続する方式の
半導体素子において、該半導体素子の前記接続端子の反
対側面に、該半導体素子の熱膨張係数とは異なる熱膨張
係数を有する熱膨張制御層を積層して、当該素子と当該
基体との熱膨張係数差を調整して成ることを特徴とする
制御された熱膨張係数を有する半導体素子。 ２、基体がセラミック基板で、半導体素子がシリコン単
結晶基板より成るフリップチップで、当該素子の接続端
子がボンディングパッドに半球状の半田突起電極を取り
付けて成り、制御層の積層が当該接続端子の反対側面に
当該素子の熱膨張係数より大なる熱膨張係数を有する制
御板を接着剤により貼着して成る、特許請求の範囲第１
項記載の半導体素子。[Scope of Claims] 1. In a semiconductor element connected to a substrate having different coefficients of thermal expansion by face-down bonding through connection terminals thereof, the semiconductor element A device having a controlled thermal expansion coefficient, characterized in that it is formed by stacking thermal expansion control layers having a thermal expansion coefficient different from that of the element and the substrate to adjust the difference in thermal expansion coefficient between the element and the substrate. semiconductor element. 2. A flip chip whose base body is a ceramic substrate and whose semiconductor element is a silicon single crystal substrate.The connection terminal of the element is formed by attaching a hemispherical solder protrusion electrode to a bonding pad, and the laminated control layer is attached to the connection terminal. Claim 1, wherein a control plate having a thermal expansion coefficient larger than that of the element is adhered to the opposite side with an adhesive.
Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61146904A JPS634635A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61146904A JPS634635A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS634635A true JPS634635A (en) | 1988-01-09 |
Family
ID=15418199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61146904A Pending JPS634635A (en) | 1986-06-25 | 1986-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS634635A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH077042A (en) * | 1992-12-08 | 1995-01-10 | Hughes Aircraft Co | Thermally matched integrated circuit chip device and manufcture thereof |
-
1986
- 1986-06-25 JP JP61146904A patent/JPS634635A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH077042A (en) * | 1992-12-08 | 1995-01-10 | Hughes Aircraft Co | Thermally matched integrated circuit chip device and manufcture thereof |
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