JP2010232702A - Laminated semiconductor device - Google Patents

Laminated semiconductor device Download PDF

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JP2010232702A
JP2010232702A JP2010163162A JP2010163162A JP2010232702A JP 2010232702 A JP2010232702 A JP 2010232702A JP 2010163162 A JP2010163162 A JP 2010163162A JP 2010163162 A JP2010163162 A JP 2010163162A JP 2010232702 A JP2010232702 A JP 2010232702A
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relay
pad
conductive layer
semiconductor elements
wiring board
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Naohisa Okumura
尚久 奥村
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Toshiba Corp
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To facilitate connection between a semiconductor element and a wiring board after applying a conductive layer to connection between electrode pads, when laminating a plurality of semiconductor elements over a wiring board in multiple steps. <P>SOLUTION: On the wiring board 2, the plurality of semiconductor elements 9 are laminated in a step-like form to expose electrode pads 16 by directing pad arrangement sides in the same direction. The electrode pads 16 of the plurality of semiconductor elements 9 are connected to one another by a conductive layer 19. The conductive layer 19 includes a first conductive layer 191 for linearly connecting the electrode pads 16 possessed by the plurality of semiconductor elements 9, and a second conductive layer 193 wired on an exposure surface equivalent to a step surface of a step part of the plurality of semiconductor elements 9. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は積層型半導体装置に関する。   The present invention relates to a stacked semiconductor device.

ＮＡＮＤ型フラッシュメモリ等を内蔵するメモリカード（半導体メモリカード）は、急速に小型化と高容量化が進められている。小型化されたメモリカードを実現するために、メモリ素子やコントローラ素子等の半導体素子は配線基板上に積層して搭載されている。半導体素子の電極パッドはワイヤボンディングを適用して配線基板の接続パッドと電気的に接続される。さらに、メモリカードの高容量化を図るために、メモリ素子自体も配線基板上に多段に積層されるようになってきている。   A memory card (semiconductor memory card) incorporating a NAND flash memory or the like has been rapidly reduced in size and capacity. In order to realize a miniaturized memory card, semiconductor elements such as a memory element and a controller element are stacked and mounted on a wiring board. The electrode pads of the semiconductor element are electrically connected to the connection pads of the wiring board by applying wire bonding. Furthermore, in order to increase the capacity of memory cards, memory elements themselves are also stacked in multiple stages on a wiring board.

メモリ素子の積層数は増加傾向にあり、メモリカードの記憶容量に応じて４段、さらには８段もしくはそれ以上に積層することが検討されている。半導体素子（メモリ素子）を多段に積層するためには１個当りの素子厚を薄くする必要がある。素子厚を薄くした半導体素子にワイヤボンディングを適用した場合、ボンディング荷重で半導体素子がダメージを受けるおそれがある。そこで、複数の半導体素子を電極パッドが露出するように階段状に積層すると共に、複数の半導体素子の電極パッド間や電極パッドと配線基板の接続パッドとの間を導電層で電気的に接続することが検討されている（特許文献１，２参照）。   The number of stacked memory elements tends to increase, and it has been studied to stack four layers or even eight or more depending on the storage capacity of the memory card. In order to stack semiconductor elements (memory elements) in multiple stages, it is necessary to reduce the thickness of each element. When wire bonding is applied to a semiconductor element having a thin element thickness, the semiconductor element may be damaged by a bonding load. Accordingly, a plurality of semiconductor elements are stacked in a stepped manner so that the electrode pads are exposed, and the electrode pads of the plurality of semiconductor elements and the electrode pads and the connection pads of the wiring board are electrically connected by a conductive layer. (See Patent Documents 1 and 2).

複数の半導体素子を単に階段状に積層した場合には、半導体素子の積層数が増加するにつれて階段方向の長さが長くなり、配線基板に対する半導体素子の占有面積が増加する。このような点に対して、例えば半導体素子を階段状に積層した複数の素子群をスペーサ層等を介して積み重ねたり、あるいは階段方向を反対方向に向けた複数の素子群を積み重ねることによって、配線基板に対する半導体素子の占有面積を低減することができる。ただし、この場合には素子群内の電極パッド間の接続には導電層が適用できるものの、上方に位置する素子群の半導体素子と配線基板とを導電層で接続することが困難となる。   When a plurality of semiconductor elements are simply stacked in a staircase pattern, the length in the staircase direction increases as the number of stacked semiconductor elements increases, and the area occupied by the semiconductor elements with respect to the wiring board increases. For such a point, for example, by stacking a plurality of element groups in which semiconductor elements are stacked stepwise via a spacer layer or the like, or by stacking a plurality of element groups in which the staircase directions are opposite to each other, wiring is performed. The area occupied by the semiconductor element with respect to the substrate can be reduced. However, in this case, although a conductive layer can be applied to the connection between the electrode pads in the element group, it is difficult to connect the semiconductor element of the element group located above and the wiring board with the conductive layer.

また、電気特性や信号特性が等しい電極パッドについては、階段状に積層された複数の半導体素子の電極パッドを導電層で順に接続することができる。しかし、チップセレクト等を行う制御信号用の電極パッドに関しては、制御信号に応じて複数の半導体素子の電極パッドを個々に配線基板の接続パッドと接続しなければならない場合がある。半導体素子と配線基板との接続に金属ワイヤを用いた場合、金属ワイヤに入線角度を付けることによって、複数の半導体素子の電極パッドを個々に配線基板の接続パッドと接続することができるものの、単に導電層を適用しただけでは接続パッドとの接続が困難になる。   For electrode pads having the same electrical characteristics and signal characteristics, the electrode pads of a plurality of semiconductor elements stacked in a staircase pattern can be sequentially connected by a conductive layer. However, with respect to the control signal electrode pads for performing chip selection or the like, there are cases where the electrode pads of a plurality of semiconductor elements must be individually connected to the connection pads of the wiring board in accordance with the control signals. When a metal wire is used for the connection between the semiconductor element and the wiring board, the electrode pads of a plurality of semiconductor elements can be individually connected to the connection pads of the wiring board by giving an angle of entry to the metal wire. The connection with the connection pad becomes difficult only by applying the conductive layer.

特開２００４−０６３５６９号公報JP 2004-063569 A 特開２００５−３０２７６３号公報JP 2005-302763 A

本発明の目的は、複数の半導体素子を配線基板上に多段に積層するにあたって、複数の半導体素子の電極パッド間の接続に導電層を適用した上で、半導体素子の電極パッドと配線基板の接続パッドとの間を容易に接続することを可能にした積層型半導体装置を提供することにある。   The object of the present invention is to apply a conductive layer to the connection between the electrode pads of the plurality of semiconductor elements and to connect the electrode pads of the semiconductor element to the wiring board when laminating the plurality of semiconductor elements on the wiring substrate in multiple stages. It is an object of the present invention to provide a stacked semiconductor device that can be easily connected to pads.

本発明の態様に係る積層型半導体装置は、接続パッドを有する配線基板と、外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記配線基板上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている素子群と、少なくとも前記複数の半導体素子の前記電極パッド間を接続する導電層と、前記素子群を封止するように、前記配線基板上に形成された封止樹脂層とを具備し、前記導電層は、前記複数の半導体素子が有する前記電極パッドを直線状に接続する第１導電層と、前記複数の半導体素子の階段部分の段面に相当する露出面上を引き回されている第２導電層とを有することを特徴としている。   A stacked semiconductor device according to an aspect of the present invention includes a wiring board having connection pads and a plurality of semiconductor elements having electrode pads arranged along one side of the outer shape, and the plurality of semiconductor elements are on the wiring board. A group of elements stacked in a staircase pattern so that the pad array sides are directed in the same direction and the electrode pads are exposed; a conductive layer connecting at least the electrode pads of the plurality of semiconductor elements; and the element A sealing resin layer formed on the wiring substrate so as to seal a group, and the conductive layer is a first conductive layer that linearly connects the electrode pads of the plurality of semiconductor elements. And a second conductive layer routed on an exposed surface corresponding to the step surface of the stepped portions of the plurality of semiconductor elements.

本発明の態様に係る積層型半導体装置によれば、複数の半導体素子の階段部分における露出面上で導電層を引き回しているため、半導体素子と配線基板とを容易に接続することができる。   According to the stacked semiconductor device of the aspect of the present invention, since the conductive layer is routed on the exposed surface in the stepped portion of the plurality of semiconductor elements, the semiconductor elements and the wiring board can be easily connected.

本発明の実施形態による積層型半導体装置を示す平面図である。1 is a plan view showing a stacked semiconductor device according to an embodiment of the present invention. 図１のＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line of FIG. 図１に示す積層型半導体装置における半導体素子の電極パッド間の接続構造を示す平面図である。FIG. 2 is a plan view showing a connection structure between electrode pads of a semiconductor element in the stacked semiconductor device shown in FIG. 1. 図３の平面図に対応する断面図である。It is sectional drawing corresponding to the top view of FIG. 図１に示す積層型半導体装置の製造工程を示す図であって、中継素子となる半導体ウエハ上に複数のメモリ素子を積層する段階を示す平面図である。FIG. 2 is a diagram showing a manufacturing process of the stacked semiconductor device shown in FIG. 1, and is a plan view showing a step of stacking a plurality of memory elements on a semiconductor wafer serving as a relay element. 図５に示す半導体ウエハの１個の中継素子に相当する素子領域を示す平面図である。FIG. 6 is a plan view showing an element region corresponding to one relay element of the semiconductor wafer shown in FIG. 5. 図６の断面を示す図である。It is a figure which shows the cross section of FIG.

以下、本発明を実施するための形態について、図面を参照して説明する。図１および図２は本発明の実施形態による半導体記憶装置（積層型半導体装置）の構成を示す図であって、図１は半導体記憶装置（積層型半導体装置）の平面図、図２はそのＡ−Ａ線に沿った断面図（長辺方向に切断した断面図）である。これらの図に示される半導体記憶装置（積層型半導体装置）１は半導体メモリカードを構成しており、例えば半導体記憶装置１のみでマイクロＳＤTM規格のメモリカード（マイクロＳＤTMカード）として使用されるものである。すなわち、半導体記憶装置１はケースレスのメモリカードである。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. 1 and 2 are diagrams showing a configuration of a semiconductor memory device (stacked semiconductor device) according to an embodiment of the present invention. FIG. 1 is a plan view of the semiconductor memory device (stacked semiconductor device), and FIG. It is sectional drawing (sectional drawing cut | disconnected in the long side direction) along the AA line. The semiconductor memory device (laminated semiconductor device) 1 shown in these drawings constitutes a semiconductor memory card, and is used as a micro SD ™ standard memory card (micro SD ™ card) only by the semiconductor memory device 1, for example. Is. That is, the semiconductor memory device 1 is a caseless memory card.

半導体記憶装置１は素子実装基板と端子形成基板とを兼ねる配線基板２を備えている。配線基板２は、例えば絶縁性樹脂基板の内部や表面に配線網を設けたものであり、具体的にはガラス−エポキシ樹脂やＢＴ樹脂（ビスマレイミド・トリアジン樹脂）等を使用したプリント配線板が適用される。配線基板２は、端子形成面となる第１の主面２ａと、素子実装面となる第２の主面２ｂとを備えている。   The semiconductor memory device 1 includes a wiring board 2 that serves as both an element mounting board and a terminal forming board. The wiring board 2 is, for example, a wiring network provided inside or on the surface of an insulating resin board. Specifically, a printed wiring board using glass-epoxy resin, BT resin (bismaleimide / triazine resin) or the like is used. Applied. The wiring board 2 includes a first main surface 2a serving as a terminal formation surface and a second main surface 2b serving as an element mounting surface.

配線基板２は概略矩形状の外形を有している。配線基板２の一方の短辺３Ａはメモリカードをカードスロットに挿入する際の先端部に相当する。他方の短辺３Ｂはメモリカードの後方部に相当する。配線基板２の一方の長辺４Ａは直線形状であるのに対し、他方の長辺４Ｂはメモリカードの前後や表裏の向きを示す切り欠き部やくびれ部を有している。さらに、配線基板２の各角部は曲線状（Ｒ形状）とされている。   The wiring board 2 has a substantially rectangular outer shape. One short side 3 </ b> A of the wiring board 2 corresponds to a tip portion when the memory card is inserted into the card slot. The other short side 3B corresponds to the rear part of the memory card. One long side 4A of the wiring board 2 has a linear shape, while the other long side 4B has a notch portion or a constricted portion indicating the front and back direction of the memory card and the front and back sides. Further, each corner of the wiring board 2 is curved (R shape).

配線基板２の第１の主面２ａには、メモリカードの入出力端子となる外部接続端子５が形成されている。外部接続端子５は電解めっき等により形成された金属層で構成されている。なお、配線基板２の第１の主面２ａはメモリカードの表面に相当する。さらに、配線基板２の第１の主面２ａには、外部接続端子５の形成領域を除く領域に第１の配線網（図示せず）が設けられている。第１の配線網は例えばメモリカードのテストパッドを有している。第１の主面２ａに設けられた第１の配線網は、絶縁性の接着シールや接着テープ等を用いた絶縁層（図示せず）で覆われている。   On the first main surface 2 a of the wiring board 2, external connection terminals 5 that are input / output terminals of the memory card are formed. The external connection terminal 5 is composed of a metal layer formed by electrolytic plating or the like. The first main surface 2a of the wiring board 2 corresponds to the surface of the memory card. Furthermore, a first wiring network (not shown) is provided on the first main surface 2 a of the wiring board 2 in a region excluding the region where the external connection terminals 5 are formed. The first wiring network has, for example, a memory card test pad. The first wiring network provided on the first main surface 2a is covered with an insulating layer (not shown) using an insulating adhesive seal, adhesive tape, or the like.

配線基板２の第２の主面２ｂは、素子搭載部６と接続パッド７を含む第２の配線網とを備えている。なお、配線基板２の第２の主面２ｂはメモリカードの裏面に対応するものである。接続パッド７を有する第２の配線網は、配線基板２の図示を省略した内部配線（スルーホール等）を介して、外部接続端子５や第１の配線網と電気的に接続されている。接続パッド７は、短辺３Ａに沿った第１のパッド領域８Ａと長辺４Ａに沿った第２のパッド領域８Ｂのそれぞれに配置されている。   The second main surface 2 b of the wiring board 2 includes an element mounting portion 6 and a second wiring network including the connection pads 7. The second main surface 2b of the wiring board 2 corresponds to the back surface of the memory card. The second wiring network having the connection pads 7 is electrically connected to the external connection terminals 5 and the first wiring network through internal wiring (such as through holes) (not shown) of the wiring board 2. The connection pad 7 is disposed in each of the first pad region 8A along the short side 3A and the second pad region 8B along the long side 4A.

配線基板２の素子搭載部６には、複数のメモリ素子（半導体素子）９が搭載されている。メモリ素子９としてはＮＡＮＤ型フラッシュメモリ等の半導体メモリ素子が用いられる。メモリ素子９上にはコントローラ素子（半導体素子）１０が積層されている。コントローラ素子１０は、複数のメモリ素子９からデータの書き込みや読み出しを行うメモリ素子を選択（チップセレクト）し、選択したメモリ素子９へのデータを書き込み、また選択したメモリ素子９に記憶されたデータの読み出し等を行う。   A plurality of memory elements (semiconductor elements) 9 are mounted on the element mounting portion 6 of the wiring board 2. As the memory element 9, a semiconductor memory element such as a NAND flash memory is used. A controller element (semiconductor element) 10 is stacked on the memory element 9. The controller element 10 selects (chip selects) a memory element that writes and reads data from a plurality of memory elements 9, writes data to the selected memory element 9, and stores data stored in the selected memory element 9 Is read out.

複数のメモリ素子９は第１ないし第４の素子群（メモリ素子群）１１、１２、１３、１４に分けられており、これら素子群１１〜１４は配線基板２の第１の主面２ａ上に積み重ねられている。各素子群１１〜１４はそれぞれ４個のメモリ素子９と１個の中継素子１５とで構成されている。具体的には、第１の素子群１１は配線基板２の素子搭載部６上に配置された第１の中継素子１５Ａを有している。第１の素子群１１を構成する４個のメモリ素子９は第１の中継素子１５Ａ上に順に階段状に積層されている。   The plurality of memory elements 9 are divided into first to fourth element groups (memory element groups) 11, 12, 13, and 14. These element groups 11 to 14 are arranged on the first main surface 2 a of the wiring board 2. Are stacked. Each of the element groups 11 to 14 is composed of four memory elements 9 and one relay element 15. Specifically, the first element group 11 includes a first relay element 15 </ b> A disposed on the element mounting portion 6 of the wiring board 2. The four memory elements 9 constituting the first element group 11 are sequentially stacked on the first relay element 15A.

各メモリ素子９は矩形状の同一形状を有し、それぞれ電極パッド１６を備えている。電極パッド１６はメモリ素子９の外形の一辺、具体的には一方の短辺に沿って配列されている。このように、メモリ素子９は短辺片側パッド構造を有している。同様に、中継素子１５は、その外形の一辺（具体的には一方の短辺）に沿って配列された中継パッド１７を備え、メモリ素子９より若干大きい矩形状の外形を有している。中継素子１５としては素子構造を持たない中継用半導体素子（Ｓｉインターボーザ等）が用いられ、これは通常の半導体素子（Ｓｉ素子等）と同様な工程で作製される。   Each memory element 9 has the same rectangular shape and includes an electrode pad 16. The electrode pads 16 are arranged along one side of the outer shape of the memory element 9, specifically, one short side. Thus, the memory element 9 has a short side one-side pad structure. Similarly, the relay element 15 includes a relay pad 17 arranged along one side (specifically, one short side) of the outer shape, and has a rectangular outer shape slightly larger than the memory element 9. As the relay element 15, a relay semiconductor element (Si interposer or the like) having no element structure is used, which is manufactured in the same process as a normal semiconductor element (Si element or the like).

第１の中継素子１５Ａは、中継パッド１７が形成された電極形成面を上方に向けて、配線基板２の素子搭載部６上に接着層（図示せず）を介して接着されている。接着層には一般的なポリイミド樹脂、エポキシ樹脂、アクリル樹脂等を主成分とするダイアタッチフィルム（接着剤フィルム）が用いられる。メモリ素子９の接着層も同様である。第１の中継素子１５Ａはパッド配列辺（一方の短辺）を配線基板２の短辺３Ａに向けて配置されている。すなわち、第１の中継素子１５Ａは中継パッド１７が配線基板２の第１のパッド領域８Ａの近傍に位置するように配置されている。   The first relay element 15A is bonded to the element mounting portion 6 of the wiring board 2 via an adhesive layer (not shown) with the electrode forming surface on which the relay pad 17 is formed facing upward. A die attach film (adhesive film) mainly composed of a general polyimide resin, epoxy resin, acrylic resin or the like is used for the adhesive layer. The same applies to the adhesive layer of the memory element 9. The first relay element 15 </ b> A is arranged with the pad arrangement side (one short side) facing the short side 3 </ b> A of the wiring board 2. That is, the first relay element 15 </ b> A is arranged so that the relay pad 17 is positioned in the vicinity of the first pad region 8 </ b> A of the wiring board 2.

第１の素子群１１を構成する４個のメモリ素子９のうち、最下段のメモリ素子９は電極パッド１６が形成された電極形成面を上方に向け、かつ中継パッド１７が露出するように短辺を長辺方向にずらして、第１の中継素子１５Ａ上に接着層（図示せず）を介して接着されている。同様に、残りの３個のメモリ素子９は下段側のメモリ素子９の電極パッド１６が露出するように短辺を長辺方向にずらして、最下段のメモリ素子９上にそれぞれ接着層（図示せず）を介して順に接着されている。   Of the four memory elements 9 constituting the first element group 11, the lowermost memory element 9 is short so that the electrode formation surface on which the electrode pad 16 is formed faces upward and the relay pad 17 is exposed. The side is shifted in the long side direction and bonded to the first relay element 15A via an adhesive layer (not shown). Similarly, the remaining three memory elements 9 are shifted in the long side direction so that the electrode pads 16 of the lower memory element 9 are exposed, and adhesive layers (see FIG. (Not shown).

このように、４個のメモリ素子９はそれぞれ第１の中継素子１５Ａとパッド配列辺を同方向に向け、かつ長辺を揃えると共に、中継パッド１７および下段側のメモリ素子９の電極パッド１６が露出するように短辺を長辺方向にずらして、第１の中継素子１５Ａ上に順に階段状に積層されている。すなわち、第１の中継素子１５Ａと４個のメモリ素子９は中継パッド１７および各電極パッド１６が露出するように階段状に積層されている。従って、第１の中継素子１５Ａの中継パッド１７と４個のメモリ素子９の各電極パッド１６はいずれも上方に向けて露出させた状態で、第１のパッド領域８Ａの近傍に位置している。   As described above, the four memory elements 9 have the pad array sides in the same direction as the first relay elements 15A and the long sides are aligned, and the relay pads 17 and the electrode pads 16 of the memory elements 9 on the lower side are provided. The short side is shifted in the long side direction so as to be exposed, and the first relay element 15A is sequentially stacked in a stepped manner. That is, the first relay element 15A and the four memory elements 9 are stacked stepwise so that the relay pad 17 and each electrode pad 16 are exposed. Accordingly, the relay pad 17 of the first relay element 15A and the electrode pads 16 of the four memory elements 9 are both exposed in the upward direction and are located in the vicinity of the first pad region 8A. .

第１の素子群１２上には第２ないし第４の素子群１２〜１４が順に積み重ねられている。第２ないし第４の素子群１２〜１４はそれぞれ第１の素子群１２と同様な構成を有している。第２の素子群１２は、第１の素子群１１の最上段のメモリ素子９上に接着層（図示せず）を介して接着された第２の中継素子１５Ｂと、その上に順に階段状に積層された４個のメモリ素子９とを備えている。第２の素子群１２を構成する４個のメモリ素子９は、第１の素子群１１を構成するメモリ素子９と同様な構成を有している。第２の中継素子１５Ｂも第１の中継素子１５Ａと同様な構成を有している。第３および第４の素子群１３、１４を構成するメモリ素子９および中継素子１５Ｃ、１５Ｄも同様である。   On the first element group 12, second to fourth element groups 12 to 14 are sequentially stacked. The second to fourth element groups 12 to 14 each have the same configuration as the first element group 12. The second element group 12 includes a second relay element 15B bonded to the uppermost memory element 9 of the first element group 11 via an adhesive layer (not shown), and a stepped shape in that order. And four memory elements 9 stacked on each other. The four memory elements 9 constituting the second element group 12 have the same configuration as the memory elements 9 constituting the first element group 11. The second relay element 15B has the same configuration as the first relay element 15A. The same applies to the memory element 9 and the relay elements 15C and 15D constituting the third and fourth element groups 13 and 14.

第２の素子群１２を構成する第２の中継素子１５Ｂと４個のメモリ素子９は、それぞれパッド配列辺を同方向に向け、かつ長辺方向を揃えると共に、中継パッド１７および下段側のメモリ素子９の電極パッド１６が露出するように、短辺を長辺方向にずらして階段状に積層されている。第２の素子群１２は第１の素子群１１と階段方向を同方向に向けて積層されている。従って、第２の中継素子１５Ｂの中継パッド１７と４個のメモリ素子９の各電極パッド１６は、第１の素子群１１と同様に、いずれも上方に向けて露出させた状態で、第１のパッド領域８Ａの近傍に位置している。   The second relay element 15B and the four memory elements 9 constituting the second element group 12 have the pad array side directed in the same direction and the long side direction aligned, and the relay pad 17 and the lower side memory. The short side is shifted in the long side direction so that the electrode pad 16 of the element 9 is exposed, and the layers are stacked stepwise. The second element group 12 is laminated with the first element group 11 so that the staircase direction is the same direction. Accordingly, the relay pad 17 of the second relay element 15B and the electrode pads 16 of the four memory elements 9 are both exposed upward in the same manner as the first element group 11 in the first element group 11. Is located in the vicinity of the pad region 8A.

同様に、第３の素子群１３は第２の素子群１２上に配置された第３の中継素子１５Ｃと４個のメモリ素子９とで構成されており、第４の素子群１４は第３の素子群１３上に配置された第４の中継素子１５Ｄと４個のメモリ素子９とで構成されている。第３および第４の中継素子１５Ｃ、１５Ｄは、下段側の素子群１２、１３の最上段のメモリ素子９上に接着層（図示せず）を介して接着されている。第３および第４の素子群１３、１４を構成する中継素子１５Ｃ、１５Ｄと４個のメモリ素子９は、それぞれパッド配列辺を同方向に向け、かつ中継パッド１７および下段側のメモリ素子９の電極パッド１６が露出するように、第１の素子群１１と同方向に向けて階段状に積層されている。   Similarly, the third element group 13 includes a third relay element 15C disposed on the second element group 12 and four memory elements 9, and the fourth element group 14 includes The fourth relay element 15D and the four memory elements 9 are arranged on the element group 13. The third and fourth relay elements 15C and 15D are bonded to the uppermost memory element 9 of the lower element groups 12 and 13 via an adhesive layer (not shown). The relay elements 15C and 15D and the four memory elements 9 constituting the third and fourth element groups 13 and 14 are respectively arranged so that the pad arrangement sides are directed in the same direction, and the relay pad 17 and the lower memory element 9 The electrode pads 16 are stacked stepwise in the same direction as the first element group 11 so that the electrode pads 16 are exposed.

第２ないし第４の素子群１２〜１４は第１の素子群１１と素子配置や積層構造を揃えて階段状に積層されている。このように、第１ないし第４の素子群１１〜１４はそれぞれ階段方向、素子配置および積層構造が同一となるように構成されている。従って、各中継パッド１７や電極パッド１６を露出させた上で、配線基板２に対する中継素子１５およびメモリ素子９の占有面積の増大を抑制している。すなわち、半導体記憶装置１の素子占有面積は、各素子群１１〜１４の配線基板２に対する投影面積を揃えているため、１つの素子群の占有面積（実際には中継素子１５の面積）となる。従って、複数のメモリ素子９を具備する半導体記憶装置１の小型化を図ることが可能となる。   The second to fourth element groups 12 to 14 are stacked stepwise with the first element group 11 in the same element arrangement and stacked structure. As described above, the first to fourth element groups 11 to 14 are configured to have the same step direction, element arrangement, and stacked structure. Therefore, after the relay pads 17 and the electrode pads 16 are exposed, an increase in the area occupied by the relay elements 15 and the memory elements 9 with respect to the wiring board 2 is suppressed. That is, the element occupation area of the semiconductor memory device 1 is the same as the area occupied by one element group (actually the area of the relay element 15) because the projected areas of the element groups 11 to 14 on the wiring board 2 are uniform. . Accordingly, it is possible to reduce the size of the semiconductor memory device 1 including the plurality of memory elements 9.

ただし、第２ないし第４の素子群１２〜１４を構成する第２ないし第４の中継素子１５Ｂ〜１５Ｄは、それぞれ下段側の素子群１１〜１３からはみ出して配置されることになる。従って、第２ないし第４の中継素子１５Ｂ〜１５Ｄの各中継パッド１７の下方は中空状態となる。すなわち、第２ないし第４の中継素子１５Ｂ〜１５Ｄはオーバーハング構造となる。そこで、第２ないし第４の中継素子１５Ｂ〜１５Ｄのオーバーハング部分の下方（中空部）には、それぞれ絶縁樹脂１８が充填されている。絶縁樹脂１８としては、エポキシ樹脂、ポリイミド樹脂、シリコーン樹脂等の熱硬化性樹脂が用いられる。絶縁樹脂１８は配線基板２上に各素子群１１〜１４を配置した後に液状樹脂を充填し、これを硬化させることにより形成される。液状樹脂はディスペンサ等を用いて注入される。   However, the 2nd thru | or 4th relay elements 15B-15D which comprise the 2nd thru | or 4th element groups 12-14 will be arrange | positioned and protruded from the element groups 11-13 of the lower stage side, respectively. Therefore, the lower part of each relay pad 17 of the second to fourth relay elements 15B to 15D is in a hollow state. That is, the second to fourth relay elements 15B to 15D have an overhang structure. Therefore, the insulating resin 18 is filled below (over the hollow portions) of the overhang portions of the second to fourth relay elements 15B to 15D. As the insulating resin 18, a thermosetting resin such as an epoxy resin, a polyimide resin, or a silicone resin is used. The insulating resin 18 is formed by placing each element group 11 to 14 on the wiring substrate 2, filling a liquid resin, and curing the resin. The liquid resin is injected using a dispenser or the like.

各素子群１１〜１４を構成する４個のメモリ素子９の電極パッド１６間は、図３および図４に示すように導電層１９で電気的に接続されている。メモリ素子９の電極パッド１６と中継素子１５の中継パッド１７との間も、同様に導電層１９で電気的に接続されている。各素子群１１〜１４はそれぞれ同様な接続構造を有しているため、第１の素子群１１の接続構造を代表例として図３および図４に示す。これらの図は第１の素子群１１を構成する第１の中継素子１５Ａ上に４個のメモリ素子９、すなわち第１ないし第４の電極パッド１６ａ〜１６ｄを有する第１ないし第４のメモリ素子９ａ〜９ｄが順に階段状に積層された状態、特にメモリ素子９ａ〜９ｄの階段部分を示している。   The electrode pads 16 of the four memory elements 9 constituting each element group 11 to 14 are electrically connected by a conductive layer 19 as shown in FIGS. Similarly, the conductive layer 19 electrically connects the electrode pad 16 of the memory element 9 and the relay pad 17 of the relay element 15. Since each of the element groups 11 to 14 has a similar connection structure, the connection structure of the first element group 11 is shown in FIGS. 3 and 4 as a representative example. These drawings show the first to fourth memory elements having four memory elements 9, that is, first to fourth electrode pads 16a to 16d, on the first relay element 15A constituting the first element group 11. 9a to 9d are sequentially stacked in a staircase pattern, particularly the staircase portions of the memory elements 9a to 9d.

導電層１９は、第１ないし第４のメモリ素子９ａ〜９ｄの階段部分の段差部に相当する側面を介して、階段部分の段面に相当する露出面上に形成されている。このような導電層１９は、例えば導電性材料の微粒子を溶媒やバインダ中に分散させた導電性ペースト（もしくは導電性塗料）を所望のパターンに応じて塗布することにより形成される。導電性材料の微粒子としては、金微粒子や銀微粒子等が用いられる。導電性ペーストは、例えばインクジェットヘッドから吐出させて塗布される。あるいは、スクリーン印刷法等のマスクを用いた印刷法を適用して、導電性ペーストを塗布してもよい。インクジェット法によれば、微細パターンを有する導電層１９を再現性よく形成することができる。   The conductive layer 19 is formed on the exposed surface corresponding to the step surface of the staircase portion via the side surface corresponding to the step portion of the staircase portion of the first to fourth memory elements 9a to 9d. Such a conductive layer 19 is formed, for example, by applying a conductive paste (or conductive paint) in which fine particles of a conductive material are dispersed in a solvent or a binder according to a desired pattern. As the fine particles of the conductive material, gold fine particles, silver fine particles and the like are used. The conductive paste is applied by being discharged from, for example, an inkjet head. Alternatively, the conductive paste may be applied by applying a printing method using a mask such as a screen printing method. According to the ink jet method, the conductive layer 19 having a fine pattern can be formed with good reproducibility.

メモリ素子９ａ〜９ｄの階段部分の段差部に相当する側面は、通常、半導体基板（Ｓｉ基板等）が露出している場合が多い。そこで、各メモリ素子９ａ〜９ｄの側面は第１の絶縁層２０で覆われている。導電層１９は第１の絶縁層２０上に形成される。このため、第１の絶縁層２０はスロープ状に形成することが好ましい。これによって、導電層１９の形成性を高めることができ、第１の絶縁層２０上での配線切れの発生等を抑制することができる。第１の絶縁層２０は導電層１９と同様に、絶縁性ペースト（もしくは絶縁性塗料）をインクジェット法やマスクを用いた印刷法等を適用して塗布することにより形成される。あるいは、絶縁性の液状樹脂を塗布して形成してもよい。   In many cases, the semiconductor substrate (Si substrate or the like) is usually exposed at the side surface corresponding to the stepped portion of the staircase portion of the memory elements 9a to 9d. Therefore, the side surfaces of the memory elements 9 a to 9 d are covered with the first insulating layer 20. The conductive layer 19 is formed on the first insulating layer 20. For this reason, the first insulating layer 20 is preferably formed in a slope shape. As a result, the formability of the conductive layer 19 can be improved, and the occurrence of wiring breakage on the first insulating layer 20 can be suppressed. Similar to the conductive layer 19, the first insulating layer 20 is formed by applying an insulating paste (or insulating paint) by applying an inkjet method, a printing method using a mask, or the like. Alternatively, an insulating liquid resin may be applied and formed.

ここで、第１ないし第４のメモリ素子９ａ〜９ｄの電極パッド１６ａ〜１６ｄの電気特性や信号特性等が等しい場合には、第１ないし第４のメモリ素子９ａ〜９ｄと中継素子１５Ａの階段部分に導電層１９を直線状に形成することによって、第１ないし第４の電極パッド１６ａ〜１６ｄと中継パッド１７との間を順に接続することができる。例えば、第１ないし第４のメモリ素子９ａ〜９ｄの電極パッド１６のうち、データ信号用端子（ＩＯ）や電圧端子（Ｖｃｃ）等に関しては、第１ないし第４の電極パッド１６ａ〜１６ｄが直線状の導電層１９１で順に接続されている。   Here, when the electrical characteristics and signal characteristics of the electrode pads 16a to 16d of the first to fourth memory elements 9a to 9d are equal, the staircase between the first to fourth memory elements 9a to 9d and the relay element 15A. By forming the conductive layer 19 in a straight line in the portion, the first to fourth electrode pads 16a to 16d and the relay pad 17 can be connected in order. For example, among the electrode pads 16 of the first to fourth memory elements 9a to 9d, the first to fourth electrode pads 16a to 16d are linear with respect to the data signal terminal (IO) and the voltage terminal (Vcc). The conductive layers 191 are connected in order.

一方、素子選択（チップセレクト）等の制御信号用端子（ＣＥ，ＲＢ等）に関しては、例えば制御信号に応じて各メモリ素子９ａ〜９ｄの電極パッド１６ａ〜１６ｄ毎に配線基板２の接続パッド７（ここでは中継素子１５Ａの中継パッド１７）と電気的に接続しなければならない場合がある。例えば、ＣＥ端子およびＲＢ端子に関しては、第１および第２のメモリ素子９ａ、９ｂの電極パッド１６ａ、１６ｂと、第３および第４のメモリ素子９ｃ、９ｄの電極パッド１６ｃ、１６ｄとに分け、それぞれを個別に配線基板２の接続パッド７（ここでは中継素子１５Ａの中継パッド１７）と電気的に接続する。   On the other hand, for control signal terminals (CE, RB, etc.) such as element selection (chip select), for example, the connection pads 7 of the wiring board 2 for each of the electrode pads 16a-16d of the memory elements 9a-9d according to the control signal. In some cases, it may be necessary to electrically connect to the relay pad 17 of the relay element 15A. For example, the CE terminal and the RB terminal are divided into electrode pads 16a and 16b of the first and second memory elements 9a and 9b and electrode pads 16c and 16d of the third and fourth memory elements 9c and 9d. Each is individually electrically connected to the connection pad 7 of the wiring board 2 (here, the relay pad 17 of the relay element 15A).

このような場合、第１ないし第４の電極パッド１６ａ〜１６ｄを直線状の導電層１９で順に接続することができず、また第３および第４の電極パッド１６ｃ、１６ｄと中継パッド１７との間に第１および第２の電極パッド１６ａ、１６ｂが存在することになるため、直接的に接続することができない。そこで、この実施形態の積層型半導体装置１においては、電極パッド１６間および電極パッド１６と中継パッド１７との間を接続する導電層１９の一部、具体的には制御信号用端子の接続に用いられる導電層１９を、第１ないし第４のメモリ素子９ａ〜９ｄの階段部分の段差部に相当する露出面上で引き回している。   In such a case, the first to fourth electrode pads 16a to 16d cannot be connected in order by the linear conductive layer 19, and the third and fourth electrode pads 16c and 16d and the relay pad 17 are not connected. Since the first and second electrode pads 16a and 16b exist between them, they cannot be directly connected. Therefore, in the stacked semiconductor device 1 of this embodiment, a part of the conductive layer 19 that connects the electrode pads 16 and between the electrode pads 16 and the relay pads 17, specifically, connection of control signal terminals is used. The conductive layer 19 used is routed on the exposed surface corresponding to the stepped portion of the step portion of the first to fourth memory elements 9a to 9d.

具体的には、ＣＥ端子およびＲＢ端子となる電極パッド１６のうち、第１および第２のメモリ素子９ａ、９ｂの電極パッド１６ａ、１６ｂは導電層１９２で中継パッド１７と接続している。第３および第４のメモリ素子９ｃ、９ｄの電極パッド１６ｃ、１６ｄについては、電極パッド１６ｃ、１６ｄ間を導電層１９３で接続し、さらに導電層１９３を露出面上で引き回し、各メモリ素子９の隣接する電極パッド１６間に配置した後、中継パッド１７と接続している。このように、導電層１９の一部をメモリ素子９の露出面上で引き回すことによって、制御信号用の電極パッド１６に関しても中継素子１５の中継パッド１７、ひいては配線基板２の接続パッド７と導電層１９で良好に接続することができる。   Specifically, among the electrode pads 16 serving as the CE terminal and the RB terminal, the electrode pads 16 a and 16 b of the first and second memory elements 9 a and 9 b are connected to the relay pad 17 by the conductive layer 192. Regarding the electrode pads 16c and 16d of the third and fourth memory elements 9c and 9d, the electrode pads 16c and 16d are connected by the conductive layer 193, and the conductive layer 193 is further routed on the exposed surface. After being arranged between the adjacent electrode pads 16, it is connected to the relay pad 17. In this way, by routing a part of the conductive layer 19 on the exposed surface of the memory element 9, the conductive pad 19 of the relay element 15 and the connection pad 7 of the wiring board 2 and the conductive pad 17 are also electrically connected to the electrode pad 16 for the control signal. The layer 19 can be connected well.

導電層１９の一部をメモリ素子９の露出面上で引き回すにあたって、図３に示すＲＢ端子のように、各メモリ素子９の隣接する電極パッド１６間にスペースが存在する場合には、電極パッド１６間に直接導電層１９を形成すればよい。一方、図３に示すＣＥ端子のように、電極パッド１６間に配線引き回し用のスペースが存在しない場合には、隣接する電極パッド１６（非接続パッド）を第２の絶縁層２１で覆った後、その上に導電層１９を形成する。すなわち、各メモリ素子９ａ〜９ｄの露出面上には導電層１９の配線パターン（制御端子用配線の形成パターン）に応じて第２の絶縁層２１が形成されている。そして、導電層１９の一部は第２の絶縁層２１上を介して引き回されている。第２の絶縁層２１は第１の絶縁層２０と同様にして形成することができる。   When a part of the conductive layer 19 is routed on the exposed surface of the memory element 9, when there is a space between the adjacent electrode pads 16 of each memory element 9 as in the RB terminal shown in FIG. The conductive layer 19 may be directly formed between the sixteen. On the other hand, when there is no wiring routing space between the electrode pads 16 as in the CE terminal shown in FIG. 3, the adjacent electrode pads 16 (non-connected pads) are covered with the second insulating layer 21. A conductive layer 19 is formed thereon. That is, the second insulating layer 21 is formed on the exposed surfaces of the memory elements 9a to 9d in accordance with the wiring pattern of the conductive layer 19 (control terminal wiring formation pattern). A part of the conductive layer 19 is routed through the second insulating layer 21. The second insulating layer 21 can be formed in the same manner as the first insulating layer 20.

この実施形態の半導体記憶装置（積層型半導体装置）１においては、導電層１９の一部をメモリ素子９の階段部分の段面に相当する露出面上で引き回しているため、制御信号用端子のようにメモリ素子９毎の接続が必要な場合おいても、メモリ素子９の電極パッド１６と中継素子１５の中継パッド１７、ひいては配線基板２の接続パッド７と導電層１９で良好に接続することができる。さらに、メモリ素子９の露出面に第２の絶縁層２１を形成することによって、導電層１９の引き回し性を高めることができる。従って、メモリ素子９の電極パッド１６と中継素子１５の中継パッド１７、ひいては配線基板２の接続パッド７との接続を、より容易に導電層１９で実施することが可能となる。   In the semiconductor memory device (stacked semiconductor device) 1 of this embodiment, a part of the conductive layer 19 is routed on the exposed surface corresponding to the step surface of the step portion of the memory element 9, so that the control signal terminal Thus, even when connection for each memory element 9 is necessary, the electrode pad 16 of the memory element 9 and the relay pad 17 of the relay element 15, and by extension, the connection pad 7 of the wiring board 2 and the conductive layer 19 should be connected well. Can do. Furthermore, by forming the second insulating layer 21 on the exposed surface of the memory element 9, the routing property of the conductive layer 19 can be improved. Therefore, the connection between the electrode pad 16 of the memory element 9 and the relay pad 17 of the relay element 15 and consequently the connection pad 7 of the wiring board 2 can be more easily performed by the conductive layer 19.

なお、メモリ素子９の露出面における導電層１９の引き回しは、中継素子１５とメモリ素子９とを用いて素子群を構成する場合に限らず、複数のメモリ素子９のみを用いて素子群を構成する場合にも有効である。この際、メモリ素子９の電極パッド１６と配線基板２の接続パッド７との接続は導電層１９で実施してもよい。また、例えば最下段のメモリ素子９の厚さのみを厚くした上で、最下段のメモリ素子９の電極パッド１６と配線基板２の接続パッド７との接続にワイヤボンディングを適用してもよい。中継素子１５と配線基板２との接続に導電層１９を適用することを必ずしも除外するものではない。   The routing of the conductive layer 19 on the exposed surface of the memory element 9 is not limited to the case where an element group is configured using the relay element 15 and the memory element 9, and the element group is configured using only a plurality of memory elements 9. It is also effective when At this time, the connection between the electrode pad 16 of the memory element 9 and the connection pad 7 of the wiring board 2 may be performed by the conductive layer 19. Further, for example, the thickness of only the lowermost memory element 9 may be increased, and then wire bonding may be applied to the connection between the electrode pad 16 of the lowermost memory element 9 and the connection pad 7 of the wiring board 2. The application of the conductive layer 19 to the connection between the relay element 15 and the wiring board 2 is not necessarily excluded.

中継素子１５および複数のメモリ素子９の積層は配線基板２上に順に実施してもよいが、例えば図５ないし図７に示すように、中継素子１５用の半導体ウエハ１０１上に複数のメモリ素子９を順に積層した後に半導体ウエハ１０１を切断し、中継素子１５と複数のメモリ素子９との積層体を素子モジュールとして個片化することが好ましい。さらに、導電層１９の形成についても、半導体ウエハ１０１上で実施することが好ましい。これらによって、各素子群に対応する中継素子１５と複数のメモリ素子９との積層体の製造工数や製造コスト等を削減することができる。なお、図６および図７は半導体ウエハ１０１の１個の中継素子１５に相当する素子領域１０２を示している。   The relay element 15 and the plurality of memory elements 9 may be stacked on the wiring substrate 2 in order. For example, as illustrated in FIGS. 5 to 7, a plurality of memory elements may be formed on the semiconductor wafer 101 for the relay element 15. It is preferable that the semiconductor wafer 101 is cut after laminating 9 in order, and the laminated body of the relay element 15 and the plurality of memory elements 9 is singulated as an element module. Further, the formation of the conductive layer 19 is preferably performed on the semiconductor wafer 101. As a result, it is possible to reduce the number of manufacturing steps, manufacturing costs, and the like of the stacked body of the relay element 15 and the plurality of memory elements 9 corresponding to each element group. 6 and 7 show an element region 102 corresponding to one relay element 15 of the semiconductor wafer 101. FIG.

まず、中継素子１５用の半導体ウエハ１０１の各素子領域１０２に、複数のメモリ素子９を順に積層する。複数のメモリ素子９は接着層を介して接着される。次いで、各素子領域１０２の複数のメモリ素子９に対して絶縁層や導電層を順に形成する。この際、複数のノズルを有する印刷装置等を使用することによって、絶縁層や導電層の形成コストを低減することが可能となる。この後、半導体ウエハ１０１を各素子領域１０２に応じて切断することによって、各素子群に対応する素子モジュール（中継素子１５と複数のメモリ素子９との積層体）を得ることができる。   First, a plurality of memory elements 9 are sequentially stacked in each element region 102 of the semiconductor wafer 101 for the relay element 15. The plurality of memory elements 9 are bonded through an adhesive layer. Next, an insulating layer and a conductive layer are sequentially formed on the plurality of memory elements 9 in each element region 102. At this time, by using a printing apparatus having a plurality of nozzles, the formation cost of the insulating layer and the conductive layer can be reduced. Thereafter, by cutting the semiconductor wafer 101 according to each element region 102, an element module (a stacked body of the relay element 15 and the plurality of memory elements 9) corresponding to each element group can be obtained.

さらに、上記した素子モジュールを配線基板２上に必要数だけ積み重ねることによって、積層型半導体装置１の元となる構造体が得られる。このように、中継素子１５と複数のメモリ素子９との積層体を予め形成しておくことによって、積層型半導体装置１の製造工数や製造コスト等も削減することが可能となる。さらに、素子モジュールの段階で中継素子１５の中継パッド１７を利用して検査を実施することによって、積層型半導体装置１の不良発生率を抑制することができる。なお、素子モジュールの段階で検査した結果として、複数のメモリ素子９のいずれかが不良と判断された場合、不良のメモリ素子９を除く記憶容量分のモジュールとして使用することも可能である。   Further, a necessary number of the above-described element modules are stacked on the wiring board 2 to obtain a structure that is the basis of the stacked semiconductor device 1. In this manner, by forming a stacked body of the relay element 15 and the plurality of memory elements 9 in advance, it is possible to reduce the manufacturing man-hours and manufacturing costs of the stacked semiconductor device 1. Furthermore, by performing inspection using the relay pad 17 of the relay element 15 at the stage of the element module, the defect occurrence rate of the stacked semiconductor device 1 can be suppressed. If any of the plurality of memory elements 9 is determined to be defective as a result of the inspection at the element module stage, it can be used as a module for a storage capacity excluding the defective memory element 9.

上述したように、各素子群１１〜１４を構成するメモリ素子９の電極パッド１６間、およびメモリ素子９の電極パッド１６と中継素子１５の中継パッド１７との間は、導電層１９を介して電気的に接続されている。さらに、各素子群１１〜１４を構成する中継素子１５の中継パッド１７は、それぞれ配線基板２の第１のパッド領域８Ａに配置された接続パッド７と金属ワイヤ２２を介して電気的に接続されている。すなわち、第１の中継素子１５Ａの中継パッド１７は接続パッド７と第１の金属ワイヤ２２Ａを介して電気的に接続されている。同様に、第２ないし第４の中継素子１５Ｂ〜１５Ｄの中継パッド１７は接続パッド７と第２ないし第４の金属ワイヤ２２Ｂ〜２２Ｄを介して電気的に接続されている。金属ワイヤ２２には一般的なＡｕ線やＣｕ線等の金属細線が用いられる。   As described above, the conductive layer 19 is interposed between the electrode pads 16 of the memory element 9 and between the electrode pad 16 of the memory element 9 and the relay pad 17 of the relay element 15 constituting each of the element groups 11 to 14. Electrically connected. Further, the relay pad 17 of the relay element 15 constituting each of the element groups 11 to 14 is electrically connected to the connection pad 7 disposed in the first pad region 8 </ b> A of the wiring board 2 through the metal wire 22. ing. That is, the relay pad 17 of the first relay element 15A is electrically connected to the connection pad 7 via the first metal wire 22A. Similarly, the relay pads 17 of the second to fourth relay elements 15B to 15D are electrically connected to the connection pad 7 via the second to fourth metal wires 22B to 22D. As the metal wire 22, a general fine metal wire such as an Au wire or a Cu wire is used.

メモリ素子９の電極パッド１６と中継素子１５の中継パッド１７との間を導電層１９で接続した上で、中継パッド１７と配線基板２の接続パッド７との間を金属ワイヤ２２で接続することによって、メモリ素子９の保護と配線基板２との接続性の向上を両立させることができる。すなわち、メモリ素子９の電極パッド１６間の接続には導電層１９を適用しているため、メモリ素子９にワイヤボンディングを実施した場合のダメージの発生を回避することができる。さらに、配線基板２と直接接続される中継素子１５は素子構造を持たないため、通常のワイヤボンディングを実施することができる。従って、積層位置が上方となる第２ないし第４の素子群１２〜１４を構成する中継素子１５Ｂ〜１５Ｄに関しても、配線基板２と容易に接続することができる。   The electrode pad 16 of the memory element 9 and the relay pad 17 of the relay element 15 are connected by the conductive layer 19, and the relay pad 17 and the connection pad 7 of the wiring board 2 are connected by the metal wire 22. As a result, both the protection of the memory element 9 and the improvement of the connectivity with the wiring board 2 can be achieved. That is, since the conductive layer 19 is applied to the connection between the electrode pads 16 of the memory element 9, it is possible to avoid the occurrence of damage when wire bonding is performed on the memory element 9. Furthermore, since the relay element 15 directly connected to the wiring board 2 does not have an element structure, normal wire bonding can be performed. Therefore, the relay elements 15B to 15D constituting the second to fourth element groups 12 to 14 whose stacking positions are above can be easily connected to the wiring board 2.

加えて、第２ないし第４の素子群１２〜１４を構成する中継素子１５Ｂ〜１５Ｄの下方に存在する中空部には絶縁樹脂１８が充填されているため、各中継パッド１７にワイヤボンディングする際の接続不良やクラックの発生を防ぐことができる。なお、中継素子１５と配線基板２とを金属ワイヤ２２で接続する構造は、複数の素子群１１〜１４を積み重ねる場合に限らず、単一の素子群の中継素子１５と配線基板２との接続に対しても有効である。前述した製造工程に示すように、中継素子１５上への複数のメモリ素子９の積層および導電層１９の形成はウエハ工程で実施することができる。従って、このような積層体を配線基板２上に配置した後に、通常のワイヤボンディング工程を実施して中継素子１５と配線基板２とを接続することによって、製造コストの低減等を図ることが可能となる。   In addition, since the hollow portions existing below the relay elements 15B to 15D constituting the second to fourth element groups 12 to 14 are filled with the insulating resin 18, the wire bonding to the relay pads 17 is performed. Connection failure and cracks can be prevented. The structure in which the relay element 15 and the wiring board 2 are connected by the metal wire 22 is not limited to the case where the plurality of element groups 11 to 14 are stacked, and the connection between the relay element 15 and the wiring board 2 of a single element group. It is also effective against As shown in the manufacturing process described above, the stacking of the plurality of memory elements 9 and the formation of the conductive layer 19 on the relay element 15 can be performed in a wafer process. Therefore, after arranging such a laminate on the wiring board 2, a normal wire bonding process is performed to connect the relay element 15 and the wiring board 2, thereby reducing the manufacturing cost. It becomes.

第４の素子群１４（具体的には最上段のメモリ素子９）上には、コントローラ素子１０が接着層（図示せず）を介して接着されている。コントローラ素子１０はコ字型パッド構造を有しており、第１の外形辺に沿って配列された電極パッド２３Ａと第２の外形辺に沿って配列された電極パッド２３Ｂと第３の外形辺に沿って配列された電極パッド２３Ｃとを備えている。これら電極パッド２３Ａ〜２３Ｃのうち、第２のパッド領域８Ｂの近傍に位置する電極パッド２３Ａは、第２のパッド領域８Ｂに配置された接続パッド７と金属ワイヤ２４Ａを介して電気的に接続されている。   On the fourth element group 14 (specifically, the uppermost memory element 9), the controller element 10 is bonded via an adhesive layer (not shown). The controller element 10 has a U-shaped pad structure. The electrode pad 23A is arranged along the first outer edge, the electrode pad 23B is arranged along the second outer edge, and the third outer edge. And electrode pads 23C arranged along the line. Of these electrode pads 23A to 23C, the electrode pad 23A located in the vicinity of the second pad region 8B is electrically connected to the connection pad 7 disposed in the second pad region 8B via the metal wire 24A. ing.

第１のパッド領域８Ａの近傍に位置する電極パッド２３Ｂは、第１のパッド領域８Ａに配置された接続パッド７と金属ワイヤ２４Ｂを介して電気的に接続されている。第３の外形辺に沿って配列された電極パッド２３Ｃに関しては、第１のパッド領域８Ａに配置された接続パッド７と直接接続することが困難であることから、コントローラ素子１０と隣接してコントローラ用の中継素子２５が配置されている。第３の外形辺に沿って配列された電極パッド２３Ｃは、コントローラ用の中継素子２５を介して第１のパッド領域８Ａに配置された接続パッド７と接続されている。   The electrode pad 23B located in the vicinity of the first pad region 8A is electrically connected to the connection pad 7 disposed in the first pad region 8A via the metal wire 24B. The electrode pads 23C arranged along the third outer side are difficult to directly connect to the connection pads 7 arranged in the first pad region 8A. A relay element 25 is arranged. The electrode pads 23C arranged along the third outer side are connected to the connection pads 7 arranged in the first pad region 8A via the controller relay element 25.

コントローラ用の中継素子２５は１つの外形辺とそれと直交する他の外形辺のそれぞれに沿って配列された電極パッド（中継パッド）２６Ａ、２６Ｂを有している。コントローラ用の中継素子２５は電極パッド２６Ａがコントローラ素子１０の電極パッド２３Ｃと対向し、かつ電極パッド２６Ｂが第１のパッド領域８Ａの近傍に位置するように配置されている。中継素子２５の電極パッド２６Ａはコントローラ素子１０の電極パッド２３Ｃと第１の中継用金属ワイヤ２７Ａを介して接続されており、電極パッド２６Ｂは第２の中継用金属ワイヤ２７Ｂを介して接続パッド７と電気的に接続されている。中継素子２５は電極パッド２６Ａと電極パッド２６Ｂとを繋ぐ配線層を有している。   The controller relay element 25 has electrode pads (relay pads) 26A and 26B arranged along one outer side and another outer side perpendicular thereto. The relay element 25 for the controller is arranged so that the electrode pad 26A faces the electrode pad 23C of the controller element 10 and the electrode pad 26B is positioned in the vicinity of the first pad region 8A. The electrode pad 26A of the relay element 25 is connected to the electrode pad 23C of the controller element 10 via the first relay metal wire 27A, and the electrode pad 26B is connected to the connection pad 7 via the second relay metal wire 27B. And are electrically connected. The relay element 25 has a wiring layer that connects the electrode pad 26A and the electrode pad 26B.

メモリ素子９やコントローラ素子１０が実装された配線基板２の第２の主面２ｂには、例えばエポキシ樹脂からなる封止樹脂層２８がモールド成形されている。メモリ素子９やコントローラ素子１０は、金属ワイヤ２２、２４、２７等と共に封止樹脂層２８で一体的に封止されている。封止樹脂層２８の先端には、メモリカードの前方を示す傾斜部２９が設けられている。封止樹脂層２８の後方には封止樹脂を一部盛り上げた取手部３０が設けられている。これらによって、半導体メモリカードとして用いられる半導体記憶装置１が構成されている。なお、図１では封止樹脂層２８の図示を省略している。   On the second main surface 2b of the wiring substrate 2 on which the memory element 9 and the controller element 10 are mounted, a sealing resin layer 28 made of, for example, an epoxy resin is molded. The memory element 9 and the controller element 10 are integrally sealed with a sealing resin layer 28 together with the metal wires 22, 24, 27 and the like. An inclined portion 29 indicating the front of the memory card is provided at the tip of the sealing resin layer 28. Behind the sealing resin layer 28 is provided a handle portion 30 in which a part of the sealing resin is raised. These constitute a semiconductor memory device 1 used as a semiconductor memory card. In FIG. 1, illustration of the sealing resin layer 28 is omitted.

半導体記憶装置１は、ベースカードのような収納ケースを用いることなく、それ単体で半導体メモリカード（例えばマイクロＳＤTMカード）を構成するものである。従って、封止樹脂層２８等は直接外部に露出した状態とされる。すなわち、半導体記憶装置１は封止樹脂層２８等を外部に露出させたケースレスの半導体メモリカードである。このため、上述したメモリカードの前後や表裏の向きを示す切り欠き部やくびれ部、また傾斜部２９等は半導体記憶装置１自体に設けられている。 The semiconductor memory device 1 constitutes a semiconductor memory card (for example, a micro SD ™ card) by itself without using a storage case such as a base card. Therefore, the sealing resin layer 28 and the like are directly exposed to the outside. That is, the semiconductor memory device 1 is a caseless semiconductor memory card in which the sealing resin layer 28 and the like are exposed to the outside. Therefore, the semiconductor memory device 1 itself is provided with the notches and constricted portions, the inclined portions 29 and the like that indicate the front and back and front and back directions of the memory card.

半導体記憶装置１でケースレスのマイクロＳＤTMカードを構成する場合、半導体記憶装置１の厚さ（カード厚）は、例えば７００〜７６０μｍの範囲に設定される。メモリ素子９とコントローラ素子１０の積層厚（素子厚）は、それに配線基板２の厚さや封止樹脂層２８のコントローラ素子１０上での厚さ（素子上樹脂厚）を加えて、カード厚の範囲内とする必要がある。メモリ素子９の極薄化と導電層１９の適用によって、半導体記憶装置１の高容量化と高信頼性化とを両立させることができる。言い換えると、薄型で高容量の半導体記憶装置１の製造歩留りや信頼性を高めることが可能となる。 When a caseless micro SD ™ card is configured with the semiconductor memory device 1, the thickness (card thickness) of the semiconductor memory device 1 is set in a range of 700 to 760 μm, for example. The thickness of the memory element 9 and the controller element 10 (element thickness) is added to the thickness of the wiring board 2 and the thickness of the sealing resin layer 28 on the controller element 10 (resin thickness on the element), Must be within range. By making the memory element 9 extremely thin and applying the conductive layer 19, it is possible to achieve both high capacity and high reliability of the semiconductor memory device 1. In other words, it is possible to increase the manufacturing yield and reliability of the thin and high capacity semiconductor memory device 1.

半導体記憶装置１は４個の素子群を有し、各素子群はそれぞれ１個の中継素子１５と４個のメモリ素子９で構成されているため、合計４個の中継素子１５と合計１６個のメモリ素子９とを具備している。例えば、配線基板２の厚さを１１０μｍ、中継素子１５、メモリ素子９およびコントローラ素子１０の各厚さを１８μｍ、第１の中継素子１５Ａの接着層の厚さを２０μｍ、それを除く素子接着層の各厚さを５μｍ、封止樹脂層２８の素子上樹脂厚を１５２μｍとしたとき、これらの合計厚は７６０μｍとなり、カード厚を満足させることができる。この際、記憶容量が１ＧＢのメモリ素子９を１６個使用した場合、１６ＧＢのマイクロＳＤTMカードを半導体記憶装置１で実現することが可能となる。 Since the semiconductor memory device 1 has four element groups, and each element group is composed of one relay element 15 and four memory elements 9, a total of four relay elements 15 and a total of 16 elements. The memory element 9 is provided. For example, the thickness of the wiring board 2 is 110 μm, the thickness of each of the relay element 15, the memory element 9 and the controller element 10 is 18 μm, the thickness of the adhesive layer of the first relay element 15 A is 20 μm, and the element adhesive layer excluding it When the thickness of each is 5 μm and the on-element resin thickness of the sealing resin layer 28 is 152 μm, the total thickness is 760 μm, and the card thickness can be satisfied. In this case, if the storage capacity using the memory device 9 of 1GB 16 pieces, it is possible to realize a micro SD TM card 16GB in the semiconductor memory device 1.

上述したように、メモリ素子９の電極パッド１６間の接続に導電層１９を適用することによって、メモリ素子９へのダメージを抑制することができる。従って、メモリ素子９の厚さを薄くした場合においても、半導体記憶装置１の信頼性を高めることが可能となる。この実施形態の半導体記憶装置１は、例えばメモリ素子９の厚さを３０μｍ以下、さらには２０μｍ以下というように薄くした場合に有効である。この実施形態のメモリ素子９は例えば３０μｍ以下、さらには２０μｍ以下の厚さを有している。ただし、メモリ素子９の厚さはこれに限定されるものではなく、例えば５０μｍ程度の厚さを有するメモリ素子９を用いる場合においても導電層１９を適用することができる。   As described above, by applying the conductive layer 19 to the connection between the electrode pads 16 of the memory element 9, damage to the memory element 9 can be suppressed. Therefore, even when the thickness of the memory element 9 is reduced, the reliability of the semiconductor memory device 1 can be improved. The semiconductor memory device 1 of this embodiment is effective when, for example, the thickness of the memory element 9 is reduced to 30 μm or less, and further to 20 μm or less. The memory element 9 of this embodiment has a thickness of, for example, 30 μm or less, and further 20 μm or less. However, the thickness of the memory element 9 is not limited to this, and the conductive layer 19 can be applied even when the memory element 9 having a thickness of, for example, about 50 μm is used.

なお、配線基板２上に積み重ねる素子群の数、また各素子群を構成するメモリ素子（半導体素子）９の数は、上述した実施形態に限定されるものではない。各素子群は複数のメモリ素子（半導体素子）９を有していればよい。また、素子群の数は例えば半導体記憶装置１の記憶容量に応じて適宜に設定することができる。場合によっては単一の素子群（複数のメモリ素子９を備える）で半導体記憶装置１を構成してもよい。   The number of element groups stacked on the wiring board 2 and the number of memory elements (semiconductor elements) 9 constituting each element group are not limited to the above-described embodiment. Each element group only needs to have a plurality of memory elements (semiconductor elements) 9. Further, the number of element groups can be appropriately set according to the storage capacity of the semiconductor memory device 1, for example. In some cases, the semiconductor memory device 1 may be configured by a single element group (including a plurality of memory elements 9).

また、上述した実施形態の半導体記憶装置１はそれら単体で構成するケースレスの半導体メモリカードに対して有効であるが、必ずしもベースカードのようなケースを用いた半導体メモリカードを除外するものではない。さらに、半導体メモリカード以外の半導体記憶装置にも適用可能である。具体的には、実施形態の装置構造はＢＧＡパッケージ構造やＬＧＡパッケージ構造を有する半導体記憶装置に適用することができる。   Further, the semiconductor memory device 1 of the above-described embodiment is effective for a caseless semiconductor memory card configured as a single unit, but does not necessarily exclude a semiconductor memory card using a case such as a base card. . Furthermore, the present invention can also be applied to semiconductor memory devices other than semiconductor memory cards. Specifically, the device structure of the embodiment can be applied to a semiconductor memory device having a BGA package structure or an LGA package structure.

本発明の積層型半導体装置は上記実施形態に限定されるものではなく、配線基板上に複数の半導体素子を積層して搭載した各種構造に適用可能である。本発明の積層型半導体装置の具体的な構造は、本発明の基本構成を満足するものであれば種々に変形が可能である。さらに、実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。   The stacked semiconductor device of the present invention is not limited to the above embodiment, and can be applied to various structures in which a plurality of semiconductor elements are stacked and mounted on a wiring board. The specific structure of the stacked semiconductor device of the present invention can be variously modified as long as it satisfies the basic configuration of the present invention. Furthermore, the embodiments can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

１…半導体記憶装置（積層型半導体装置）、２…配線基板、５…外部接続端子、６…素子搭載部、７…接続パッド、９…メモリ素子、１０…コントローラ素子、１１，１２，１３，１４…素子群、１５…中継素子、１６，２３…電極パッド、１７…中継パッド、１９…導電層、２０…第１の絶縁層、２１…第２の絶縁層、２２，２４…金属ワイヤ、２８…封止樹脂層。   DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device (laminated type semiconductor device), 2 ... Wiring board, 5 ... External connection terminal, 6 ... Element mounting part, 7 ... Connection pad, 9 ... Memory element, 10 ... Controller element, 11, 12, 13, DESCRIPTION OF SYMBOLS 14 ... Element group, 15 ... Relay element, 16, 23 ... Electrode pad, 17 ... Relay pad, 19 ... Conductive layer, 20 ... 1st insulating layer, 21 ... 2nd insulating layer, 22, 24 ... Metal wire, 28: Sealing resin layer.

Claims (5)

接続パッドを有する配線基板と、
外形の一辺に沿って配列された電極パッドを有する複数の半導体素子を備え、前記複数の半導体素子は前記配線基板上にパッド配列辺を同方向に向け、かつ前記電極パッドが露出するように階段状に積層されている素子群と、
少なくとも前記複数の半導体素子の前記電極パッド間を接続する導電層と、
前記素子群を封止するように、前記配線基板上に形成された封止樹脂層とを具備し、
前記導電層は、前記複数の半導体素子が有する前記電極パッドを直線状に接続する第１導電層と、前記複数の半導体素子の階段部分の段面に相当する露出面上を引き回されている第２導電層とを有することを特徴とする積層型半導体装置。 A wiring board having connection pads;
A plurality of semiconductor elements having electrode pads arranged along one side of the outer shape, wherein the plurality of semiconductor elements are stepped so that the pad arrangement sides are directed in the same direction on the wiring board and the electrode pads are exposed. A group of elements stacked in a shape;
A conductive layer connecting at least the electrode pads of the plurality of semiconductor elements;
A sealing resin layer formed on the wiring substrate so as to seal the element group;
The conductive layer is routed on a first conductive layer that linearly connects the electrode pads of the plurality of semiconductor elements, and an exposed surface corresponding to a stepped surface of a stepped portion of the plurality of semiconductor elements. A stacked semiconductor device comprising a second conductive layer. 請求項１記載の積層型半導体装置において、
さらに、前記複数の半導体素子の階段部分の段差部に相当する側面を覆う第１の絶縁層と、前記複数の半導体素子の前記露出面上に前記導電層の配線パターンに応じて形成された第２の絶縁層とを具備し、前記第２導電層は前記第２の絶縁層上を介して引き回されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1,
A first insulating layer covering a side surface corresponding to a stepped portion of the stepped portion of the plurality of semiconductor elements; and a first insulating layer formed on the exposed surface of the plurality of semiconductor elements according to the wiring pattern of the conductive layer. A stacked semiconductor device, wherein the second conductive layer is routed through the second insulating layer. 請求項１または請求項２記載の積層型半導体装置において、
前記素子群は外形の一辺に沿って配列された中継パッドを有する中継素子を介して前記配線基板上に配置されており、前記中継パッドは前記電極パッドと前記導電層を介して電気的に接続されていると共に、前記接続パッドと金属ワイヤを介して電気的に接続されていることを特徴とする積層型半導体装置。 The stacked semiconductor device according to claim 1 or 2,
The element group is disposed on the wiring board via a relay element having a relay pad arranged along one side of the outer shape, and the relay pad is electrically connected to the electrode pad via the conductive layer. The stacked semiconductor device is electrically connected to the connection pad through a metal wire. 接続パッドを有する配線基板と、
外形の一辺に沿って配列された中継パッドを有する中継素子と、前記中継素子上に配置され、外形の一辺に沿って配列された電極パッドを有する複数の半導体素子とを備え、前記中継素子および前記複数の半導体素子は前記配線基板上にパッド配列辺を同方向に向け、かつ前記中継パッドおよび前記電極パッドが露出するように階段状に積層されている素子群と、
前記複数の半導体素子の階段部分の段差部に相当する側面を覆う絶縁層と、
前記複数の半導体素子の前記電極パッドと前記中継素子の前記中継パッドとを電気的に接続する導電層であって、前記複数の半導体素子が有する前記電極パッドを直線状に接続する第１導電層と、前記複数の半導体素子の階段部分の段面に相当する露出面上を引き回されている第２導電層とを有する導電層と、
前記中継素子の前記中継パッドと前記配線基板の前記接続パッドとを電気的に接続する金属ワイヤと、
前記素子群を前記金属ワイヤと共に封止するように、前記配線基板上に形成された封止樹脂層と
を具備することを特徴とする積層型半導体装置。 A wiring board having connection pads;
A relay element having a relay pad arranged along one side of the outer shape; and a plurality of semiconductor elements arranged on the relay element and having an electrode pad arranged along one side of the outer shape; The plurality of semiconductor elements have a group of elements stacked in a staircase pattern so that the pad array side is directed in the same direction on the wiring board, and the relay pads and the electrode pads are exposed;
An insulating layer covering a side surface corresponding to a stepped portion of the stepped portion of the plurality of semiconductor elements;
A conductive layer that electrically connects the electrode pads of the plurality of semiconductor elements and the relay pads of the relay element, the first conductive layer connecting the electrode pads of the plurality of semiconductor elements linearly And a conductive layer having a second conductive layer routed on an exposed surface corresponding to the step surface of the stepped portion of the plurality of semiconductor elements,
A metal wire that electrically connects the relay pad of the relay element and the connection pad of the wiring board;
A laminated semiconductor device comprising: a sealing resin layer formed on the wiring substrate so as to seal the element group together with the metal wires. 接続パッドを有する配線基板と、
外形の一辺に沿って配列された中継パッドを有する第１の中継素子と、前記第１の中継素子上に配置され、外形の一辺に沿って配列された電極パッドを有する複数の半導体素子とを備え、前記第１の中継素子および前記複数の半導体素子は前記配線基板上にパッド配列辺を同方向に向け、かつ前記中継パッドおよび前記電極パッドが露出するように階段状に積層されている第１の素子群と、
前記第１の素子群における前記複数の半導体素子の階段部分の段差部に相当する側面を覆う第１の素子群用絶縁層と、
前記第１の素子群を構成する前記複数の半導体素子の前記電極パッドと前記第１の中継素子の前記中継パッドとを電気的に接続する第１の素子群用導電層であって、前記複数の半導体素子が有する前記電極パッドを直線状に接続する第１導電層と、前記複数の半導体素子の階段部分の段面に相当する露出面上を引き回されている第２導電層とを有する第１の素子群用導電層と、
前記第１の中継素子の前記中継パッドと前記配線基板の前記接続パッドとを電気的に接続する第１の金属ワイヤと、
外形の一辺に沿って配列された中継パッドを有する第２の中継素子と、前記第２の中継素子上に配置され、外形の一辺に沿って配列された電極パッドを有する複数の半導体素子とを備え、前記第２の中継素子および前記複数の半導体素子は前記第１の素子群上にパッド配列辺を同方向に向け、かつ前記中継パッドおよび前記電極パッドが露出するように階段状に積層されている第２の素子群と、
前記第２の素子群における前記複数の半導体素子の階段部分の段差部に相当する側面を覆う第２の素子群用絶縁層と、
前記第２の素子群を構成する前記複数の半導体素子の前記電極パッドと前記第２の中継素子の前記中継パッドとを電気的に接続する第２の素子群用導電層であって、前記複数の半導体素子が有する前記電極パッドを直線状に接続する第３導電層と、前記複数の半導体素子の階段部分の段面に相当する露出面上を引き回されている第４導電層とを有する第２の素子群用導電層と、
前記第２の中継素子の前記中継パッドと前記配線基板の前記接続パッドとを電気的に接続する第２の金属ワイヤと、
前記第１および第２の素子群を前記第１および第２の金属ワイヤと共に封止するように、前記配線基板上に形成された封止樹脂層と
を具備することを特徴とする積層型半導体装置。 A wiring board having connection pads;
A first relay element having relay pads arranged along one side of the outer shape; and a plurality of semiconductor elements having electrode pads arranged on the first relay element and arranged along one side of the outer shape. And the first relay element and the plurality of semiconductor elements are stacked in a stepped manner on the wiring board so that the pad array side faces in the same direction and the relay pad and the electrode pad are exposed. 1 element group;
A first element group insulating layer covering a side surface corresponding to a stepped portion of a stepped portion of the plurality of semiconductor elements in the first element group;
A first element group conductive layer electrically connecting the electrode pads of the plurality of semiconductor elements constituting the first element group and the relay pads of the first relay element, A first conductive layer that linearly connects the electrode pads of the semiconductor element, and a second conductive layer that is routed on an exposed surface corresponding to the step surface of the stepped portion of the plurality of semiconductor elements. A first element group conductive layer;
A first metal wire that electrically connects the relay pad of the first relay element and the connection pad of the wiring board;
A second relay element having relay pads arranged along one side of the outer shape, and a plurality of semiconductor elements having electrode pads arranged on the second relay element and arranged along one side of the outer shape. And the second relay element and the plurality of semiconductor elements are stacked stepwise on the first element group so that the pad array side faces in the same direction and the relay pad and the electrode pad are exposed. A second element group,
A second element group insulating layer covering a side surface corresponding to a stepped portion of a stepped portion of the plurality of semiconductor elements in the second element group;
A second element group conductive layer for electrically connecting the electrode pads of the plurality of semiconductor elements constituting the second element group and the relay pads of the second relay element, A third conductive layer that linearly connects the electrode pads of the semiconductor element, and a fourth conductive layer that is routed on an exposed surface corresponding to the step surface of the stepped portion of the plurality of semiconductor elements. A second element group conductive layer;
A second metal wire for electrically connecting the relay pad of the second relay element and the connection pad of the wiring board;
And a sealing resin layer formed on the wiring substrate so as to seal the first and second element groups together with the first and second metal wires. apparatus.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013162071A (en) * 2012-02-08 2013-08-19 J Devices:Kk Semiconductor device and manufacturing method of the same
US9286950B2 (en) 2011-05-03 2016-03-15 Samsung Electronics Co., Ltd. Semiconductor chip, memory chip, semiconductor package and memory system
JP2016081943A (en) * 2014-10-09 2016-05-16 三菱電機株式会社 Semiconductor device, and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113252A (en) * 1984-11-08 1986-05-31 Fujitsu Ltd Semiconductor device
JPH01140652A (en) * 1987-11-26 1989-06-01 Sharp Corp Three-dimensional semiconductor device
JP2003086762A (en) * 2001-07-04 2003-03-20 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2003232518A (en) * 2002-02-07 2003-08-22 Star Trading Kk Battery ignition type lighter having ignition automatic safety device function
JP2006278975A (en) * 2005-03-30 2006-10-12 Sharp Corp Semiconductor device
JP2006313798A (en) * 2005-05-06 2006-11-16 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113252A (en) * 1984-11-08 1986-05-31 Fujitsu Ltd Semiconductor device
JPH01140652A (en) * 1987-11-26 1989-06-01 Sharp Corp Three-dimensional semiconductor device
JP2003086762A (en) * 2001-07-04 2003-03-20 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2003232518A (en) * 2002-02-07 2003-08-22 Star Trading Kk Battery ignition type lighter having ignition automatic safety device function
JP2006278975A (en) * 2005-03-30 2006-10-12 Sharp Corp Semiconductor device
JP2006313798A (en) * 2005-05-06 2006-11-16 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9286950B2 (en) 2011-05-03 2016-03-15 Samsung Electronics Co., Ltd. Semiconductor chip, memory chip, semiconductor package and memory system
JP2013162071A (en) * 2012-02-08 2013-08-19 J Devices:Kk Semiconductor device and manufacturing method of the same
JP2016081943A (en) * 2014-10-09 2016-05-16 三菱電機株式会社 Semiconductor device, and method of manufacturing the same

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