JP2005210048A - Manufacturing method of semiconductor device, semiconductor device, circuit board, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of improving an etching rate in dry etching and improving the quality of the semiconductor device. <P>SOLUTION: Before carrying out dry-etching to the rear face of a semiconductor substrate 10, a film 70 reduced in the area of an etching opening is formed on the rear face 10b of the semiconductor substrate 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, a circuit board, and an electronic apparatus.

Portable electronic devices such as mobile phones, notebook personal computers, and PDAs (Personal Data Assistance) are required to be smaller and lighter. Along with this, the mounting space of the semiconductor chip in the electronic device described above is also limited, and high-density mounting of the semiconductor chip has become a problem. Therefore, a three-dimensional mounting technique has been proposed in which semiconductor chips are stacked and the semiconductor chips are interconnected to achieve high-density mounting of the semiconductor chips (see, for example, Patent Document 1).
JP 2002-25948 A

  In the above three-dimensional mounting technology, a semiconductor chip usually has a structure in which an electrode penetrates from an active surface to a back surface of a substrate on which an integrated circuit is formed. Therefore, an etching process for exposing the tip of the through electrode is performed in the manufacturing process of the semiconductor chip.

  Among etching processes that expose the tip of the through electrode, in particular, in the etching process that exposes the tip of the electrode on the back side of the substrate, the substrate is formed for the purpose of uniforming the back surface height of the substrate excluding the electrode tip. Etching is simultaneously performed on the entire back surface of the substrate.

  In this case, it is preferable to use dry etching rather than wet etching for improving accuracy. However, when dry etching is applied to the above etching process, the etching area is too large compared to the tip portion of the electrode that requires accuracy, so that it is difficult to improve the etching rate, and thus etching takes time. was there. In other words, the normal etching gas does not have a high selectivity with respect to the insulating film covering the tip of the electrode. Therefore, the etching rate cannot be increased by increasing the etching conditions, and therefore the etching takes a lot of time. It was.

  The present invention has been made in view of the above circumstances, and a semiconductor device manufacturing method, a semiconductor device, a circuit board, and a semiconductor device capable of improving the etching rate in dry etching processing and improving the quality of the semiconductor device, An object is to provide electronic equipment.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate, and the semiconductor substrate is formed from an active surface of the semiconductor substrate on which an integrated circuit is formed. Forming a recess over the interior of the substrate, forming an insulating layer on the inner surface of the recess, filling an inner side of the insulating layer with a conductive material to form an electrode, and dry the back surface of the semiconductor substrate. Etching to expose the tip of the electrode, and removing the insulating layer at the tip of the electrode to expose the tip of the electrode. Before the dry etching of the back surface, a step of forming a film for reducing an etching opening area on the back surface of the semiconductor substrate is provided.

According to the method for manufacturing a semiconductor device according to the present invention, since the film for reducing the etching opening area is formed on the back surface of the semiconductor substrate, the etching of the portion masked by the film is suppressed during dry etching. On the other hand, the opening of the film is preferentially etched. Therefore, the etching rate is improved as compared with the whole surface etching in which the entire back surface of the semiconductor substrate is dry-etched, and accordingly, the etching characteristics are stabilized and the etching time is shortened.
For example, when the etching opening area is set to 1% or less as compared with the whole surface etching, an improvement in etching rate of about 10 times or more can be expected.
Note that the mask film formed on the back surface of the semiconductor substrate can be removed at any timing after dry etching. In addition, the film may be left in the case where no trouble is caused by the film or when a specific function is given to the film.

  Another method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having an electrode penetrating the semiconductor substrate, from the active surface of the semiconductor substrate on which the integrated circuit is formed to the inside of the semiconductor substrate. A step of forming a recess, a step of forming an insulating layer on the inner surface of the recess, a step of filling an inner side of the insulating layer with a conductive material to form an electrode, and dry etching the back surface of the semiconductor substrate. A step of exposing the tip of the electrode, and a step of exposing the tip of the electrode by removing the insulating layer at the tip of the electrode and drying the back surface of the semiconductor substrate. XeF gas is used as an etching gas for etching.

  According to the method for manufacturing a semiconductor device of the present invention, XeF gas, which has a high selectivity between the semiconductor substrate and the insulating film covering the electrode tip, is used as an etching gas for dry etching the back surface of the semiconductor substrate. Therefore, the etching rate can be improved without increasing the etching conditions, and the etching characteristics can be stabilized and the etching time can be shortened.

Also in this method of manufacturing a semiconductor device, it is desirable to have a step of forming a film for reducing an etching opening area on the back surface of the semiconductor substrate before dry etching the back surface of the semiconductor substrate.
As a result, the etching rate is further improved as described above, and the etching characteristics are stabilized and the etching time is shortened.

In the method for manufacturing a semiconductor device, it is preferable that the film has an opening at a position corresponding to a tip portion of the electrode.
Thereby, the part corresponding to the front-end | tip part of an electrode is preferentially etched among the back surfaces of a semiconductor substrate. Then, the tip portion of the electrode is exposed satisfactorily by a high rate and stable dry etching process. Further, when the etching selectivity is improved by improving the etching rate, it becomes easier to expose the tip of the electrode higher.

  In this case, in the semiconductor device manufacturing method described above, it is desirable that the opening of the film is determined in shape (including the opening area) according to the shape of the terminal connected to the tip of the electrode.

Here, when the portion corresponding to the tip portion of the electrode (the opening portion of the film) in the back surface of the semiconductor substrate is preferentially etched, the portion becomes depressed as compared with other portions.
Therefore, when a plurality of semiconductor devices are stacked, it is possible to reduce the distance between the substrates by disposing at least a part of the other electrode connected to the tip of the electrode inside the recess. That is, it is possible to reduce the size of the stacked semiconductor device.
Or when laminating | stacking a some semiconductor device, it becomes possible to avoid mechanical contact in parts other than an electrode reliably by the said hollow, and it becomes possible to connect electrodes more reliably.
Since the recess is partially formed on the back surface of the semiconductor substrate, the strength of the semiconductor substrate is ensured by having a predetermined thickness for the other portion even if the substrate thickness of the recess is reduced. .

In the method of manufacturing a semiconductor device, the step of forming the film may include a step of forming a resist film on a back surface of the semiconductor substrate and a step of patterning the resist film to form the opening. .
By using such a patterning method, it is possible to easily cope with higher definition and higher density of the semiconductor substrate.

Preferably, the method for manufacturing a semiconductor device includes a step of wet-etching the back surface of the semiconductor substrate so that the position of the back surface of the semiconductor substrate approaches the tip of the electrode before forming the film. .
That is, by forming the back surface position of the semiconductor substrate close to the tip of the electrode by wet etching before forming the mask film, the processing time required for dry etching can be shortened.

  The tip of the electrode may be exposed to some extent by wet etching, and then the tip of the electrode may be further exposed by dry etching. In this case, the manufactured semiconductor device has a configuration in which the tip portion of the electrode protrudes from the back surface of the semiconductor substrate. The form in which the tip portion of the electrode protrudes facilitates connection between the electrodes when a plurality of semiconductor devices are stacked.

A semiconductor device according to the present invention is manufactured by using the semiconductor device manufacturing method described above.
A semiconductor device manufactured using the above manufacturing method can be improved in quality by stabilizing etching characteristics and shortening etching time.

  Another semiconductor device according to the present invention is formed through an insulating layer in a semiconductor substrate on which an integrated circuit is formed and a through hole formed from the active surface of the semiconductor substrate to the back surface of the semiconductor substrate. And a recess is formed around the electrode on the back surface of the semiconductor substrate.

According to the semiconductor device described above, the depression is formed around the electrode on the back surface of the semiconductor substrate, so that the weight and size can be reduced.
Since the recess is partially formed on the back surface of the semiconductor substrate, the strength of the semiconductor substrate is ensured by having a predetermined thickness for the other portion even if the substrate thickness of the recess is reduced. .

  In the semiconductor device described above, it is preferable that the recess (on the back surface of the semiconductor substrate) has a shape (including a size and a depth) determined in accordance with the shape of another electrode connected to the electrode.

  For example, in the case of stacking a plurality of semiconductor devices, at least a part of the other electrode connected to the tip of the electrode is disposed in the inside of the recess, thereby reducing the distance between the substrates, and as a result, the semiconductor The apparatus can be reduced in size. Or the mechanical contact in parts other than an electrode is avoided by the said hollow, and electrodes come to connect reliably.

  The above-described semiconductor device is used in a form in which, for example, a plurality of semiconductor devices are stacked and the electrodes of the semiconductor devices adjacent in the vertical direction are electrically connected via solder or wax material.

  A circuit board according to the present invention is mounted with the above-described semiconductor device. Thereby, the circuit board with the said effect can be provided.

  An electronic apparatus according to the present invention includes the above-described semiconductor device. Thereby, the electronic device with the said effect can be provided.

Embodiments of the present invention will be described below with reference to the drawings.
Here, FIG. 1 is a side sectional view of an electrode portion of a semiconductor chip, FIGS. 2 to 9 are explanatory views of a method of manufacturing a semiconductor chip, FIG. 10 is an explanatory view of a stacked state of a semiconductor device, and FIG. FIG. 12 and FIG. 13 are explanatory diagrams of rewiring, FIG. 14 is an explanatory diagram of a circuit board, and FIG. 15 is a perspective view of a mobile phone which is an example of an electronic device. FIG.
In each drawing used for the following description, the scale of each member is appropriately changed in order to make each member a recognizable size.

(Semiconductor device)
First, a semiconductor chip which is an embodiment of a semiconductor device according to the present invention will be described with reference to FIG.
FIG. 1 is a side sectional view of an electrode portion of a semiconductor chip according to the present embodiment. The semiconductor chip 2 according to the present embodiment includes a first insulating material in a semiconductor substrate 10 on which an integrated circuit is formed and a through hole H4 formed from the active surface 10a of the semiconductor substrate 10 to the back surface 10b of the semiconductor substrate 10. And an electrode 34 formed through an insulating film 22 as a layer.

  In addition, a recess 10 k is formed around the plug portion 36 of the electrode 34 on the back surface 10 b of the semiconductor substrate 10. The shape and size of the recess 10k are determined according to the shape and size of the other electrode connected to the tip of the electrode 34 in the recess 10k. In the case of this example, the same terminal as the post portion 35 of the electrode 34 formed on the active surface 10a (the post portion of the electrode on another substrate) is connected to the tip of the electrode 34 in the recess 10k, as will be described later. Therefore, the planar shape and size of the recess 10k on the back surface 10b are determined according to the planar shape and size of the post portion 35 on the active surface 10a side. Specifically, the recess 10k is formed in a shape and size that allow at least a part of the post portion 35 to be accommodated therein. That is, the opening area of the recess 10k is larger than the cross-sectional area of the post portion 35 (area when viewed in plan). As will be described later, the recess 10k is formed in association with a technique for improving the processing efficiency in the manufacturing process of the semiconductor chip.

(Semiconductor device)
In the semiconductor chip 2 shown in FIG. 1, an integrated circuit (not shown) made of transistors, memory elements, and other electronic elements is formed on a surface 10a of a semiconductor substrate 10 made of Si (silicon) or the like. An insulating film 12 made of SiO ₂ (silicon oxide) or the like is formed on the active surface 10 a of the semiconductor substrate 10. Further, an interlayer insulating film 14 made of borophosphosilicate glass (hereinafter referred to as BPSG) or the like is formed on the surface of the insulating film 12.

  An electrode pad 16 is formed on a predetermined portion of the surface of the interlayer insulating film 14. The electrode pad 16 includes a first layer 16a made of Ti (titanium) or the like, a second layer 16b made of TiN (titanium nitride) or the like, a third layer 16c made of AlCu (aluminum / copper) or the like, and TiN or the like. The fourth layer (cap layer) 16d is formed by sequentially stacking. Note that the constituent material of the electrode pad 16 may be appropriately changed according to the electrical characteristics, physical characteristics, and chemical characteristics required for the electrode pad 16. That is, the electrode pad 16 may be formed using only Al generally used as an electrode of the integrated circuit, or the electrode pad 16 may be formed using only Cu having a low electric resistance.

  The electrode pads 16 are formed side by side in the periphery of the semiconductor chip 2 in plan view. The electrode pad 16 may be formed side by side in the periphery of the semiconductor chip 2 or may be formed side by side in the center. When formed in the peripheral portion, the semiconductor chip 2 is formed side by side along at least one side (in many cases, two or four sides). Each electrode pad 16 is electrically connected to the integrated circuit described above at a location not shown. Note that no integrated circuit is formed below the electrode pad 16.

A passivation film 18 is formed on the surface of the interlayer insulating film 14 so as to cover the electrode pad 16. The passivation film 18 is made of SiO ₂ (silicon oxide), SiN (silicon nitride), polyimide resin, or the like, and has a thickness of, for example, about 1 μm.

An opening H1 of the passivation film 18 and an opening H2 of the electrode pad 16 are formed at the center of the electrode pad 16. The diameter of the opening H2 is smaller than the diameter of the opening H1, and is set to about 60 μm, for example. The fourth layer 16d in the electrode pad 16 is opened with the same diameter as the opening H1. On the other hand, an insulating film 20 made of SiO ₂ (silicon oxide) or the like is formed on the surface of the passivation film 18 and the inner surfaces of the opening H1 and the opening H2.

  A hole H3 penetrating the insulating film 20, the interlayer insulating film 14, the insulating film 12, and the semiconductor substrate 10 is formed in the central portion of the electrode pad 16. The diameter of the hole H3 is smaller than the diameter of the opening H2, for example, about 30 μm. The hole H3 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view. The opening H1, the opening H2, and the hole H3 form a through hole H4 that penetrates from the active surface to the back surface of the semiconductor substrate.

  An insulating film 22 as a first insulating layer is formed on the inner surface of the through hole H4 and the surface of the insulating film 20. The insulating film 22 prevents current leakage, erosion due to oxygen, moisture, and the like, and is formed to a thickness of about 1 μm. The insulating film 22 is formed so as to protrude from the back surface 10 b of the semiconductor substrate 10. On the other hand, the insulating film 20 and the insulating film 22 formed on the surface of the third layer 16c of the electrode pad 16 are partially removed along the periphery of the opening H2.

  A base film 24 is formed on the exposed surface of the third layer 16 c of the electrode pad 16 and the remaining surface of the insulating film 22. The base film 24 includes a barrier layer (barrier metal) formed on the surface of the insulating film 22 and the like, and a seed layer (seed electrode) formed on the surface of the barrier layer. The barrier layer prevents the constituent material of the electrode 34 described later from diffusing into the substrate 10 and is made of TiW (titanium tungsten), TiN (titanium nitride), TaN (tantalum nitride), or the like. On the other hand, the seed layer serves as an electrode when an electrode 34 described later is formed by plating, and is made of Cu, Au, Ag, or the like.

  An electrode 34 is formed inside the base film 24. The electrode 34 is made of a conductive material having a low electrical resistance such as Cu or W. Note that if the electrode 34 is formed of a conductive material in which poly-Si (polysilicon) is doped with impurities such as B and P, it is not necessary to prevent diffusion to the substrate 10, so that the barrier layer described above becomes unnecessary. . And the plug part 36 of the electrode 34 is formed by forming the electrode 34 in the through-hole H4. The plug portion 36 and the electrode pad 16 are electrically connected via the base film 24 at the P portion in FIG. Further, the lower end surface of the plug portion 36 is exposed to the outside. On the other hand, the post part 35 of the electrode 34 is formed by extending the electrode 34 above the passivation film 18 and also at the peripheral part of the opening H1. The post portion 35 is not limited to a circular shape in plan view, and may be formed in a rectangular shape in plan view.

  In the present embodiment, the tip end surface of the plug portion 36 of the electrode 34 on the back side of the substrate 10 is formed so as to protrude from the back surface 10 b of the semiconductor substrate 10. Thereby, when laminating a plurality of semiconductor chips, a space between the semiconductor chips can be ensured, so that the gaps between the semiconductor chips can be easily filled with underfill or the like. Note that by adjusting the protruding height of the plug portion 36, the interval between the stacked semiconductor chips can be adjusted. Further, instead of filling underfill or the like after the lamination, even when a thermosetting resin or the like is applied to the back surface 10b of the semiconductor chip 2 before the lamination, the thermosetting resin or the like is applied while avoiding the protruding plug portion 36. Therefore, the semiconductor chip wiring connection can be reliably performed.

  On the other hand, a solder layer 40 is formed on the upper surface of the post portion 35 of the electrode 34. The solder layer 40 may be formed of a general PbSn alloy or the like, but is preferably formed of a lead-free solder material such as an AgSn alloy from the viewpoint of the environment. Instead of the solder layer 40 which is a soft wax material, a hard wax material (molten metal) layer made of SnAg alloy or the like, or a metal paste layer made of Ag paste or the like may be formed. It is preferable from the viewpoint of the environment and the like that the hard wax material layer and the metal paste layer are also formed of a lead-free material. The semiconductor chip 2 according to the present embodiment is configured as described above.

(Method for manufacturing semiconductor device)
Next, the semiconductor chip manufacturing method according to the present embodiment will be described with reference to FIGS. 2 to 9 are explanatory diagrams of the semiconductor chip manufacturing method according to the present embodiment. In the following, a case where a plurality of semiconductor chip formation regions in a semiconductor substrate are simultaneously processed will be described as an example. However, the following processing may be performed on each semiconductor chip.

  First, as shown in FIG. 2A, the insulating film 12 and the interlayer insulating film 14 are formed on the surface of the semiconductor substrate 10. Then, an electrode pad 16 is formed on the surface of the interlayer insulating film 14. Specifically, first, the first to fourth layers of the electrode pad 16 are sequentially formed on the entire surface of the interlayer insulating film 14. Each film is formed by sputtering or the like. Next, a resist or the like is applied to the surface. Further, the final shape of the electrode pad 16 is patterned on the resist by photolithography. Then, etching is performed using the patterned resist as a mask to form electrode pads in a predetermined shape (for example, a rectangular shape). Thereafter, a passivation film 18 is formed on the surface of the electrode pad 16.

  Next, an opening H <b> 1 is formed in the passivation film 18. Specifically, a resist or the like is first applied to the entire surface of the passivation film. The resist may be a photoresist, an electron beam resist, an X-ray resist, or the like, and may be either a positive type or a negative type. The resist is applied by spin coating, dipping, spray coating, or the like. Note that pre-baking is performed after the resist is applied. Then, the resist is exposed using a mask in which the pattern of the opening H1 is formed, and further developed to pattern the shape of the opening H1 in the resist. Note that post-baking is performed after resist patterning.

  Then, the passivation film 18 is etched using the patterned resist as a mask. In the present embodiment, the fourth layer of the electrode pad 16 is also etched together with the passivation film 18. For etching, wet etching can be employed, but dry etching is preferably employed. The dry etching may be reactive ion etching (RIE). Note that after the opening H1 is formed in the passivation film 18, the resist on the passivation film 18 is stripped with a stripping solution. As a result, as shown in FIG. 2A, the opening H1 is formed in the passivation film 18, and the electrode pad 16 is exposed.

  Next, as illustrated in FIG. 2B, an opening H <b> 2 is formed in the electrode pad 16. Specifically, a resist or the like is applied to the entire exposed electrode pad 16 and passivation film 18 to pattern the shape of the opening H2. Next, the electrode pad 16 is dry-etched using the patterned resist as a mask. Note that RIE can be used for dry etching. Thereafter, when the resist is peeled off, an opening H2 is formed in the electrode pad 16 as shown in FIG.

Next, as shown in FIG. 2C, an insulating film 20 is formed on the entire upper surface of the substrate 10. The insulating film 20 functions as a mask when the hole H3 is drilled in the substrate 10 by dry etching. The film thickness of the insulating film 20 is set to about 2 μm, for example, depending on the depth of the hole H3 drilled in the substrate 10. In the present embodiment, SiO ₂ is used as the insulating film 20, but a photoresist may be used as long as the selection ratio with Si can be obtained. Further, the insulating film 20 is formed of tetraethyl silicate (Si (OC ₂ H ₅ ) ₄ : hereinafter referred to as TEOS), that is, PE-TEOS formed by PECVD (Plasma Enhanced Chemical Vapor Deposition). Alternatively, O ₃ -TEOS which is thermal CVD using ozone, silicon oxide formed using CVD, or the like can be used.

  Next, the shape of the hole H3 is patterned in the insulating film 20. Specifically, a resist or the like is first applied to the entire surface of the insulating film 20, and the shape of the hole H3 is patterned. Next, the insulating film 20, the interlayer insulating film 14, and the insulating film 12 are dry-etched using the patterned resist as a mask. Thereafter, if the resist is peeled off, the shape of the hole H3 is patterned in the insulating film 20 and the like, and the substrate 10 is exposed.

Next, the hole H3 is drilled in the substrate 10 by high-speed dry etching. Note that RIE or ICP (Inductively Coupled Plasma) can be used as dry etching.
At this time, as described above, the insulating film 20 (SiO ₂ ) is used as a mask, but a resist may be used as a mask instead of the insulating film 20. The depth of the hole H3 is appropriately set according to the thickness of the semiconductor chip to be finally formed. That is, the depth of the hole H3 is set so that the tip of the electrode formed inside the hole H3 can be exposed on the back surface of the substrate 10 after the semiconductor chip is etched to the final thickness. Thus, the hole H3 is formed in the substrate 10 as shown in FIG. A recess H0 is formed from the active surface of the substrate 10 to the inside by the opening H1, the opening H2, and the hole H3.

Next, as illustrated in FIG. 3A, an insulating film 22 that is a first insulating layer is formed on the inner surface of the recess H <b> 0 and the surface of the insulating film 20. The insulating film 22 is made of, for example, PE-TEOS or O ₃ -TEOS, and is formed to have a surface film thickness of about 1 μm by, for example, plasma TEOS.

  Next, anisotropic etching is performed on the insulating film 22 and the insulating film 20 to expose a part of the electrode pad 16. In the present embodiment, a part of the surface of the electrode pad 16 is exposed along the periphery of the opening H2. Specifically, a resist or the like is first applied to the entire surface of the insulating film 22, and the exposed portion is patterned. Next, the insulating film 22 and the insulating film 20 are anisotropically etched using the patterned resist as a mask. For this anisotropic etching, it is preferable to use dry etching such as RIE. As a result, the state shown in FIG.

  Next, as shown in FIG. 3B, a base film 24 is formed on the exposed surface of the electrode pad 16 and the remaining surface of the insulating film 22. As the base film 24, a barrier layer is first formed, and a seed layer is formed thereon. The barrier layer and the seed layer are formed using, for example, a PVD (Physical Vapor Deposition) method such as vacuum evaporation, sputtering, or ion plating, a CVD method, an IMP (ion metal plasma) method, an electroless plating method, or the like.

  Next, as shown in FIG. 4A, an electrode 34 is formed. Specifically, a resist 32 is first applied on the entire upper surface of the substrate 10. As the resist 32, a liquid resist for plating or a dry film can be employed. In addition, although it is possible to use a resist used when etching an Al electrode generally provided in a semiconductor device or an insulating resin resist, it has resistance to a plating solution and an etching solution used in a process described later. That is the premise.

  The resist 32 is applied by a spin coating method, a dipping method, a spray coating method, or the like. Here, the thickness of the resist 32 is set to be approximately the same as the height of the post portion 35 of the electrode 34 to be formed plus the thickness of the solder layer 40. Note that pre-baking is performed after the resist 32 is applied.

  Next, the resist 32 is patterned according to the planar shape of the post portion 35 of the electrode 34 to be formed. Specifically, the resist 32 is patterned by performing exposure processing and development processing using a mask on which a predetermined pattern is formed. Here, if the post portion 35 has a rectangular planar shape, a rectangular opening is patterned in the resist 32. The size of the opening is set according to the pitch of the electrodes 34 in the semiconductor chip, and is formed to have a size of 120 μm square or 80 μm square, for example. Further, the size of the opening is set so that the resist 32 does not fall after patterning.

  The method for forming the resist 32 so as to surround the post portion 35 of the electrode 34 has been described above. However, the resist 32 is not necessarily formed so as to surround the entire circumference of the post portion 35. For example, when the electrodes 34 are formed adjacent to each other only in the left-right direction of the paper surface of FIG. 4A, the resist 32 need not be formed in the depth direction of the paper surface. As described above, the resist 32 is formed along at least a part of the outer shape of the post portion 35.

  In addition, the method for forming the resist 32 using the photolithography technique has been described above. However, when the resist 32 is formed by this method, when the resist is applied to the entire surface, a part of the resist may enter the hole H3 and remain as a residue in the hole H3 even if development processing is performed. Therefore, it is preferable to form the resist 32 in a patterned state by using, for example, a dry film or a printing method such as screen printing. Alternatively, the resist 32 may be formed in a patterned state by discharging a droplet of a resist only to a position where the resist 32 is formed using a droplet discharge device such as an inkjet device. Thereby, the resist 32 can be formed without entering the hole H3.

  Next, using this resist 32 as a mask, the electrode material is filled into the recess H0 to form the electrode. The electrode material is filled by a plating process, a CVD method, or the like. For the plating process, for example, an electrochemical plating (ECP) method is used. Note that a seed layer constituting the base film 24 is used as an electrode in the plating process. Moreover, a cup type plating apparatus is used as the plating apparatus. The cup-type plating apparatus is an apparatus that performs plating by ejecting a plating solution from a cup-shaped container. Thereby, the electrode material is filled in the recess H0, and the plug portion 36 is formed. Further, the opening formed in the resist 32 is also filled with the electrode material, and the post portion 35 is formed.

  Next, a solder layer 40 is formed on the upper surface of the electrode 34. The solder layer 40 is formed by a solder plating method or a printing method such as screen printing. A seed layer constituting the base film 24 can be used as an electrode for solder plating. Moreover, a cup type plating apparatus can be used as the plating apparatus. On the other hand, a hard wax material layer made of SnAg or the like may be formed instead of the solder layer 40. The hard wax material layer can also be formed by a plating method or a printing method. As a result, the state shown in FIG.

Next, as shown in FIG. 4B, the resist 32 is stripped (removed) using a stripping solution or the like.
Note that ozone water or the like can be used as the stripping solution. Subsequently, the base film 24 exposed above the substrate 10 is removed. Specifically, a resist or the like is first applied to the entire upper surface of the substrate 10 and the shape of the post portion 35 of the electrode 34 is patterned. Next, the base film 24 is dry-etched using the patterned resist as a mask. When a hard wax material layer is formed instead of the solder layer 40, the base film 24 can be etched using the hard wax material layer as a mask. In this case, since photolithography is not required, the manufacturing process can be simplified.

  Next, as illustrated in FIG. 5A, the reinforcing member 50 is mounted below the substrate 10 after the substrate 10 is turned upside down. Although a protective film or the like may be employed as the reinforcing member 50, it is preferable to employ a hard material such as glass. Thereby, when processing the back surface 10b of the board | substrate 10, it can prevent that a crack etc. generate | occur | produce in the board | substrate 10. FIG. The reinforcing member 50 is attached to the substrate 10 via an adhesive 52 or the like. As the adhesive 52, it is desirable to use a curable adhesive such as a thermosetting adhesive or a photocurable adhesive. Thereby, the reinforcing member 50 can be firmly attached while absorbing the irregularities on the active surface 10a of the substrate 10. Further, when a photocurable adhesive such as an ultraviolet curable adhesive is used as the adhesive 52, it is preferable to employ a light transmissive material such as glass as the reinforcing member 50. In this case, the adhesive 52 can be easily cured by irradiating light from the outside of the reinforcing member 50.

  Next, as shown in FIG. 5B, the entire back surface 10 b of the substrate 10 is etched to bring the position of the back surface 10 b of the substrate closer to the tip of the electrode 34. In this example, by this etching, the tip of the electrode 34 covered with the insulating film 22 is exposed and the tip is protruded as compared with the back surface 10 b of the substrate 10. At this time, the protruding height of the electrode 34 is, for example, 5 to 10 μm. In this step, wet etching is used. Although wet etching is often inferior in etching accuracy to dry etching, it is advantageous for shortening the processing tact. If the back surface 10b of the substrate 10 is subjected to mechanical polishing such as back grinding and then wet etching is performed to expose the tip of the insulating film 22, the processing tact can be further shortened.

Next, as shown in FIG. 6, a resist film 70 is patterned and formed on the back surface 10 b of the substrate 10 as a mask for reducing the opening area in the next dry etching process.
The specific procedure is as follows. First, a resist is applied to the entire back surface 10b of the substrate 10, and then the resist is patterned by performing exposure processing and development processing using a mask on which a predetermined pattern is formed. Then, a resist film 70 in which a predetermined opening 70a is formed is obtained. The resist needs to be resistant to subsequent dry etching. Pre-baking may be performed after applying the resist. For the application of the resist, various known techniques such as spin coating, dipping, and spray coating can be applied.

  The resist film 70 is patterned according to the planar shape of the post portion 35 of the electrode 34 on the active surface 10a side of the substrate 10. Specifically, patterning is performed so that an opening 70 a having a shape and a size capable of accommodating a part of the post portion 35 is formed in the resist film 70. The formation position of the opening 70b is a position corresponding to the tip of the electrode 34 on the back surface 10b. For alignment at the time of patterning, for example, a double-sided aligner may be used.

Next, as shown in FIG. 7, dry etching is performed on the back surface 10b of the substrate 10 using the resist film 70 as a mask. As the dry etching, the above-described various methods can be used. Further, by using SF ₆ / O ₂ as an etching gas, it is possible to increase the etching rate. When residual sulfur due to SF ₆ becomes a problem, a CF-based etching gas may be used. By the dry etching, a recess 10k having substantially the same planar shape and size as the resist film 70 is formed around the tip of the electrode 34 on the back surface 10b of the substrate 10. Thereafter, as shown in FIG. 8, the resist film 70 is peeled off and removed from the back surface 10 b of the substrate 10.

  Here, at the time of dry etching shown in FIG. 7, the resist film 70 is formed on the back surface 10 b of the substrate 10, so that the etching of the portion masked by the resist film 70 is suppressed, while the resist film 70. The portion of the opening 70a is preferentially etched. Therefore, the etching rate is improved as compared with the whole surface etching in which the entire back surface 10b of the substrate 10 is dry-etched. For example, when the etching opening area is set to 1% or less as compared with the whole surface etching, an improvement in etching rate of about 10 times or more can be expected.

  Further, by improving the etching rate with respect to the back surface 10b of the substrate, the etching selectivity (etching rate of the back surface 10b of the substrate / etching rate of the insulating film 22) is increased, and the etching characteristics are stabilized and the etching time is shortened. As a result, the electrode on the back surface 10b side of the substrate 10 can be exposed with high accuracy and high height. This is advantageous in improving the electrical quality of the manufactured semiconductor chip.

  Next, as shown in FIG. 9, the tip of the electrode 34 is exposed. Specifically, the insulating film 22 and the base film 24 covering the tip of the electrode 34 are removed, and the tip of the electrode 34 is exposed. The insulating film 22 and the base film 24 are removed by dry etching or CMP (Chemical and Mechanical Polishing) polishing. As the dry etching, the above-described various methods can be used. In CMP, the substrate is polished by a balance between mechanical polishing of the substrate by a polishing cloth and chemical action by a polishing liquid supplied thereto. Note that the tip of the electrode 34 may be polished when the insulating film 22 and the base film 24 are removed by polishing. In this case, since the base film 24 is completely removed, it is possible to prevent poor conduction between the electrodes when the semiconductor chips are stacked.

Thereafter, the adhesive 52 is dissolved with a solvent or the like, and the reinforcing member 50 is removed from the substrate 10.
Next, a dicing tape (not shown) is attached to the back surface 10b of the substrate 10, and then the substrate 10 is diced to be separated into individual semiconductor chips. Note that the substrate 10 may be cut by irradiation with CO ₂ laser or YAG laser. Thus, the state shown in FIG. 1 is obtained, and the semiconductor chip 2 according to the present embodiment is completed.

Next, another method for manufacturing the semiconductor chip according to the present embodiment will be described.
This manufacturing method is different from the above manufacturing method in that the etching gas is SF ₆ / O in the step shown in FIG. 7, that is, the step of dry etching the back surface 10b of the substrate 10 using the resist film 70 as a mask. Instead of using ₂ , XeF gas is used.

This XeF gas has a high selection ratio particularly between the semiconductor substrate 10 made of Si and the insulating film 22 made of silicon oxide such as PE-TEOS or O ₃ -TEOS, thereby damaging the insulating film 22. Only the semiconductor substrate 10 can be selectively etched without this. Therefore, the etching rate can be improved without increasing the etching conditions.

Here, the etching using XeF gas as the etching gas is performed by a procedure called pulse etching. In the pulse etching, XeF ₂ gas generated by sublimation is used as XeF gas, and this gas is supplied into the etching chamber until it reaches a desired gas pressure, and the reaction is continued for a certain time. After that, it is a method of repeating the cycle of discarding for a certain time with a dry pump. The pressure in the etching chamber and the sublimation chamber is automatically performed by opening and closing the air drive valve while monitoring the gas pressure with a capacitance pressure gauge.
Note that the etching mechanism of silicon (Si) by XeF ₂ gas is as follows.
2XeF ₂ + Si → 2Xe + SiF ₄

Thus, according to the manufacturing method using XeF gas (XeF ₂ gas) as an etching gas, the etching rate can be improved without increasing the etching conditions, that is, for example, without extremely increasing the etching gas concentration. Therefore, the etching characteristics can be stabilized and the etching time can be shortened.
Also in this manufacturing method, since the resist film 70 is formed on the back surface 10b of the substrate 10 before the back surface of the semiconductor substrate 10 is dry-etched, etching on the portion masked by the resist film 70 is suppressed. On the other hand, the opening 70a portion of the resist film 70 is preferentially etched. Therefore, the etching rate is further improved as compared with the whole surface etching in which the entire back surface 10b of the substrate 10 is dry etched. Therefore, the etching characteristics can be further stabilized and the etching time can be further shortened.

However, in this manufacturing method, a mask made of a resist film 70 as shown in FIG. 6 is formed before dry etching, and dry etching is not performed using this mask, but XeF gas (XeF ₂ gas) is directly used as an etching gas. May be used to etch the entire back surface 10b of the substrate 10 and scrape the periphery of the tip of the electrode 34 so that the tip protrudes relatively.
Even in this case, since XeF gas is used as the etching gas, a high selection ratio can be obtained particularly between the substrate 10 and the insulating film 22 covering the tip of the electrode 34, thereby extremely increasing the etching gas concentration. A sufficient etching rate can be secured without increasing the etching conditions such as.
Therefore, by omitting the mask formation process in this way, the manufacturing process can be simplified, thereby improving the productivity.

  After performing dry etching on the back surface 10b of the substrate 10 in this way, the semiconductor chip is separated into pieces through the steps shown in FIGS. 8 and 9 in the same manner as in the above embodiment, and shown in FIG. A semiconductor chip 2 is obtained.

(Laminated structure)
The semiconductor chips 1 formed as described above are stacked to form the semiconductor device 1 mounted three-dimensionally. FIG. 10 is a side cross-sectional view showing a state in which the semiconductor chips according to the present embodiment are stacked.
Each of the semiconductor chips 2a and 2b is arranged so that the lower end surface of the plug portion of the electrode 34 in the upper semiconductor chip 2a is positioned on the upper surface of the post portion of the electrode 34 in the lower semiconductor chip 2b. Then, the electrodes 34 in the respective semiconductor chips 2a and 2b are joined to each other through the solder layer 40. Specifically, the semiconductor chips 2a and 2b are pressed against each other while the solder layer 40 is dissolved by reflow. As a result, a solder alloy is formed at the joint between the solder layer 40 and the electrode 34, and both are mechanically and electrically joined. Thus, the semiconductor chips 2a and 2b are connected by wiring. If necessary, an underfill is filled in the gaps between the stacked semiconductor chips.

  Here, although the melted solder layer 40 is deformed upward along the outer periphery of the electrode plug portion 36 in the upper semiconductor chip 2a, the recess 10k is formed on the back surface 10b of the semiconductor chip 2a. The solder layer 40 is prevented from coming into contact with other objects. That is, since the recess 10 is formed to have a size capable of accommodating the post portion 35, a sufficient gap is formed between the solder layer 40 and the upper semiconductor chip 2a. As a result, when the semiconductor chips are stacked, it is possible to prevent a short circuit between the solder layer 40 and the back surface 10b of the semiconductor chip 2a. Or mechanical contact (interference) in parts other than an electrode is avoided by the hollow 10k, and electrodes are connected reliably.

  Further, in the semiconductor manufacturing apparatus 1 having this laminated structure, a depression 10k is formed around each electrode 34, and the weight can be reduced correspondingly. In addition, in the back surface of the semiconductor substrate 10, the recess 10k is partial, and even if the substrate thickness at the location of the recess 10k is reduced, the other portions have a predetermined thickness, thereby ensuring the strength of the semiconductor substrate. It is possible enough.

  In the above example, the tip of the electrode 34 (tip of the plug part 36) is protruded compared to the back surface 10b of the substrate 10, but the tip of the electrode 34 is as high as the back surface 10b. Or as shown in FIG. 11, it is good also as a form lower than the back surface 10b.

  As shown in FIG. 11, in the form in which the tip portion (plug portion 36) of the electrode 34 is formed lower than the back surface 10b, when a plurality of semiconductor chips are stacked, the depression of the substrate 10 of the upper semiconductor chip 2a is formed. A part of the electrode 34 (post part, solder layer 40) on the active surface side of the lower semiconductor chip 2a is arranged inside 10k. As a result, the distance between the substrates can be made closer without causing a short circuit. That is, the semiconductor device 1 having a stacked structure can be further downsized.

(Relocation wiring)
In order to mount the semiconductor device stacked as described above on the circuit board, it is desirable to perform rewiring. First, rewiring will be briefly described. FIG. 12 is an explanatory diagram of the rewiring of the semiconductor chip. Since a plurality of electrodes 62 are formed along the opposite side of the surface of the semiconductor chip 61 shown in FIG. 12A, the pitch between adjacent electrodes is narrowed. When such a semiconductor chip 61 is mounted on a circuit board, adjacent electrodes may be short-circuited. Therefore, in order to widen the pitch between the electrodes, rewiring is performed to draw out the plurality of electrodes 62 formed along the opposite sides of the semiconductor chip 61 to the center.

  FIG. 12B is a plan view of the semiconductor chip on which rewiring has been performed. A plurality of circular electrode pads 63 are arranged on the matrix at the center of the surface of the semiconductor chip 61. Each electrode pad 63 is connected to one or a plurality of electrodes 62 by rewiring 64. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion, and the pitch is increased.

  FIG. 13 is a side cross-sectional view taken along line AA in FIG. A solder resist 65 is formed at the center of the bottom surface of the semiconductor chip 61 that is the lowermost layer by inverting the stacked semiconductor device as described above. A rewiring 64 is formed from the post portion of the electrode 62 to the surface of the solder resist 65. An electrode pad 63 is formed at the end of the rewiring 64 on the solder resist 65 side, and a bump 78 is formed on the surface of the electrode pad. The bump 78 is, for example, a solder bump and is formed by a printing method or the like. A reinforcing resin 66 and the like are molded on the entire bottom surface of the semiconductor chip 61.

(Circuit board)
FIG. 14 is a perspective view of a circuit board. In FIG. 14, the semiconductor device 1 formed by stacking semiconductor chips is mounted on a circuit board 1000. Specifically, bumps formed on the lowermost semiconductor chip in the semiconductor device 1 are mounted by performing reflow, FCB (Flip Chip Bonding), or the like on the electrode pads formed on the surface of the circuit board 1000. Has been. The semiconductor device 1 may be mounted with an anisotropic conductive film or the like sandwiched between the circuit board.

(Electronics)
Next, an example of an electronic device including the above-described semiconductor device is described with reference to FIGS.
FIG. 15 is a perspective view of a mobile phone. The semiconductor device described above is arranged inside the housing of the mobile phone 300.

  Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

  It should be noted that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Examples of electronic components manufactured using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but it goes without saying that the present invention is not limited to such examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

Side surface sectional drawing of the electrode part of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. Explanatory drawing of the manufacturing method of a semiconductor chip. 3 is an explanatory diagram of a stacked state of a semiconductor device. Explanatory drawing of the other example of the lamination | stacking state of a semiconductor device. Explanatory drawing of rewiring. Explanatory drawing of rewiring. An explanatory view of a circuit board. The perspective view of the mobile telephone which is an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device (laminated structure), 2 ... Semiconductor chip (semiconductor device), 10 ... Semiconductor substrate, 10k ... Depression, 34 ... Electrode, 35 ... Post part, 36 ... Plug part, 40 ... Solder layer,
70: Resist film

Claims (14)

A method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate,
Forming a recess from the active surface of the semiconductor substrate on which the integrated circuit is formed to the inside of the semiconductor substrate;
Forming an insulating layer on the inner surface of the recess;
Filling the inside of the insulating layer with a conductive material to form an electrode;
Dry etching the back surface of the semiconductor substrate to expose the tip of the electrode;
Removing the insulating layer at the tip of the electrode to expose the tip of the electrode,
A method of manufacturing a semiconductor device, comprising: forming a film for reducing an etching opening area on a back surface of the semiconductor substrate before dry etching the back surface of the semiconductor substrate. A method of manufacturing a semiconductor device having an electrode penetrating a semiconductor substrate,
Forming a recess from the active surface of the semiconductor substrate on which the integrated circuit is formed to the inside of the semiconductor substrate;
Forming an insulating layer on the inner surface of the recess;
Filling the inside of the insulating layer with a conductive material to form an electrode;
Dry etching the back surface of the semiconductor substrate to expose the tip of the electrode;
Removing the insulating layer at the tip of the electrode to expose the tip of the electrode,
A method of manufacturing a semiconductor device, wherein XeF gas is used as an etching gas when dry-etching the back surface of the semiconductor substrate.   3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a film for reducing an etching opening area on the back surface of the semiconductor substrate before dry etching the back surface of the semiconductor substrate.   The method of manufacturing a semiconductor device according to claim 1, wherein the film has an opening at a position corresponding to a tip portion of the electrode.   The method for manufacturing a semiconductor device according to claim 4, wherein the opening of the film has a shape determined in accordance with a shape of another electrode connected to a tip portion of the electrode.   6. The step of forming the film includes a step of forming a resist film on a back surface of the semiconductor substrate, and a step of patterning the resist film to form the opening. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   6. The method according to claim 1, further comprising: wet-etching the back surface of the semiconductor substrate before forming the film so that the position of the back surface of the semiconductor substrate approaches the tip of the electrode. Or a manufacturing method of the semiconductor device according to any one of 6 and 6. A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1. A semiconductor substrate on which an integrated circuit is formed;
An electrode formed through an insulating layer inside a through-hole formed from the active surface of the semiconductor substrate to the back surface of the semiconductor substrate;
A recess is formed around the electrode on the back surface of the semiconductor substrate.   The semiconductor device according to claim 9, wherein a shape of a recess on a back surface of the semiconductor substrate is determined according to a shape of another electrode connected to the electrode.   11. The semiconductor device according to claim 10, wherein at least a part of another electrode connected to the electrode is disposed inside a recess on a back surface of the semiconductor substrate. A plurality of the semiconductor devices according to any one of claims 8 to 11 are stacked, and the electrodes of the semiconductor devices adjacent in the vertical direction are electrically connected via solder or a wax material. Semiconductor device. A circuit board on which the semiconductor device according to claim 12 is mounted. An electronic apparatus comprising the semiconductor device according to claim 12.

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