JP2006041148A - Method for manufacturing semiconductor device, semiconductor device, and electronic apparatus - Google Patents

Method for manufacturing semiconductor device, semiconductor device, and electronic apparatus Download PDF

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JP2006041148A
JP2006041148A JP2004218274A JP2004218274A JP2006041148A JP 2006041148 A JP2006041148 A JP 2006041148A JP 2004218274 A JP2004218274 A JP 2004218274A JP 2004218274 A JP2004218274 A JP 2004218274A JP 2006041148 A JP2006041148 A JP 2006041148A
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hole
semiconductor device
connection terminal
substrate
etching
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Takehide Matsuo
剛秀 松尾
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Seiko Epson Corp
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Seiko Epson Corp
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device in which high reliability can be ensured by the high-bonding strength of a stacked semiconductor chip, and to provide a semiconductor device and an electronic apparatus comprising the semiconductor device. <P>SOLUTION: The method for manufacturing a semiconductor device comprises a step for forming a first hole H3 from the active surface 10a of a semiconductor substrate 10 toward the interior thereof, a step for forming a first connection terminal 20 by filling the inside of the first hole H3 with a conductive material, a step for forming a second hole H6 reaching the bottom face of the first hole H3 from the rear surface 10b of the semiconductor substrate 10 on the side opposite to the active surface 10a, and a step for forming a second connection terminal 21 by filling the inside of the second hole H6 with a conductive material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置の製造方法、半導体装置、及びこれを備える電子機器に関する。   The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and an electronic apparatus including the same.

現在、携帯電話機、ノート型パーソナルコンピュータ、ＰＤＡ（Personal data assistance）等の携帯性を有する電子機器、センサ、マイクロマシン、及びプリンタヘッド等の機器の小型・軽量化を図るため、その内部に設けられる半導体チップ等の各種の電子部品を小型化する研究・開発が盛んに行われている。また、上記の電子機器は付加価値を高めるため高機能化が図られており内部に設けられる電子部品も高機能化及び高速化が要求されている。
高機能を有する電子部品の一つとしてシステムＬＳＩ（Large Scale Integration）があるが、システムＬＳＩを製品化するには時間を要するため近年の電子機器の開発サイクルに間に合わない状況も生じつつある。そこで、システムＬＳＩが有する複数の機能のうちの各々の機能を１つのＩＣ（Integrated Circuit）に持たせ、これらのＩＣを組み合わせて１つのパッケージングのシステムＬＳＩを実現するＳＩＰ（System In Package）技術が案出されている。 Currently, in order to reduce the size and weight of portable electronic devices such as mobile phones, notebook personal computers, PDAs (Personal data assistance), sensors, micromachines, printer heads, etc., semiconductors provided therein Research and development to reduce the size of various electronic parts such as chips are actively conducted. In addition, the above-described electronic devices are highly functional in order to increase added value, and the electronic components provided inside are also required to have high functionality and high speed.
There is a system LSI (Large Scale Integration) as one of high-functional electronic components. However, since it takes time to commercialize the system LSI, there is a situation that is not in time for the development cycle of electronic devices in recent years. Therefore, SIP (System In Package) technology for realizing each of a plurality of functions of a system LSI in one IC (Integrated Circuit) and combining these ICs to realize one packaging system LSI. Has been devised.

ＳＩＰ技術においては三次元的に複数のＩＣを積層することで高集積化を図っているが、積層されたＩＣをシステムＬＳＩとして機能させるには各々の電気的接続を取る必要がある。従来は各ＩＣに形成された電極をワイヤーボンディング技術を用いて電気的に接続していたが、ワイヤーボンディングによる接続では配線長が長くなるとともに、パッケージングの小型化に限度がある。
このため、ＩＣの裏面に対してエッチング処理又は研磨処理を行ってＩＣを薄板化するとともに、ＩＣの表面と裏面とを貫通する金属からなる接続端子を形成し、積層するＩＣに形成された接続部を接合することで、ＩＣ間の電気的接続をとる三次元実装技術が案出されてきた。この三次元実装技術の詳細については、例えば以下の特許文献１を参照されたい。
特開２００２−２５９４８号公報 In the SIP technology, high integration is achieved by stacking a plurality of ICs three-dimensionally. However, in order for the stacked ICs to function as a system LSI, it is necessary to establish electrical connections. Conventionally, the electrodes formed in each IC are electrically connected using wire bonding technology. However, connection by wire bonding increases the wiring length and limits the miniaturization of packaging.
For this reason, etching or polishing is performed on the back surface of the IC to thin the IC, and a connection terminal made of metal penetrating the front and back surfaces of the IC is formed, and the connection formed on the stacked ICs A three-dimensional mounting technique has been devised in which electrical connections between ICs are made by joining parts. For details of this three-dimensional mounting technique, see, for example, Patent Document 1 below.
JP 2002-25948 A

ところで、上述した三次元実装技術を用いてＩＣを積層して製造される電子部品は最終的には封止樹脂にて封止されており、ある程度の信頼性を確保することはできる。しかしながら、電子部品が携帯性を有する電子機器に搭載される場合には、外部からの強い振動及び衝撃が加わることが想定されるため、より高い堅牢性を確保する必要がある。このため、電子部品の更なる信頼性の向上を図るためには各ＩＣに形成された接続端子間の接合強度を高める必要がある。
三次元実装技術を用いて製造された従来の電子部品は、ＩＣに形成された接続端子の先端部（他のＩＣと接合される部分）が通常平坦な形状になっているため、積層されたＩＣの接続端子間は二次元的に接合された状態にあり、接合強度が低く信頼性が低いという問題があった。
また、半導体基板全面にエッチングを施して半導体基板の裏面に接続端子の先端を露出させるために、絶縁膜を厚膜化する等の特別な処理が必要となり、半導体装置の製造方法が煩雑化するという問題があった。 By the way, an electronic component manufactured by stacking ICs using the above-described three-dimensional mounting technique is finally sealed with a sealing resin, and a certain degree of reliability can be ensured. However, when the electronic component is mounted on an electronic device having portability, it is assumed that strong vibration and impact from the outside are applied, so it is necessary to ensure higher robustness. For this reason, in order to further improve the reliability of the electronic component, it is necessary to increase the bonding strength between the connection terminals formed in each IC.
Conventional electronic parts manufactured using three-dimensional mounting technology are laminated because the tip of the connection terminal formed on the IC (the part to be joined with other ICs) is usually flat. There is a problem that the connection terminals of the IC are two-dimensionally bonded, and the bonding strength is low and the reliability is low.
Further, in order to etch the entire surface of the semiconductor substrate and expose the tip of the connection terminal on the back surface of the semiconductor substrate, a special process such as thickening the insulating film is required, which complicates the manufacturing method of the semiconductor device. There was a problem.

本発明は、上述した事情に鑑みてなされたもので、積層された半導体チップの接合強度が高く、これにより高い信頼性を確保することができる半導体装置の製造方法及び半導体装置、並びに当該半導体装置を備える電子機器を提供することを目的とする。   The present invention has been made in view of the above-described circumstances. A semiconductor device manufacturing method, a semiconductor device, and a semiconductor device capable of ensuring high reliability due to high bonding strength of stacked semiconductor chips, and the semiconductor device. An object of the present invention is to provide an electronic device including the above.

本発明に係る半導体装置の製造方法、半導体装置、及び電子機器では、上記課題を解決するために以下の手段を採用した。
第１の発明は、半導体基板の能動面から半導体基板の内部にかけて第一孔部を形成する工程と、第一孔部の内側に導電材料を充填して第一接続端子を形成する工程と、半導体基板の能動面とは反対側の裏面から第一孔部の底面に到達する第二孔部を形成する工程と、第二孔部の内面に導電材料を充填して第二接続端子を形成する工程と、を有するようにした。
この発明によれば、裏面側にも接続端子が形成される裏面側に露出させる電極の露出量を容易に高くすることができる。これにより、半導体基板を複数積層した場合に各電極の接合状態を良好に維持することが可能となる。 The semiconductor device manufacturing method, semiconductor device, and electronic apparatus according to the present invention employ the following means in order to solve the above-described problems.
The first invention includes a step of forming a first hole from the active surface of the semiconductor substrate to the inside of the semiconductor substrate, a step of filling the inside of the first hole with a conductive material to form a first connection terminal, Forming a second hole reaching the bottom surface of the first hole from the back surface opposite to the active surface of the semiconductor substrate, and forming a second connection terminal by filling the inner surface of the second hole with a conductive material And a step of performing.
According to this invention, the exposure amount of the electrode exposed on the back surface side where the connection terminal is formed also on the back surface side can be easily increased. As a result, when a plurality of semiconductor substrates are stacked, the bonding state of each electrode can be maintained satisfactorily.

また、第一接続端子の形成に先立って第一孔部の内面に第一絶縁膜を形成する工程と、第二接続端子の形成に先立って第二孔部の内面に第一絶縁膜に連接する第二絶縁膜を形成する工程と、を有するものでは、半導体基板に導電性材料が用いられた場合であっても、半導体基板を貫通する電極を形成することができる。そして、容易に電極の露出量を高くすることができるので、絶縁膜の厚膜化が不要となる。
また、第一接続端子と第二接続端子とは、略同一形状に形成されるものでは、半導体基板を複数積層した場合に、各接続端子の接合状態を容易に良好にすることができる。さらに、接合時の熱上昇に対して導電材料が膨張することに起因する絶縁膜の破損防止が可能となる。 A step of forming a first insulating film on the inner surface of the first hole portion prior to the formation of the first connection terminal; and a step of connecting the first insulating film to the inner surface of the second hole portion prior to the formation of the second connection terminal. The step of forming the second insulating film is capable of forming an electrode penetrating the semiconductor substrate even when a conductive material is used for the semiconductor substrate. And since the exposure amount of an electrode can be easily made high, it becomes unnecessary to thicken an insulating film.
In addition, the first connection terminal and the second connection terminal are formed in substantially the same shape. When a plurality of semiconductor substrates are stacked, the connection state of each connection terminal can be easily improved. Furthermore, it is possible to prevent the insulating film from being damaged due to the expansion of the conductive material with respect to the heat rise during bonding.

第２の発明は、半導体装置が、第１の発明の製造方法を使用して製造されるようにした。この発明によれば、半導体基板を貫通する各電極の接合状態を向上が図られる。   In the second invention, the semiconductor device is manufactured using the manufacturing method of the first invention. According to the present invention, the bonding state of each electrode penetrating the semiconductor substrate can be improved.

また、集積回路が形成された半導体基板と、半導体基板の能動面から半導体基板の裏面にかけて形成された貫通孔の内部に絶縁層を介して形成された電極と、を有してなり、電極が、能動面側と裏面側にそれぞれ略同一形状の接続端子を備えるようにした。
この発明によれば、裏面側にも電極が形成するので、裏面側に露出させる電極の露出量を容易に高くすることができる。これにより、半導体基板を複数積層した場合に各電極の接合状態を良好に維持することが可能となる。
例えば、上述した半導体装置は、複数積層され、上下に隣接する半導体装置の接続端子がハンダまたは蝋材を介して電気的に接続された形態となって使用される。 A semiconductor substrate on which an integrated circuit is formed; and an electrode formed through an insulating layer in a through hole formed from the active surface of the semiconductor substrate to the back surface of the semiconductor substrate. The active surface side and the back surface side are each provided with connection terminals having substantially the same shape.
According to this invention, since the electrode is formed also on the back surface side, the exposure amount of the electrode exposed on the back surface side can be easily increased. As a result, when a plurality of semiconductor substrates are stacked, the bonding state of each electrode can be maintained satisfactorily.
For example, the semiconductor device described above is used in a form in which a plurality of semiconductor devices are stacked and the connection terminals of the semiconductor devices adjacent in the vertical direction are electrically connected via solder or wax material.

第３の発明は、回路基板が、第２の発明の半導体装置が実装されていることを特徴とする。これにより、上記効果をともなった回路基板を提供することができる。   The third invention is characterized in that the circuit board is mounted with the semiconductor device of the second invention. Thereby, the circuit board with the said effect can be provided.

第４の発明は、電子機器が、第２の発明の回路基板を備えたことを特徴とする。これにより、上記効果をともなった電子機器を提供することができる。   According to a fourth aspect of the invention, an electronic apparatus includes the circuit board according to the second aspect of the invention. Thereby, the electronic device with the said effect can be provided.

以下、本発明の半導体装置の製造方法、半導体装置、及び電子機器の実施形態について、図を参照して説明する。
〔半導体装置の製造方法〕
図１〜図８は、本発明の実施形態による半導体装置の製造方法を示す工程図である。
図１（ａ）に示すように、基板１０は、例えばＳｉ（シリコン）基板であり、その能動面１０ａ側にトランジスタ、メモリ素子、その他の電子素子、並びに電気配線（何れも図示省略）及び電子回路の外部電極となる電極パッド１４からなる電子回路が形成されている。一方、基板１０の裏面１０ｂにはこれらの電子回路は形成されていない。尚、基板１０の厚みは、例えば５００μｍ程度である。 Hereinafter, embodiments of a method for manufacturing a semiconductor device, a semiconductor device, and an electronic apparatus according to the present invention will be described with reference to the drawings.
[Method for Manufacturing Semiconductor Device]
1 to 8 are process diagrams showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in FIG. 1A, the substrate 10 is, for example, a Si (silicon) substrate, and on its active surface 10a side, a transistor, a memory element, other electronic elements, electrical wiring (all not shown), and an electron An electronic circuit composed of electrode pads 14 serving as external electrodes of the circuit is formed. On the other hand, these electronic circuits are not formed on the back surface 10 b of the substrate 10. The thickness of the substrate 10 is, for example, about 500 μm.

基板１０上には基板１０の基本的な材料であるＳｉの酸化膜（ＳｉＯ２）からなる絶縁膜と硼燐珪酸ガラス（ＢＰＳＧ）からなる層間絶縁膜とを順に形成した絶縁膜１２が形成されている。また、絶縁膜１２上の一部には、図示しない箇所で基板１０の能動面１０ａに形成された電子回路と電気的に接続された電極パッド１４が形成されている。この電極パッド１４は、Ｔｉ（チタン）からなる第１層、ＴｉＮ（窒化チタン）からなる第２層、ＡｌＣｕ（アルミニウム／銅）からなる第３層、及びＴｉＮからなる第４層（キャップ層）を順に積層して形成したものである。尚、電極パッド１４の下方には電子回路が形成されていない点に注意されたい。 An insulating film 12 is formed on the substrate 10 by sequentially forming an insulating film made of a Si oxide film (SiO 2 ), which is a basic material of the substrate 10, and an interlayer insulating film made of borophosphosilicate glass (BPSG). ing. In addition, an electrode pad 14 electrically connected to an electronic circuit formed on the active surface 10a of the substrate 10 is formed on a part of the insulating film 12 at a location not shown. The electrode pad 14 includes a first layer made of Ti (titanium), a second layer made of TiN (titanium nitride), a third layer made of AlCu (aluminum / copper), and a fourth layer made of TiN (cap layer). Are sequentially laminated. It should be noted that no electronic circuit is formed below the electrode pad 14.

電極パッド１４は、例えばスパッタリングにより第１層〜第４層からなる積層構造を絶縁膜１２上の全面に形成し、レジスト等を用いて所定の形状（例えば、円形形状）にパターニングすることにより形成される。尚、本実施形態では、電極パッド１４が上記の積層構造により形成されている場合を例に挙げて説明するが、電極パッド１４がＡｌのみで形成されていても良いが、電気抵抗の低い銅を用いて形成することが好ましい。また、電極パッド１４は、上記の構成に限られず、必要とされる電気的特性、物理的特性、及び化学的特性に応じて適宜変更しても良い。   The electrode pad 14 is formed by, for example, forming a laminated structure composed of first to fourth layers on the entire surface of the insulating film 12 by sputtering, and patterning it into a predetermined shape (for example, a circular shape) using a resist or the like. Is done. In the present embodiment, the case where the electrode pad 14 is formed by the above laminated structure will be described as an example. However, although the electrode pad 14 may be formed of only Al, copper having low electrical resistance is used. It is preferable to form using. In addition, the electrode pad 14 is not limited to the above-described configuration, and may be appropriately changed according to required electrical characteristics, physical characteristics, and chemical characteristics.

また、上記絶縁膜１２上には電極パッド１４を覆うように、パッシベーション膜１６が形成されている。このパッシベーション膜１６は、ＳｉＯ２（酸化珪素）、ＳｉＮ（窒化珪素）、ポリイミド樹脂等により形成され、又はＳｉＮ上にＳｉＯ２を積層した構成、あるいはその逆であることが好ましい。また、パッシベーション膜１６の膜厚は２μｍ程度以上であって６μｍ程度以下であることが好ましい。 Further, a passivation film 16 is formed on the insulating film 12 so as to cover the electrode pad 14. The passivation film 16 is preferably formed of SiO 2 (silicon oxide), SiN (silicon nitride), polyimide resin, or the like, or a structure in which SiO 2 is stacked on SiN, or vice versa. The thickness of the passivation film 16 is preferably about 2 μm or more and about 6 μm or less.

以上の構成の基板に対して、まず能動面１０ａ側に形成された電極パッド１４を開口するとともに基板１０を穿孔して孔部Ｈ３を形成する工程が行われる。まず、スピンコート法、ディッピング法、スプレーコート法等の方法によりレジスト（図示省略）をパッシベーション膜１６上の全面に塗布する。尚、このレジストは、電極パッド１４上を覆っているパッシベーション膜１６を開口するために用いるものであり、フォトレジスト、電子線レジスト、Ｘ線レジストの何れであってもよく、ポジ型又はネガ型の何れであってもよい。   First, a step of opening the electrode pad 14 formed on the active surface 10a side and drilling the substrate 10 to form the hole H3 is performed on the substrate having the above configuration. First, a resist (not shown) is applied on the entire surface of the passivation film 16 by a method such as spin coating, dipping, or spray coating. This resist is used for opening the passivation film 16 covering the electrode pad 14, and may be any of a photoresist, an electron beam resist, and an X-ray resist, and is a positive type or a negative type. Any of these may be used.

パッシベーション膜１６上にレジストを塗布すると、プリベークを行った後で、所定のパターンが形成されたマスクを用いて露光処理及び現像処理を行い、レジストを所定形状にパターニングする。尚、レジストの形状は、電極パッド１４の開口形状及び基板１０に形成する孔の断面形状に応じて設定される。レジストのパターニングが終了すると、ポストベークを行った後で、図１（ｂ）に示すように、電極パッド１４を覆うパッシベーション膜１６の一部をエッチングして開口部Ｈ１を形成する。なお、図１（ｂ）は、パッシベーション膜１６を開口して開口部Ｈ１を形成した状態を示す断面図である。   When a resist is applied on the passivation film 16, after pre-baking, exposure and development are performed using a mask on which a predetermined pattern is formed, and the resist is patterned into a predetermined shape. The shape of the resist is set according to the opening shape of the electrode pad 14 and the cross-sectional shape of the hole formed in the substrate 10. When the resist patterning is completed, after the post-baking, as shown in FIG. 1B, a part of the passivation film 16 covering the electrode pad 14 is etched to form an opening H1. FIG. 1B is a cross-sectional view showing a state in which the passivation film 16 is opened to form an opening H1.

尚、パッシベーション膜１６のエッチングにはドライエッチングを適用することが好ましい。ドライエッチングは、反応性イオンエッチング（ＲＩＥ：Reactive Ion Etching）であってもよい。また、パッシベーション膜１６のエッチングとしてウェットエッチングを適用してもよい。パッシベーション膜１６に形成される開口部Ｈ１の断面形状は、後述する工程で形成される電極パッド１４の開口形状及び基板１０に形成される孔の断面形状に応じて設定され、その径は電極パッド１４に形成される開口の径及び基板１０に形成される孔の径と同程度、例えば５０μｍ程度に設定される。   Note that dry etching is preferably applied to the etching of the passivation film 16. The dry etching may be reactive ion etching (RIE). Further, wet etching may be applied as the etching of the passivation film 16. The cross-sectional shape of the opening H1 formed in the passivation film 16 is set according to the opening shape of the electrode pad 14 formed in the process described later and the cross-sectional shape of the hole formed in the substrate 10, and its diameter is the electrode pad. 14 and the diameter of the hole formed in the substrate 10, for example, about 50 μm.

以上の工程が終了すると、開口部Ｈ１を形成したパッシベーション膜１６上のレジストをマスクとして、ドライエッチングにより電極パッド１４を開口する。
図２（ａ）は、電極パッド１４を開口して開口部Ｈ２を形成した状態を示す断面図である。尚、図１，図２の図中においてレジストは省略してある。図２（ａ）に示すように、パッシベーション膜１６に形成された開口部Ｈ１の径と電極パッド１４に形成された開口部Ｈ２の径は同程度となる。尚、ドライエッチングとしてはＲＩＥを用いることができる。 When the above steps are completed, the electrode pad 14 is opened by dry etching using the resist on the passivation film 16 in which the opening H1 is formed as a mask.
FIG. 2A is a cross-sectional view showing a state in which the electrode pad 14 is opened to form the opening H2. In FIGS. 1 and 2, the resist is omitted. As shown in FIG. 2A, the diameter of the opening H1 formed in the passivation film 16 and the diameter of the opening H2 formed in the electrode pad 14 are approximately the same. Note that RIE can be used as the dry etching.

更に、以上の工程で使用したレジストをマスクとして、次に絶縁膜１２をエッチングして、図２（ｂ）に示すように基板１０を露出させる。図２（ｂ）は、絶縁膜１２をエッチングして、基板１０の一部を露出させた状態を示す断面図である。この後、開口マスクとして使用してきたパッシベーション膜１６上に形成したレジストを、剥離液或いはアッシング等により剥離する。   Further, using the resist used in the above steps as a mask, the insulating film 12 is then etched to expose the substrate 10 as shown in FIG. FIG. 2B is a cross-sectional view showing a state in which the insulating film 12 is etched and a part of the substrate 10 is exposed. Thereafter, the resist formed on the passivation film 16 that has been used as the opening mask is removed by a remover or ashing.

尚、上記プロセスにおいては、同一のレジストマスクを用いてエッチングを繰り返したが、各エッチング工程終了後、レジストをパターニングし直しても勿論良い。また、電極パッド１４に形成された開口部Ｈ２を開口した後レジストを剥離し、電極パッド１４の最表面のＴｉＮをマスクにして、絶縁膜１２をエッチングし、図２（ｂ）に示すように基板１０を露出せしめることも可能である。更に付け加えるならば、各エッチング時の選択比を考慮して、レジストを厚膜化しておくことが必要である。   In the above process, the etching is repeated using the same resist mask. However, the resist may be patterned again after each etching step. Further, after opening the opening H2 formed in the electrode pad 14, the resist is peeled off, and the insulating film 12 is etched using the outermost surface TiN of the electrode pad 14 as a mask, as shown in FIG. It is also possible to expose the substrate 10. In addition, it is necessary to increase the thickness of the resist in consideration of the selectivity during each etching.

以上の工程が終了すると、パッシベーション膜１６をマスクとして、ドライエッチングにより基板１０を穿孔して孔部Ｈ３（第一孔部）を形成する（第一孔部形成工程）。
基板１０を穿孔する深さは例えば７０μｍ程度であるため、製造効率の観点からは特開２００２−９３７７６号公報に開示されたＳｉ高速エッチング法、又は米国特許ＵＳＰ５５０１８９３に開示されたボッシュプロセス法を用いて異方性エッチングを行うことが好ましい。Ｓｉ高速エッチング法を用いる場合には、エッチングガスとしてＳＦ６／Ｏ２の混合ガスを用いることができ、ボッシュプロセス法を用いる場合にはＳＦ６／Ｃ４Ｆ８を用いることができる。尚、ここでは、ドライエッチングとしてＲＩＥのほかにＩＣＰ（Inductively Coupled Plasma）を用いることができる。 When the above steps are completed, the substrate 10 is drilled by dry etching using the passivation film 16 as a mask to form a hole H3 (first hole) (first hole forming step).
Since the depth of drilling the substrate 10 is about 70 μm, for example, from the viewpoint of manufacturing efficiency, the Si high-speed etching method disclosed in Japanese Patent Application Laid-Open No. 2002-93776 or the Bosch process method disclosed in US Pat. No. 5,501,893 is used. It is preferable to perform anisotropic etching. When the Si high-speed etching method is used, a mixed gas of SF 6 / O 2 can be used as the etching gas, and when the Bosch process method is used, SF 6 / C 4 F 8 can be used. Here, in addition to RIE, ICP (Inductively Coupled Plasma) can be used as dry etching.

図３（ａ）は、基板１０を穿孔して、孔部Ｈ３を形成した状態を示す断面図である。図３（ａ）に示す通り、パッシベーション膜１６をマスクとして基板１０を穿孔しているため、基板１０に形成される孔部Ｈ３の径はパッシベーション膜１６に形成された開口部Ｈ１の径と同程度となる。その結果、パッシベーション膜１６に形成された開口部Ｈ１の径、電極パッド１４に形成された開口部Ｈ２の径、及び基板１０に形成された孔部Ｈ３の径は、ほぼ同一になる。尚、孔部Ｈ３の深さは、最終的に形成する半導体チップの厚みに応じて適宜設定される。また、孔部Ｈ３は異方性エッチングにより形成しているため、孔部Ｈ３の底面は平坦な（フラット）形状になる。   FIG. 3A is a cross-sectional view showing a state in which the hole 10 is formed by drilling the substrate 10. As shown in FIG. 3A, since the substrate 10 is punched using the passivation film 16 as a mask, the diameter of the hole H3 formed in the substrate 10 is the same as the diameter of the opening H1 formed in the passivation film 16. It will be about. As a result, the diameter of the opening H1 formed in the passivation film 16, the diameter of the opening H2 formed in the electrode pad 14, and the diameter of the hole H3 formed in the substrate 10 are substantially the same. The depth of the hole H3 is appropriately set according to the thickness of the semiconductor chip to be finally formed. Further, since the hole H3 is formed by anisotropic etching, the bottom surface of the hole H3 has a flat shape.

尚、以上は、異方性エッチングから等方性エッチングに変更する方法としてエッチングガスの成分を変更する方法について説明したが、エッチングガスの成分変更に加えてバイアス電圧を低下させ、又は、エッチングガスの高圧化を行って異方性エッチングを等方性エッチングに変更するようにしても良い。また、バイアス電圧を低下させ、又は、エッチングガスの高圧化のみによって変更しても良い。   In the above, the method of changing the etching gas component as a method of changing from anisotropic etching to isotropic etching has been described. However, in addition to changing the etching gas component, the bias voltage is lowered or the etching gas is changed. The anisotropic etching may be changed to isotropic etching by increasing the pressure. Further, the bias voltage may be lowered or changed only by increasing the pressure of the etching gas.

以上の工程が終了すると、次に、パッシベーション膜１６上並びに孔部Ｈ３の内壁及び底面に第一絶縁膜１８を形成する（第一絶縁膜形成工程）。
図３（ｂ）は、パッシベーション膜１６上並びに孔部Ｈ３の内壁及び底面に第一絶縁膜１８を形成した状態を示す断面図である。この第一絶縁膜１８は、電流リークの発生、酸素及び水分等による基板１０の浸食等を防止するために設けられ、ＰＥＣＶＤ（Plasma Enhanced Chemical Vapor Deposition）を用いて形成した正珪酸四エチル（Tetra Ethyl Ortho Silicate：Ｓｉ（ＯＣ２Ｈ５）４：以下、ＴＥＯＳという）、即ちＰＥ−ＴＥＯＳ、及び、オゾンＣＶＤを用いて形成したＴＥＯＳ、即ちＯ３−ＴＥＯＳ、又はＣＶＤを用いて形成した酸化シリコンを用いることができる。尚、第一絶縁膜１８の厚みは、例えば１μｍである。 When the above steps are completed, a first insulating film 18 is then formed on the passivation film 16 and on the inner wall and bottom surface of the hole H3 (first insulating film forming step).
FIG. 3B is a cross-sectional view showing a state in which the first insulating film 18 is formed on the passivation film 16 and on the inner wall and bottom surface of the hole H3. This first insulating film 18 is provided to prevent the occurrence of current leakage, erosion of the substrate 10 due to oxygen, moisture, etc., and is formed by using tetraethyl silicate (Tetra) formed by PECVD (Plasma Enhanced Chemical Vapor Deposition). Ethyl Ortho Silicate: Si (OC 2 H 5 ) 4 : hereinafter referred to as TEOS), that is, PE-TEOS, and TEOS formed by using ozone CVD, that is, silicon oxide formed by using O 3 -TEOS, or CVD. Can be used. Note that the thickness of the first insulating film 18 is, for example, 1 μm.

続いて、スピンコート法、ディッピング法、スプレーコート法等の方法によりレジスト（図示省略）を第一絶縁膜１８上の全面に塗布する。或いは、ドライフィルムレジストを用いても良い。尚、このレジストは、電極パッド１４の一部の上方を開口するために用いるものであり、フォトレジスト、電子線レジスト、Ｘ線レジストの何れであってもよく、ポジ型又はネガ型の何れであってもよい。   Subsequently, a resist (not shown) is applied on the entire surface of the first insulating film 18 by a method such as spin coating, dipping, or spray coating. Alternatively, a dry film resist may be used. This resist is used to open an upper part of the electrode pad 14, and may be any of a photoresist, an electron beam resist, and an X-ray resist, either a positive type or a negative type. There may be.

第一絶縁膜１８上にレジストを塗布すると、プリベークを行った後で、所定のパターンが形成されたマスクを用いて露光処理及び現像処理を行い、電極パッド１４の上方以外の部分並びに孔部Ｈ３及びその周辺部のみにレジストが残された形状、例えば孔部Ｈ３を中心とした円環形状にレジストをパターニングする。レジストのパターニングが終了すると、ポストベークを行った後で、エッチングにより電極パッド１４の一部を覆う第一絶縁膜１８及びパッシベーション膜１６を除去し、電極パッド１４の一部を開口する。尚、エッチングにはドライエッチングを適用することが好ましい。ドライエッチングは、反応性イオンエッチング（ＲＩＥ：Reactive Ion Etching）であってもよい。また、エッチングとしてウェットエッチングを適用してもよい。尚、このとき、電極パッド１４を構成する第４層も併せて除去する。   When a resist is applied on the first insulating film 18, after pre-baking, exposure processing and development processing are performed using a mask on which a predetermined pattern is formed, and portions other than those above the electrode pad 14 and the hole H3. Then, the resist is patterned into a shape in which the resist is left only in the peripheral portion thereof, for example, an annular shape centering on the hole H3. After the resist patterning is completed, after the post-baking, the first insulating film 18 and the passivation film 16 covering a part of the electrode pad 14 are removed by etching, and a part of the electrode pad 14 is opened. Note that dry etching is preferably applied to the etching. The dry etching may be reactive ion etching (RIE). Further, wet etching may be applied as etching. At this time, the fourth layer constituting the electrode pad 14 is also removed.

図４（ａ）は、電極パッド１４を覆う第一絶縁膜１８及びパッシベーション膜１６の一部を除去した状態を示す断面図である。図４（ａ）に示すように、電極パッド１４の上方は開口部Ｈ４となり、電極パッド１４の一部が露出した状態となる。この開口部Ｈ４によって、後の工程で形成される第一接続端子２０と電極パッド１４とを接続することができる。従って、開口部Ｈ４は孔部Ｈ３が形成された部位以外の部位に形成されていればよい。また、隣接していても良い。   FIG. 4A is a cross-sectional view showing a state in which a part of the first insulating film 18 and the passivation film 16 covering the electrode pad 14 is removed. As shown in FIG. 4A, the upper part of the electrode pad 14 is an opening H4, and a part of the electrode pad 14 is exposed. Through this opening H4, the first connection terminal 20 and the electrode pad 14 formed in a later process can be connected. Accordingly, the opening H4 only needs to be formed at a site other than the site where the hole H3 is formed. Moreover, you may adjoin.

本実施形態では、電極パッド１４のほぼ中央に孔部Ｈ３（開口部Ｈ１）を形成する場合を例に挙げている。よって、開口部Ｈ４は、この孔部Ｈ３を取り囲むように、つまり電極パッド１４の露出面積を大きくすることが電極パッド１４と、後に形成される接続端子との接続抵抗を小さくする上で好ましい。また、孔部Ｈ３の形成場所は電極パッド１４のほぼ中央でなくても良い。尚、電極パッド１４を覆う第一絶縁膜１８及びパッシベーション膜１６の一部を除去して、電極パッド１４の一部を露出させると、除去する際に用いたレジストを剥離液により剥離する。   In this embodiment, the case where the hole part H3 (opening part H1) is formed in the approximate center of the electrode pad 14 is mentioned as an example. Therefore, in order to reduce the connection resistance between the electrode pad 14 and the connection terminal formed later, it is preferable that the opening H4 surrounds the hole H3, that is, the exposed area of the electrode pad 14 is increased. Further, the hole H3 may not be formed at substantially the center of the electrode pad 14. When the first insulating film 18 and the passivation film 16 that cover the electrode pad 14 are partially removed and a part of the electrode pad 14 is exposed, the resist used for the removal is stripped with a stripping solution.

以上の工程が終了すると、次に下地膜を形成する工程が行われる。尚、この工程及び下地膜の図示は省略している。下地膜は基板１０の上面全面に形成されるため、電極パッド１４の露出部並びに孔部Ｈ３の内壁及び底面にも下地膜が形成される。ここで、下地膜は、バリヤ層及びシード層からなり、まずバリヤ層を形成した後で、バリヤ層上にシード層を形成することで成膜される。バリヤ層は、例えばＴｉＷから形成され、シード層はＣｕから形成される。   When the above steps are completed, a step of forming a base film is performed next. In addition, illustration of this process and a base film is abbreviate | omitted. Since the base film is formed on the entire upper surface of the substrate 10, the base film is also formed on the exposed portion of the electrode pad 14 and the inner wall and bottom surface of the hole H3. Here, the base film includes a barrier layer and a seed layer, and is formed by first forming a barrier layer and then forming a seed layer on the barrier layer. The barrier layer is made of, for example, TiW, and the seed layer is made of Cu.

バリヤ層及びシード層は、例えばＩＭＰ（イオンメタルプラズマ）法、又は、真空蒸着、スパッタリング、イオンプレーティング等のＰＶＤ（Physical Vapor Deposition）法いて形成される。下地膜は、電極パッド１４と第一絶縁膜１８との段差を十分にカバーして、電極パッド１４上と第一絶縁膜１８上（孔部Ｈ３の内部を含む）に連続的に形成される。尚、下地膜を構成するバリヤ層の膜厚は、例えば１００ｎｍ程度であり、シード層の膜厚は、例えば数百ｎｍ程度である。   The barrier layer and the seed layer are formed by, for example, an IMP (ion metal plasma) method or a PVD (Physical Vapor Deposition) method such as vacuum deposition, sputtering, or ion plating. The base film sufficiently covers the step between the electrode pad 14 and the first insulating film 18 and is continuously formed on the electrode pad 14 and the first insulating film 18 (including the inside of the hole H3). . The film thickness of the barrier layer constituting the base film is, for example, about 100 nm, and the film thickness of the seed layer is, for example, about several hundred nm.

下地膜の形成が終了すると、基板１０の能動面１０ａ上にメッキレジストを塗布し、第一接続端子２０を形成する部分のみが開口した状態にパターニングしてメッキレジストパターン（図示省略）を形成する。その後、Ｃｕ電解メッキを行って基板１０の孔部Ｈ３及びメッキレジストパターンの開口部にＣｕ（銅）を埋め込み、第一接続端子２０を形成する（第一接続端子形成工程）。   When the formation of the base film is completed, a plating resist is applied on the active surface 10a of the substrate 10 and patterned so that only the portions where the first connection terminals 20 are formed are opened to form a plating resist pattern (not shown). . Thereafter, Cu electrolytic plating is performed to embed Cu (copper) in the hole H3 of the substrate 10 and the opening of the plating resist pattern to form the first connection terminal 20 (first connection terminal forming step).

図４（ｂ）は、Ｃｕ電解メッキを行って第一接続端子２０を形成した状態を示す断面図である。図４（ｂ）に示す通り、第一接続端子２０は基板１０の能動面１０ａに突出した突起状の形状である。
また、符号Ｃを付した箇所において、第一接続端子２０は電極パッド１４と電気的に接続されている。第一接続端子２０が形成されると、基板１０上に形成されているメッキレジストパターンを剥離する。 FIG. 4B is a cross-sectional view showing a state in which the first connection terminal 20 is formed by performing Cu electrolytic plating. As shown in FIG. 4B, the first connection terminal 20 has a protruding shape that protrudes from the active surface 10 a of the substrate 10.
In addition, the first connection terminal 20 is electrically connected to the electrode pad 14 at a location denoted by reference symbol C. When the first connection terminal 20 is formed, the plating resist pattern formed on the substrate 10 is peeled off.

続いて、裏面１０ｂに孔部Ｈ６を形成するに先立って、基板１０の裏面１０ｂに対してエッチングを施して、基板１０を薄板化してもよい。基板１０が厚すぎると、孔部Ｈ６の形成が困難となるからである。
基板１０を薄板化するために基板１０の裏面１０ｂに対して行う処理方法は、裏面研磨又は裏面エッチングを用いることができるが、ここではエッチングにより基板１０を薄板化する方法を例に挙げて説明する。
基板１０の裏面１０ｂのエッチングは、基板１０の厚みが５０μｍ程度となるまで行う。裏面１０ｂからのエッチングは、ウェットエッチング、ドライエッチングのいずれであってもよい。また、ウェットエッチングとドライエッチングとを組み合わせる等のように複数のエッチング処理を施してもよい。
異なるエッチング処理を２度行うことにより、エッチングに要する時間を短縮して効率化を図るとともに、基板１０の厚みを正確に制御するためである。 Subsequently, the substrate 10 may be thinned by etching the back surface 10b of the substrate 10 prior to forming the hole H6 in the back surface 10b. This is because if the substrate 10 is too thick, it is difficult to form the hole H6.
As a processing method performed on the back surface 10b of the substrate 10 in order to reduce the thickness of the substrate 10, back surface polishing or back surface etching can be used. Here, a method of thinning the substrate 10 by etching will be described as an example. To do.
Etching of the back surface 10b of the substrate 10 is performed until the thickness of the substrate 10 reaches about 50 μm. Etching from the back surface 10b may be either wet etching or dry etching. In addition, a plurality of etching processes such as a combination of wet etching and dry etching may be performed.
This is because by performing different etching processes twice, the time required for etching is shortened to improve efficiency, and the thickness of the substrate 10 is accurately controlled.

例えば、最初に行うエッチングでは、エッチング量が多いため、効率化の観点からエッチング率（レート）を高く設定する必要がある。次に行うエッチングにおいては、基板１０の厚みを正確に制御するため、第１エッチング工程でのエッチング率よりも低いエッチング率でエッチングを行う必要がある。基板１０の裏面をエッチングする場合には、第１、第２エッチング工程ともドライエッチング若しくはウェットエッチングを行っても良く、第１、第２エッチングでドライエッチングとウェットエッチングとを切り替えるようにしても良い。   For example, in the first etching, since the etching amount is large, it is necessary to set the etching rate (rate) high from the viewpoint of efficiency. In the next etching, in order to accurately control the thickness of the substrate 10, it is necessary to perform the etching at an etching rate lower than the etching rate in the first etching step. When the back surface of the substrate 10 is etched, dry etching or wet etching may be performed in both the first and second etching steps, and dry etching and wet etching may be switched between the first and second etching steps. .

また、第１エッチング工程でウェットエッチングを行う場合には、エッチング液として弗硝酸（ＨＦ（弗化水素）＋ＨＮＯ３（硝酸））を用いることができる。エッチング液として弗硝酸を用いる場合には、ＨＦとＨＮＯ３との体積比を１：４．５に設定し、液温２５℃に設定すると、約３７．８μｍ／ｍｉｎのエッチング率が得られる。ウェットエッチングとしては、例えばディップ方式を用いたエッチング又はスピンエッチング装置を用いたエッチングを用いることができる。スピンエッチング装置を用いる場合には枚葉処理が可能となる。 Further, when wet etching is performed in the first etching step, hydrofluoric acid (HF (hydrogen fluoride) + HNO 3 (nitric acid)) can be used as an etchant. When hydrofluoric acid is used as an etching solution, an etching rate of about 37.8 μm / min is obtained when the volume ratio of HF and HNO 3 is set to 1: 4.5 and the solution temperature is set to 25 ° C. As the wet etching, for example, etching using a dip method or etching using a spin etching apparatus can be used. When a spin etching apparatus is used, single wafer processing is possible.

基板１０に対して第１、第２エッチング工程を行う際に、ウェットエッチングを行うか、又はドライエッチングを行うかは、エッチング面積を考慮した各々のエッチングレート、バッチ処理又は枚葉処理を行うことができるか否か等を考慮して、総合的に効率よくエッチングすることができるエッチング法を選択すればよい。尚、ウェットエッチングはエッチングレートがエッチング面積に左右されないが、ドライエッチングはエッチング面積によりエッチングレートが左右される。   Whether the wet etching or the dry etching is performed when the first and second etching processes are performed on the substrate 10 is performed by performing each etching rate, batch processing, or single wafer processing in consideration of the etching area. In consideration of whether or not the etching can be performed, an etching method capable of performing etching comprehensively and efficiently may be selected. Note that the etching rate is not affected by the etching area in wet etching, but the etching rate is affected by the etching area in dry etching.

以上の工程が終了すると、図５（ａ）に示すように、基板１０の裏面１０ｂにレジストを塗布する。レジストは、基板１０内に形成された孔部Ｈ３に対応する位置に開口部Ｈ５を設けたパターンを有する。そして、レジストをマスクとして基板１０を穿孔することにより、図５（ｂ）に示すように、孔部Ｈ６を形成する。これにより、孔部Ｈ３の底面に到達する孔部Ｈ６（第二孔部）が形成される（第二孔部形成工程）。
なお、孔部Ｈ６の径は、孔部Ｈ３よりも小径に形成される。孔部Ｈ６の位置ずれが生じた場合でも、孔部Ｈ６が孔部Ｈ３の底面から外れないようにするためである。
また、孔部Ｈ６の形成方法は、上述した場合と同様に、Ｓｉ高速エッチング法、又はボッシュプロセス法を用いて異方性エッチングを行うことが好ましい。 When the above steps are completed, a resist is applied to the back surface 10b of the substrate 10 as shown in FIG. The resist has a pattern in which an opening H5 is provided at a position corresponding to the hole H3 formed in the substrate 10. Then, by punching the substrate 10 using the resist as a mask, a hole H6 is formed as shown in FIG. Thereby, the hole H6 (second hole) that reaches the bottom surface of the hole H3 is formed (second hole forming step).
The diameter of the hole H6 is smaller than that of the hole H3. This is to prevent the hole H6 from being detached from the bottom surface of the hole H3 even when the position of the hole H6 is displaced.
Moreover, it is preferable to perform anisotropic etching using the Si high-speed etching method or the Bosch process method as the formation method of the hole H6 as described above.

そして、図６（ａ）に示すように、第一接続端子２０の底面の第一絶縁膜１８を裏面側からエッチングにより除去して、第一接続端子２０を露出させる。なお、第一接続端子２０の底面を局所的にエッチングしてもよいし、基板１０の裏面側全体をエッチングしてもよい。第一接続端子２０の底面の第一絶縁膜１８は薄膜であるため、露出させやすいからである。   Then, as shown in FIG. 6A, the first insulating film 18 on the bottom surface of the first connection terminal 20 is removed by etching from the back surface side to expose the first connection terminal 20. The bottom surface of the first connection terminal 20 may be locally etched, or the entire back surface side of the substrate 10 may be etched. This is because the first insulating film 18 on the bottom surface of the first connection terminal 20 is a thin film and thus is easily exposed.

続いて、図６（ｂ）に示すように、レジストを除去した後に、孔部Ｈ６の内壁及び底面に第二絶縁膜１９を形成する（第二絶縁膜形成工程）。
この第二絶縁膜１９は、第一絶縁膜１８と同一の層であり、これにより、第一絶縁膜１８と第二絶縁膜１９とは、連接された一体の絶縁層となる。
更に、図７（ａ）に示すように、第一接続端子２０の底面に形成された第二絶縁膜１９をエッチングにより除去して、第一接続端子２０を露出させる。
ここで、孔部Ｈ６の位置が孔部Ｈ３の位置から外れないようになっているので、第一絶縁膜１８と第二絶縁膜１９とは、連接された一体の絶縁層として残り、電流リークの発生、酸素及び水分等による基板１０の浸食等を防止する目的を達成することが可能となる。しがたって、孔部Ｈ６の径は、孔部Ｈ３との位置合わせの精度に応じて決定される。 Subsequently, as shown in FIG. 6B, after removing the resist, the second insulating film 19 is formed on the inner wall and the bottom surface of the hole H6 (second insulating film forming step).
The second insulating film 19 is the same layer as the first insulating film 18, whereby the first insulating film 18 and the second insulating film 19 become an integrated insulating layer that is connected.
Further, as shown in FIG. 7A, the second insulating film 19 formed on the bottom surface of the first connection terminal 20 is removed by etching to expose the first connection terminal 20.
Here, since the position of the hole H6 does not deviate from the position of the hole H3, the first insulating film 18 and the second insulating film 19 remain as an integrated insulating layer connected, and current leakage occurs. It is possible to achieve the purpose of preventing the occurrence of erosion, erosion of the substrate 10 due to oxygen, moisture, and the like. Therefore, the diameter of the hole H6 is determined according to the accuracy of alignment with the hole H3.

続いて、図７（ｂ）に示すように、基板１０の裏面１０ｂに第二接続端子２１を形成するためのレジストパターンを塗布する。すなわち、裏面１０ｂに形成された孔部Ｈ６を取り囲むようにレジストを配置する。
更に、裏面側からＣｕ電解メッキを行って基板１０の開口部Ｈ５にＣｕ（銅）を埋め込み、第二接続端子２１を形成する（第二接続端子形成工程）。
これにより、図８（ａ）に示すように、孔部Ｈ３の第一接続端子２０と孔部Ｈ６の第二接続端子２１とが連接されて、基板１０を貫通する１つの接続端子が形成される。
なお、第二接続端子２１の形成時には、第一接続端子２０の形成時と同様に、バリヤ層及びシード層等の下地膜を設けてもよい。
このようにして、基板１０の表面と裏面の両側に接続端子２０，２１が形成される。 Subsequently, as shown in FIG. 7B, a resist pattern for forming the second connection terminals 21 is applied to the back surface 10 b of the substrate 10. That is, the resist is arranged so as to surround the hole H6 formed in the back surface 10b.
Further, Cu electrolytic plating is performed from the back side to embed Cu (copper) in the opening H5 of the substrate 10 to form the second connection terminal 21 (second connection terminal forming step).
Thereby, as shown in FIG. 8A, the first connection terminal 20 of the hole H3 and the second connection terminal 21 of the hole H6 are connected to form one connection terminal penetrating the substrate 10. The
When the second connection terminal 21 is formed, a base film such as a barrier layer and a seed layer may be provided as in the formation of the first connection terminal 20.
In this way, the connection terminals 20 and 21 are formed on both the front and back surfaces of the substrate 10.

以上の工程が終了すると、接続端子２０，２１の先端部の何れか一方に無鉛ハンダ（Ｓｎ／Ａｇ）を形成する。尚、無鉛ハンダの図示は省略している。無鉛ハンダの形成が完了すると、ウェハ状態にある基板１０を切断して個々の半導体チップに分離する。ここで、基板１０の切断は、予め基板１０上に設定されているストリートライン（スクライブライン）に沿って行う。   When the above steps are completed, lead-free solder (Sn / Ag) is formed on either one of the distal ends of the connection terminals 20 and 21. The illustration of lead-free solder is omitted. When the formation of lead-free solder is completed, the substrate 10 in a wafer state is cut and separated into individual semiconductor chips. Here, the substrate 10 is cut along street lines (scribe lines) set on the substrate 10 in advance.

次に、分離した個々の半導体チップを積層して三次元実装構造とする。
半導体チップを積層するには、まず半導体チップに形成された接続端子２０に形成された無鉛ハンダ上に接合活性剤（フラックス）を塗布する工程が行われる。このフラックスは、半導体チップ同士を積層するときに、積層した半導体チップの位置ずれが生じないように粘着力で保持するとともに、半導体チップに形成された接続端子２０の表面の酸化膜を遊離させるためのものである。 Next, the separated individual semiconductor chips are stacked to form a three-dimensional mounting structure.
In order to stack the semiconductor chips, first, a step of applying a bonding activator (flux) onto lead-free solder formed on the connection terminals 20 formed on the semiconductor chip is performed. This flux is used to hold the stacked semiconductor chips with an adhesive force so that the stacked semiconductor chips are not displaced, and to release the oxide film on the surface of the connection terminal 20 formed on the semiconductor chips. belongs to.

フラックスの塗布の塗布を終えると、図８（ｂ）に示すように、半導体チップに形成された接続端子２０，２１の各々の位置が合うように、半導体チップＣ１と半導体チップＣ２との位置合わせを行って半導体チップＣ２上に半導体チップＣ１を積層する。
ここで、積層する半導体チップは、同種のもの（つまり、基板に形成されている電子回路が等しいもの）であってもよく、異種のもの（つまり、基板に形成されている電子回路が異なるもの）であってもよい。 When the application of the flux is finished, as shown in FIG. 8B, the semiconductor chip C1 and the semiconductor chip C2 are aligned so that the positions of the connection terminals 20 and 21 formed on the semiconductor chip are aligned. To stack the semiconductor chip C1 on the semiconductor chip C2.
Here, the semiconductor chips to be stacked may be the same type (that is, the same electronic circuit formed on the substrate) or different types (that is, different electronic circuits are formed on the substrate). ).

以上の工程が終了すると、積層した半導体チップＣ１，Ｃ２をリフロー装置内に配置して、半導体チップＣ１，Ｃ２に形成された接続端子２０の先端に設けられた無鉛ハンダを溶融させ、半導体チップＣ１に形成された接続端子２０と半導体チップＣ２に形成された接続端子２０とを接合する。
図８（ｂ）に示すように、半導体チップＣ１に形成された接続端子２１が、接続端子２０と略同一形状であり、無鉛ハンダの接合面積が大きいため接合強度が高まり、これによって信頼性の向上を図ることができる。 When the above steps are completed, the stacked semiconductor chips C1 and C2 are placed in a reflow apparatus, lead-free solder provided at the tip of the connection terminal 20 formed on the semiconductor chips C1 and C2 is melted, and the semiconductor chip C1 The connection terminals 20 formed on the semiconductor chip C2 are joined to the connection terminals 20 formed on the semiconductor chip C2.
As shown in FIG. 8B, the connection terminal 21 formed on the semiconductor chip C1 has substantially the same shape as the connection terminal 20, and the bonding area of lead-free solder is large, so that the bonding strength is increased. Improvements can be made.

尚、以上の説明においては、半導体チップＣ１と半導体チップＣ２とを積層する場合を例に挙げて説明したが、基板１０を切断して得られた半導体チップをインターポーザ等の搭載基板に搭載する場合も、半導体チップ同士を積層する場合と同様の工程で搭載することができる。このときには、搭載基板に形成された接続部としての接続電極と、半導体チップに形成された接続端子２０との位置合わせを行ってインターポーザ上に半導体チップを搭載し（搭載工程）、接続電極と接続端子とを接合する。   In the above description, the case where the semiconductor chip C1 and the semiconductor chip C2 are stacked has been described as an example. However, the semiconductor chip obtained by cutting the substrate 10 is mounted on a mounting substrate such as an interposer. In addition, the semiconductor chip can be mounted in the same process as that for stacking semiconductor chips. At this time, the semiconductor chip is mounted on the interposer by performing alignment between the connection electrode as the connection portion formed on the mounting substrate and the connection terminal 20 formed on the semiconductor chip (mounting process), and connected to the connection electrode. Join the terminal.

また、インターポーザ上に半導体チップを搭載する形態以外にもインターポーザに代えてＷ−ＣＳＰ（Wafer level Chip Scale Package）技術を用いて処理された基板上に半導体装置を積層するようにしても良い。ここで、Ｗ−ＣＳＰ技術とは、ウェハの状態において一括して再配置配線（再配線）及び樹脂封止を行ってから個々の半導体チップに分離する技術である。Ｗ−ＣＳＰ技術を用いて処理された基板上に半導体装置を積層する場合には、再配置配線により形成された電極上に半導体チップを積層しても良く、ウェハ状態にある基板に対して半導体チップＣ１，Ｃ２に形成された接続端子２０と同様の接続端子を形成し、この接続端子と半導体チップに形成された接続端子とを接合して積層するようにしてもよい。
〔半導体装置：再配置配線〕
以上のように積層形成された半導体装置を回路基板に実装するため、再配線を行うのが望ましい。図９は、半導体チップの再配線の説明図である。
図９（ａ）に示す半導体チップ６１の表面には、その対辺に沿って複数の電極６２が形成されているので、隣接する電極相互のピッチが狭くなっている。このような半導体チップ６１を回路基板に実装すると、隣接する電極相互が短絡するおそれがある。そこで、電極相互のピッチを広げるため、半導体チップ６１の対辺に沿って形成された複数の電極６２を中央部に引き出す再配線が行われている。 In addition to a mode in which a semiconductor chip is mounted on an interposer, a semiconductor device may be stacked on a substrate processed using a W-CSP (Wafer level Chip Scale Package) technique instead of the interposer. Here, the W-CSP technique is a technique in which rearrangement wiring (rewiring) and resin sealing are collectively performed in a wafer state and then separated into individual semiconductor chips. When a semiconductor device is stacked on a substrate processed using the W-CSP technology, a semiconductor chip may be stacked on an electrode formed by rearrangement wiring. A connection terminal similar to the connection terminal 20 formed on the chips C1 and C2 may be formed, and the connection terminal and the connection terminal formed on the semiconductor chip may be bonded and stacked.
[Semiconductor device: Relocation wiring]
In order to mount the semiconductor device stacked as described above on the circuit board, it is desirable to perform rewiring. FIG. 9 is an explanatory diagram of the rewiring of the semiconductor chip.
Since a plurality of electrodes 62 are formed on the surface of the semiconductor chip 61 shown in FIG. 9A along the opposite side, the pitch between adjacent electrodes is narrowed. When such a semiconductor chip 61 is mounted on a circuit board, adjacent electrodes may be short-circuited. Therefore, in order to widen the pitch between the electrodes, rewiring is performed to draw out the plurality of electrodes 62 formed along the opposite sides of the semiconductor chip 61 to the center.

図９（ｂ）は、再配線を行った半導体チップの平面図である。半導体チップ６１の表面中央部には、円形状の複数の電極パッド６３がマトリクス上に配列形成されている。各電極パッド６３は、再配線６４により１個または複数個の電極６２に接続されている。これにより、狭ピッチの電極６２が中央部に引き出されて、広ピッチ化されている。   FIG. 9B is a plan view of the semiconductor chip after rewiring. A plurality of circular electrode pads 63 are arranged on the matrix at the center of the surface of the semiconductor chip 61. Each electrode pad 63 is connected to one or a plurality of electrodes 62 by rewiring 64. As a result, the narrow-pitch electrodes 62 are drawn out to the central portion, and the pitch is increased.

図１０は、図９（ｂ）のＡ−Ａ線における側面断面図である。
上記のように積層形成された半導体装置を上下反転して、最下層となる半導体チップ６１の底面中央部には、ソルダーレジスト６５が形成されている。そして、電極６２のポスト部からソルダーレジスト６５の表面にかけて、再配線６４が形成されている。再配線６４のソルダーレジスト６５側の端部には電極パッド６３が形成され、その電極パッドの表面にバンプ７８が形成されている。バンプ７８は、たとえばハンダバンプであり、印刷法等によって形成する。なお、半導体チップ６１の底面全体には、補強用の樹脂６６等が成型されている。 FIG. 10 is a side cross-sectional view taken along the line AA in FIG.
A solder resist 65 is formed at the center of the bottom surface of the semiconductor chip 61 that is the lowermost layer by inverting the stacked semiconductor device as described above. A rewiring 64 is formed from the post portion of the electrode 62 to the surface of the solder resist 65. An electrode pad 63 is formed at the end of the rewiring 64 on the solder resist 65 side, and a bump 78 is formed on the surface of the electrode pad. The bump 78 is, for example, a solder bump and is formed by a printing method or the like. A reinforcing resin 66 and the like are molded on the entire bottom surface of the semiconductor chip 61.

図１１は、回路基板の斜視図である。
図１１では、半導体チップを積層して形成した半導体装置１が、回路基板１０００に実装されている。具体的には、半導体装置１における最下層の半導体チップに形成されたバンプが、回路基板１０００の表面に形成された電極パッドに対して、リフローやＦＣＢ（Flip Chip Bonding）等を行うことにより実装されている。なお、回路基板との間に異方導電性フィルム等を挟み込んで、半導体装置１を実装してもよい。 FIG. 11 is a perspective view of a circuit board.
In FIG. 11, the semiconductor device 1 formed by stacking semiconductor chips is mounted on a circuit board 1000. Specifically, bumps formed on the lowermost semiconductor chip in the semiconductor device 1 are mounted by performing reflow, FCB (Flip Chip Bonding), or the like on the electrode pads formed on the surface of the circuit board 1000. Has been. The semiconductor device 1 may be mounted with an anisotropic conductive film or the like sandwiched between the circuit board.

〔電子機器〕
次に、上述した半導体装置を備えた電子機器の例について説明する。
図１２は、電子機器の一例である携帯電話の斜視図である。上述した半導体装置は、携帯電話３００の筐体内部に配置されている。 〔Electronics〕
Next, an example of an electronic device including the above-described semiconductor device will be described.
FIG. 12 is a perspective view of a mobile phone which is an example of an electronic apparatus. The semiconductor device described above is arranged inside the housing of the mobile phone 300.

なお、上述した半導体装置は、携帯電話以外にも種々の電子機器に適用することができる。例えば、液晶プロジェクタ、マルチメディア対応のパーソナルコンピュータ（ＰＣ）およびエンジニアリング・ワークステーション（ＥＷＳ）、ページャ、ワードプロセッサ、テレビ、ビューファインダ型またはモニタ直視型のビデオテープレコーダ、電子手帳、電子卓上計算機、カーナビゲーション装置、ＰＯＳ端末、タッチパネルを備えた装置などの電子機器に適用することが可能である。   Note that the semiconductor device described above can be applied to various electronic devices other than mobile phones. For example, LCD projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desk calculators, car navigation systems The present invention can be applied to electronic devices such as a device, a POS terminal, and a device provided with a touch panel.

なお、上述した実施形態の「半導体チップ」を「電子素子」に置き換えて、電子部品を製造することもできる。このような電子素子を使用して製造される電子部品として、例えば、光素子、抵抗器、コンデンサ、コイル、発振器、フィルタ、温度センサ、サーミスタ、バリスタ、ボリュームおよびヒューズなどを挙げることができる。   It should be noted that an electronic component can be manufactured by replacing the “semiconductor chip” in the above-described embodiment with an “electronic element”. Examples of electronic components manufactured using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes, and fuses.

以上、添付図面を参照しながら本発明に係る好適な実施の形態例について説明したが、本発明は係る例に限定されないことは言うまでもない。上述した例において示した各構成部材の諸形状や組み合わせ等は一例であって、本発明の主旨から逸脱しない範囲において設計要求等に基づき種々変更可能である。   The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but it goes without saying that the present invention is not limited to such examples. Various shapes, combinations, and the like of the constituent members shown in the above-described examples are examples, and various modifications can be made based on design requirements and the like without departing from the gist of the present invention.

半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of a semiconductor device. 図１に続く工程図である。FIG. 2 is a process diagram following FIG. 1. 図２に続く工程図である。FIG. 3 is a process diagram following FIG. 2. 図３に続く工程図である。FIG. 4 is a process diagram following FIG. 3. 図４に続く工程図である。FIG. 5 is a process diagram following FIG. 4. 図５に続く工程図である。FIG. 6 is a process diagram following FIG. 5. 図６に続く工程図である。FIG. 7 is a process drawing following FIG. 6. 図７に続く工程図である。FIG. 8 is a process diagram following FIG. 7. 半導体チップの再配線の説明図である。It is explanatory drawing of the rewiring of a semiconductor chip. 図９（ｂ）のＡ−Ａ線における側面断面図である。It is side surface sectional drawing in the AA of FIG.9 (b). 回路基板の斜視図である。It is a perspective view of a circuit board. 電子機器の一例を示す図である。It is a figure which shows an example of an electronic device.

符号の説明Explanation of symbols

１０…基板（半導体基板）、 １０ａ…能動面（表面）、 １０ｂ…裏面、 １８…第一絶縁膜、 １９…第二絶縁膜、 ２０…第一接続端子（電極）、 ２１…第二接続端子（電極）、 ６２…電極、 ３００…携帯電話（電子機器） 、１０００…回路基板、 Ｈ３…孔部（第一孔部）、 Ｈ６…孔部（第二孔部）、 Ｃ１，Ｃ２，６１…半導体チップ



DESCRIPTION OF SYMBOLS 10 ... Board | substrate (semiconductor substrate), 10a ... Active surface (front surface), 10b ... Back surface, 18 ... First insulating film, 19 ... Second insulating film, 20 ... First connection terminal (electrode), 21 ... Second connection terminal (Electrode), 62 ... electrode, 300 ... mobile phone (electronic device), 1000 ... circuit board, H3 ... hole (first hole), H6 ... hole (second hole), C1, C2, 61 ... Semiconductor chip



Claims (8)

半導体基板の能動面から前記半導体基板の内部にかけて第一孔部を形成する工程と、
前記第一孔部の内側に導電材料を充填して第一接続端子を形成する工程と、
前記半導体基板の前記能動面とは反対側の裏面から前記第一孔部の底面に到達する第二孔部を形成する工程と、
前記第二孔部の内面に導電材料を充填して第二接続端子を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Forming a first hole from the active surface of the semiconductor substrate to the inside of the semiconductor substrate;
Filling the inside of the first hole with a conductive material to form a first connection terminal;
Forming a second hole portion that reaches the bottom surface of the first hole portion from the back surface opposite to the active surface of the semiconductor substrate;
Filling the inner surface of the second hole with a conductive material to form a second connection terminal;
A method for manufacturing a semiconductor device, comprising: 前記第一接続端子の形成に先立って前記第一孔部の内面に第一絶縁膜を形成する工程と、
前記第二接続端子の形成に先立って前記第二孔部の内面に前記第一絶縁膜に連接する第二絶縁膜を形成する工程と、
を有することを特徴とする請求項１に記載の半導体装置の製造方法。 Forming a first insulating film on the inner surface of the first hole prior to the formation of the first connection terminal;
Forming a second insulating film connected to the first insulating film on the inner surface of the second hole prior to the formation of the second connection terminal;
The method of manufacturing a semiconductor device according to claim 1, wherein: 前記第一接続端子と前記第二接続端子とは、略同一形状に形成されることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the first connection terminal and the second connection terminal are formed in substantially the same shape. 請求項１から３のいずれか一項に記載の半導体装置の製造方法を使用して製造されたことを特徴とする半導体装置。   A semiconductor device manufactured using the method for manufacturing a semiconductor device according to claim 1. 集積回路が形成された半導体基板と、
前記半導体基板の能動面から前記半導体基板の裏面にかけて形成された貫通孔の内部に絶縁層を介して形成された電極と、を有してなり、
前記電極は、能動面側と裏面側にそれぞれ略同一形状の接続端子を備えることを特徴とする半導体装置。 A semiconductor substrate on which an integrated circuit is formed;
An electrode formed through an insulating layer inside a through hole formed from the active surface of the semiconductor substrate to the back surface of the semiconductor substrate,
The electrode includes a connection terminal having substantially the same shape on each of an active surface side and a back surface side. 請求項４又は請求項５に記載の半導体装置が複数積層され、上下に隣接する前記半導体装置の前記接続端子がハンダまたは蝋材を介して電気的に接続されていることを特徴とする半導体装置。   6. A semiconductor device according to claim 4, wherein a plurality of the semiconductor devices according to claim 4 are stacked, and the connection terminals of the semiconductor devices vertically adjacent to each other are electrically connected via solder or a wax material. . 請求項６に記載の半導体装置が実装されていることを特徴とする回路基板。   A circuit board on which the semiconductor device according to claim 6 is mounted. 請求項７に記載の回路基板を備えたことを特徴とする電子機器。



An electronic apparatus comprising the circuit board according to claim 7.



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JP2007005403A (en) * 2005-06-21 2007-01-11 Matsushita Electric Works Ltd Method of forming through wiring in semiconductor substrate
JP2010103533A (en) * 2008-10-21 2010-05-06 Taiwan Semiconductor Manufacturing Co Ltd Design of bond pad for decreasing dishing effect
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US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
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US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
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JP2007005403A (en) * 2005-06-21 2007-01-11 Matsushita Electric Works Ltd Method of forming through wiring in semiconductor substrate
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US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
JP2015008296A (en) * 2007-03-05 2015-01-15 インヴェンサス・コーポレイション Chip having rear face contact connected to front face contact by through via
JP2010103533A (en) * 2008-10-21 2010-05-06 Taiwan Semiconductor Manufacturing Co Ltd Design of bond pad for decreasing dishing effect
US9691739B2 (en) 2008-12-19 2017-06-27 Tessera Advanced Technologies, Inc. Semiconductor device and method of manufacturing same
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US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US10354942B2 (en) 2010-09-17 2019-07-16 Tessera, Inc. Staged via formation from both sides of chip
JP2012119685A (en) * 2010-11-29 2012-06-21 Samsung Electronics Co Ltd Semiconductor device, manufacturing method of the same, and semiconductor package including semiconductor device
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
EP2893553A4 (en) * 2012-09-05 2016-05-11 Res Triangle Inst Electronic devices utilizing contact pads with protrusions and methods for fabrication
CN107851648A (en) * 2015-07-16 2018-03-27 索尼半导体解决方案公司 Solid-state image pickup, manufacture method and electronic installation
JPWO2017010311A1 (en) * 2015-07-16 2018-04-26 ソニーセミコンダクタソリューションズ株式会社 Solid-state imaging device, manufacturing method, and electronic apparatus
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