JP4581864B2 - Method for forming through wiring on semiconductor substrate - Google Patents

Method for forming through wiring on semiconductor substrate Download PDF

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JP4581864B2
JP4581864B2 JP2005181074A JP2005181074A JP4581864B2 JP 4581864 B2 JP4581864 B2 JP 4581864B2 JP 2005181074 A JP2005181074 A JP 2005181074A JP 2005181074 A JP2005181074 A JP 2005181074A JP 4581864 B2 JP4581864 B2 JP 4581864B2
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semiconductor substrate
hole
metal
insulating layer
wiring
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JP2007005403A (en
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亮 友井田
薫 戸根
將有 鎌倉
規裕 山内
久徳 城石
巧 田浦
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Panasonic Corp
Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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Description

本発明は、半導体基板への貫通配線の形成方法に関し、例えば、ウェハレベルパッケージングなどで用いられる貫通配線の形成方法に関するものである。   The present invention relates to a method for forming a through wiring on a semiconductor substrate, for example, a method for forming a through wiring used in wafer level packaging or the like.

従来から、半導体基板への貫通配線の形成方法が各所で研究開発されている（例えば、特許文献１参照）。   Conventionally, a method for forming a through wiring on a semiconductor substrate has been researched and developed in various places (for example, see Patent Document 1).

以下、上述の半導体基板への貫通配線の形成方法について図３に基づいて説明するが、図３（ａ）〜（ｃ）における半導体基板１はダイシング工程により個々のチップに分離する前のウェハである。   Hereinafter, a method for forming the through wiring on the semiconductor substrate will be described with reference to FIG. 3. The semiconductor substrate 1 in FIGS. 3A to 3C is a wafer before being separated into individual chips by a dicing process. is there.

まず、半導体基板１の一表面（図３（ａ）の上面）における貫通孔形成予定部位にエッチング加工などによって貫通孔用の有底孔（凹部）１ａを形成してから、ＣＶＤ法や熱酸化法などによって半導体基板１の上記一表面および有底孔１ａの内面に絶縁層３ａを形成するとともに半導体基板１の他表面（図３（ａ）の下面）に絶縁層３ｂを形成することにより、図３（ａ）に示す構造を得る。   First, a bottomed hole (recessed portion) 1a for a through hole is formed by etching or the like at a through hole formation scheduled portion on one surface of the semiconductor substrate 1 (upper surface in FIG. 3A), and then CVD or thermal oxidation is performed. By forming the insulating layer 3a on the one surface of the semiconductor substrate 1 and the inner surface of the bottomed hole 1a by the method or the like, and forming the insulating layer 3b on the other surface of the semiconductor substrate 1 (the lower surface of FIG. 3A), The structure shown in FIG.

その後、半導体基板１の上記一表面および有底孔１ａの内面に形成されている絶縁層３ａに金属材料（例えば、銅、ニッケルなど）からなる金属層（金属薄膜）４をＣＶＤ法やスパッタ法などによって積層してから、当該金属層４をシード層として電解メッキ法などによって金属材料（例えば、銅、ニッケルなど）からなる金属部５を析出（堆積）させることにより、図３（ｂ）に示す構造を得る。   Thereafter, a metal layer (metal thin film) 4 made of a metal material (for example, copper, nickel, etc.) is applied to the insulating layer 3a formed on the one surface of the semiconductor substrate 1 and the inner surface of the bottomed hole 1a by CVD or sputtering. Then, by depositing (depositing) a metal portion 5 made of a metal material (for example, copper, nickel, etc.) by electrolytic plating using the metal layer 4 as a seed layer, FIG. Get the structure shown.

次に、半導体基板１の上記他表面側を化学的機械的研磨（Chemical Mechanical Polishing：ＣＭＰ）技術などによって研磨して金属層４を露出させるとともに貫通孔２’を完成させ、続いて、金属部５および金属層４のうち半導体基板１の上記一表面側における不要部分を除去することによって、図３（ｃ）に示す構造を得る。ここに、図３（ｃ）では、金属部５のうち貫通孔２’に埋め込まれている部分と金属層４のうち貫通孔２’に埋め込まれている部分とで貫通配線６を構成している。   Next, the other surface side of the semiconductor substrate 1 is polished by a chemical mechanical polishing (CMP) technique or the like to expose the metal layer 4 and complete the through hole 2 ′. 5 and the metal layer 4 are removed of the unnecessary portion on the one surface side of the semiconductor substrate 1 to obtain the structure shown in FIG. Here, in FIG. 3C, the through wiring 6 is configured by a portion of the metal portion 5 embedded in the through hole 2 ′ and a portion of the metal layer 4 embedded in the through hole 2 ′. Yes.

ところで、上述の電解メッキ法により金属部５を析出させる工程においては、図４（ａ）に示すように半導体基板１の上記一表面および有底孔１ａの内面の全体に亘って形成されている絶縁層３ａに積層された金属薄膜４をシード層として利用しているので、金属部５は図４（ｂ）に示すように均一に成長するコンフォーマル成長により析出することとなる。   By the way, in the process of depositing the metal part 5 by the above-mentioned electrolytic plating method, as shown to Fig.4 (a), it forms over the said one surface of the semiconductor substrate 1, and the whole inner surface of the bottomed hole 1a. Since the metal thin film 4 laminated on the insulating layer 3a is used as a seed layer, the metal portion 5 is deposited by conformal growth that grows uniformly as shown in FIG. 4B.

しかしながら、上述のコンフォーマル成長により金属部５を析出させる方法では、有底孔１ａのアスペクト比が高くなるにつれて有底孔１ａの内側にボイド（空洞）が形成されてしまう（言い換えれば、有底孔１ａの内側を隙間なく埋め込むことができない）という問題が起こりやすかった。また、上述のコンフォーマル成長により金属部５を析出させる方法では、有底孔１ａが半導体基板１の上記一表面側において上記一表面に近づくにつれて開口面積が徐々に小さくなる形状に形成されている場合に、金属部５の成長途中で有底孔１ａの内側が完全に埋め込まれないうちに半導体基板１の一表面側において有底孔１ａの開口面が金属部５によって塞がれてしまって有底孔１ａの内側にボイドが形成されてしまうという問題があった。   However, in the method of depositing the metal part 5 by the above-described conformal growth, voids (cavities) are formed inside the bottomed hole 1a as the aspect ratio of the bottomed hole 1a increases (in other words, the bottomed hole 1a has a bottom. The problem that the inside of the hole 1a cannot be embedded without a gap) was likely to occur. Moreover, in the method of depositing the metal part 5 by the above-mentioned conformal growth, the opening area is gradually reduced as the bottomed hole 1 a approaches the one surface on the one surface side of the semiconductor substrate 1. In this case, the opening surface of the bottomed hole 1a is blocked by the metal part 5 on the one surface side of the semiconductor substrate 1 before the inside of the bottomed hole 1a is not completely buried during the growth of the metal part 5. There was a problem that voids were formed inside the bottomed hole 1a.

そこで、ボイドの発生が起こりにくい貫通配線の形成方法として、半導体基板の厚み方向に沿って金属部が成長するボトムアップ成長により金属部を析出させる方法が提案されている。   In view of this, as a method of forming a through wiring that is less likely to generate voids, a method of depositing a metal part by bottom-up growth in which the metal part grows along the thickness direction of the semiconductor substrate has been proposed.

以下、ボトムアップ成長により金属部を析出させる方法を採用した貫通配線の形成方法の一例について図５に基づいて説明する。   Hereinafter, an example of a method of forming a through wiring employing a method of depositing a metal part by bottom-up growth will be described with reference to FIG.

まず、図５（ａ）の上側に示すようにエッチング加工などによって貫通孔２を形成した半導体基板１と、図５（ａ）の下側に示すように金属材料などからなる導電層１４が一表面上に形成された基板１５とを用意し、半導体基板１と基板１５とを導電層１４を介在させた形で接合あるいは貼り合わせることにより、図５（ｂ）に示す構造を得る。   First, a semiconductor substrate 1 in which a through hole 2 is formed by etching or the like as shown in the upper side of FIG. 5A and a conductive layer 14 made of a metal material or the like as shown in the lower side of FIG. A substrate 15 formed on the surface is prepared, and the structure shown in FIG. 5B is obtained by bonding or bonding the semiconductor substrate 1 and the substrate 15 with the conductive layer 14 interposed therebetween.

その後、導電層１４をシード層として電解メッキ法により金属部５を析出させることにより、図５（ｃ）に示す構造を得る。ここにおいて、金属部５は導電層１４の表面から半導体基板１の厚み方向に沿って成長するボトムアップ成長により形成されることとなるので、貫通孔２の内側にボイドが発生しにくくなる。   Thereafter, the metal layer 5 is deposited by electrolytic plating using the conductive layer 14 as a seed layer, thereby obtaining the structure shown in FIG. Here, since the metal portion 5 is formed by bottom-up growth that grows from the surface of the conductive layer 14 along the thickness direction of the semiconductor substrate 1, voids are less likely to be generated inside the through hole 2.

さらにその後、上述の導電層１４が一表面側に形成されている基板１５を半導体基板１から剥離することにより、図５（ｄ）に示す構造を得る。ここにおいて、金属部５のうち貫通孔２の内側に形成されている部分が貫通配線となる。その後は、例えば、半導体基板１の裏面（図５（ｄ）における下面）に電極層用の導体層を形成し、当該導体層の不要部分を除去すればよい。   Thereafter, the substrate 15 having the conductive layer 14 formed on one surface side is peeled off from the semiconductor substrate 1 to obtain the structure shown in FIG. Here, a portion of the metal portion 5 formed inside the through hole 2 is a through wiring. Thereafter, for example, a conductive layer for the electrode layer may be formed on the back surface (the lower surface in FIG. 5D) of the semiconductor substrate 1, and unnecessary portions of the conductive layer may be removed.

次に、ボトムアップ成長により金属部を析出させる方法を採用した貫通配線の形成方法の他の例について図６に基づいて説明する。   Next, another example of a method for forming a through wiring employing a method of depositing a metal part by bottom-up growth will be described with reference to FIG.

まず、半導体基板１にエッチング加工などによって厚み方向に貫通する貫通孔２を形成することにより、図６（ａ）に示す構造を得る。その後、ＣＶＤ法や熱酸化法などによって半導体基板１の一表面（図６（ａ）における下面）および他表面（図６（ａ）における上面）および貫通孔２の内周面に絶縁層３を形成することにより、図６（ｂ）に示す構造を得る。   First, the structure shown in FIG. 6A is obtained by forming the through hole 2 penetrating in the thickness direction by etching or the like in the semiconductor substrate 1. Thereafter, the insulating layer 3 is formed on one surface (the lower surface in FIG. 6A) and the other surface (the upper surface in FIG. 6A) of the semiconductor substrate 1 and the inner peripheral surface of the through hole 2 by CVD or thermal oxidation. By forming, the structure shown in FIG. 6B is obtained.

続いて、半導体基板１の上記一表面側に金属材料（例えば、銅、ニッケルなど）からなる金属層４をスパッタ法などによって形成することにより、図６（ｃ）に示す構造を得る。続いて、金属層４をシード層として電解メッキ法によって、貫通孔２の内側が埋め込まれるように金属部５を析出させることにより、図６（ｅ）に示す構造を得る。ここにおいて、金属部５は、図６（ｄ）に示すように半導体基板１の上記一表面側に析出して半導体基板１の上記一表面側において貫通孔２の開口面を塞ぐように成長した部分５ａと、引き続いて、ボトムアップ成長により半導体基板１の厚み方向に沿って成長した部分５ｂ（図６（ｅ）参照）とで構成されている。金属部５を形成した後、不要部分の除去や平坦化を目的としたＣＭＰを行うことによって、金属部５のうち貫通孔２の内側に形成されている部分からなる貫通配線が完成する。その後は、例えば、半導体基板１の上記一表面側に電極層用の導体層を形成し、当該導体層の不要部分を除去すればよい。
特開２００３−３２８１８０号公報 Subsequently, a metal layer 4 made of a metal material (for example, copper, nickel, etc.) is formed on the one surface side of the semiconductor substrate 1 by a sputtering method or the like, thereby obtaining the structure shown in FIG. Subsequently, by depositing the metal portion 5 so that the inside of the through-hole 2 is embedded by electrolytic plating using the metal layer 4 as a seed layer, the structure shown in FIG. 6E is obtained. Here, as shown in FIG. 6D, the metal portion 5 is deposited on the one surface side of the semiconductor substrate 1 and grows so as to close the opening surface of the through hole 2 on the one surface side of the semiconductor substrate 1. The portion 5a and the portion 5b (see FIG. 6E) grown along the thickness direction of the semiconductor substrate 1 by bottom-up growth are subsequently formed. After the metal portion 5 is formed, by performing CMP for the purpose of removing unnecessary portions and flattening, a through wiring composed of a portion of the metal portion 5 formed inside the through hole 2 is completed. Thereafter, for example, a conductor layer for an electrode layer may be formed on the one surface side of the semiconductor substrate 1 and unnecessary portions of the conductor layer may be removed.
JP 2003-328180 A

ところで、上述の図５や図６のようにボトムアップ成長により金属部を析出させる方法を採用した貫通配線の形成方法では、コンフォーマル成長による埋め込みが困難な貫通孔（高アスペクト比の微細孔）への埋め込み性が改善される。しかしながら、ボトムアップ成長により形成された貫通配線では、コンフォーマル成長により成長された金属部５と当該金属部５の析出時のシード層たる金属層４とで構成される貫通配線６に比較して、貫通配線の下地である絶縁層３との密着性が低いので、金属部５の不要部分の除去や平坦化を目的としたＣＭＰを行った場合に、金属部５のうち貫通孔２の内側に形成されている部分の一部が剥離してチップ歩留まりが低下してしまう可能性があった。また、ボトムアップ成長により形成された貫通配線では、絶縁層３のうち貫通孔２の内周面に形成されている部位と金属部５との間に空隙が生じる可能性もあり、パッケージング時に上記空隙に起因して気密性が損なわれてしまう可能性があった。   By the way, in the formation method of the penetration wiring which employ | adopted the method of depositing a metal part by bottom-up growth as mentioned above FIG.5 and FIG.6, the penetration hole (micro hole with a high aspect ratio) which is difficult to fill by conformal growth. Improves embeddability. However, in the through wiring formed by bottom-up growth, compared to the through wiring 6 constituted by the metal part 5 grown by conformal growth and the metal layer 4 as a seed layer when the metal part 5 is deposited. Since the adhesion to the insulating layer 3 which is the base of the through wiring is low, when CMP is performed for the purpose of removing unnecessary portions of the metal portion 5 and planarization, the inside of the through hole 2 in the metal portion 5 There is a possibility that a part of the portion formed on the surface is peeled off and the chip yield is lowered. In addition, in the through wiring formed by bottom-up growth, there is a possibility that a gap is generated between a portion of the insulating layer 3 formed on the inner peripheral surface of the through hole 2 and the metal portion 5, and at the time of packaging The airtightness may be impaired due to the gap.

本発明は上記事由に鑑みて為されたものであり、その目的は、半導体基板に貫設される貫通孔の内側への埋め込み性が良好で且つ貫通孔の内周面に形成された絶縁層との密着性が良好な貫通配線を形成可能な半導体基板への貫通配線の形成方法を提供することにある。   The present invention has been made in view of the above-mentioned reasons, and an object of the present invention is to provide an insulating layer formed on the inner peripheral surface of the through-hole that has a good embedding property inside the through-hole formed in the semiconductor substrate. It is an object of the present invention to provide a method of forming a through wiring on a semiconductor substrate capable of forming a through wiring with good adhesion to the semiconductor substrate.

請求項１の発明は、半導体基板への貫通配線の形成方法であって、半導体基板に厚み方向に貫通し前記厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる貫通孔を形成する貫通孔形成工程と、半導体基板の一表面および他表面および貫通孔の内周面に絶縁層を形成する絶縁層形成工程と、半導体基板の前記他表面側を除いて前記一表面側および貫通孔の内側で絶縁層の表面に金属層を被着する金属層形成工程と、金属層をシード層として電解メッキ法により貫通孔の内側を埋め込む金属部であり金属層とともに貫通配線を構成する金属部を析出させる電解メッキ工程とを備え、絶縁層形成工程では、絶縁層を形成した後も貫通孔の内側では半導体基板の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となるように絶縁層を成膜することを特徴とする。 The invention according to claim 1 is a method for forming a through-wiring in a semiconductor substrate, wherein a through-hole is formed in the semiconductor substrate in the thickness direction and the opening area gradually decreases as it approaches the middle position from both sides in the thickness direction. A through hole forming step, an insulating layer forming step of forming an insulating layer on one surface and the other surface of the semiconductor substrate and an inner peripheral surface of the through hole, and the one surface side and the through hole except for the other surface side of the semiconductor substrate. A metal layer forming step for depositing a metal layer on the surface of the insulating layer inside the hole, and a metal part that embeds the inside of the through hole by electrolytic plating using the metal layer as a seed layer and constitutes the through wiring together with the metal layer In the insulating layer forming step, the opening area gradually increases from the both sides in the thickness direction of the semiconductor substrate toward the intermediate position after the insulating layer is formed in the insulating layer forming step. Characterized by forming an insulating layer so as to create shape.

この発明によれば、貫通孔形成工程において半導体基板に貫設される貫通孔が半導体基板の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となり、絶縁層形成工程では、絶縁層を形成した後も貫通孔の内側では半導体基板の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となるように絶縁層を成膜し、金属層形成工程では、半導体基板の前記他表面側を除いて前記一表面側および貫通孔の内側で絶縁層の表面に金属層を被着するので、電解メッキ工程において金属層をシード層として金属部を析出させる際に貫通孔の中間位置近傍にて貫通孔が塞がるまではコンフォーマル成長で金属部が析出し、引き続いて半導体基板の前記一表面側および前記他表面側それぞれへ金属部が成長していき貫通孔の内側が金属部によって埋め込まれることとなり、従来のボトムアップ成長により金属部を析出させる場合に比べて絶縁層のうち貫通孔の内側に形成されている部位と貫通配線との密着性を向上させることができ、しかも、貫通孔の内側が金属部によって完全に埋め込まれないうちに半導体基板の前記一表面側や前記他表面側において貫通孔の開口面が金属部によって塞がれるのを防止することができるから、半導体基板に貫設される貫通孔の内側への埋め込み性が良好で且つ貫通孔の内周面に形成された絶縁層との密着性が良好な貫通配線を形成可能になる。 According to this invention, the through-hole formed in the semiconductor substrate in the through-hole forming step has a shape in which the opening area gradually decreases as it approaches the intermediate position from both sides in the thickness direction of the semiconductor substrate. Even after the insulating layer is formed, the insulating layer is formed so that the opening area gradually decreases as it approaches the intermediate position from both sides in the thickness direction of the semiconductor substrate inside the through hole. Since a metal layer is deposited on the surface of the insulating layer on the one surface side and inside the through hole except for the other surface side of the semiconductor substrate , when depositing the metal part using the metal layer as a seed layer in the electrolytic plating process Until the through hole is closed in the vicinity of the intermediate position of the through hole, the metal part is deposited by conformal growth, and subsequently the metal part is placed on each of the one surface side and the other surface side of the semiconductor substrate. The portion of the insulating layer formed inside the through-hole and the through-wiring are longer than the case where the inside of the through-hole is buried by the metal portion and the metal portion is deposited by conventional bottom-up growth. In addition, before the inside of the through hole is completely filled with the metal portion, the opening surface of the through hole is blocked by the metal portion on the one surface side or the other surface side of the semiconductor substrate. Since it can be prevented from being peeled off, the through-holes penetrating through the semiconductor substrate have good embedding properties inside the through-holes and good adhesion to the insulating layer formed on the inner peripheral surface of the through-holes. Wiring can be formed.

請求項１の発明では、半導体基板に貫設される貫通孔の内側への埋め込み性が良好で且つ貫通孔の内周面に形成された絶縁層との密着性が良好な貫通配線を形成可能になるという効果がある。 According to the first aspect of the present invention, it is possible to form a through-wiring that has a good embedding property inside the through-hole penetrating the semiconductor substrate and a good adhesion to the insulating layer formed on the inner peripheral surface of the through-hole. There is an effect of becoming.

（実施形態１）
以下、本実施形態における半導体基板への貫通配線の形成方法について図１に基づいて説明するが、図１（ａ）〜（ｅ）における半導体基板１はダイシング工程を行う前のウェハである。また、本実施形態では、半導体基板１としてシリコン基板を用いる場合について例示する。 (Embodiment 1)
Hereinafter, a method for forming a through wiring in a semiconductor substrate according to the present embodiment will be described with reference to FIG. 1, but the semiconductor substrate 1 in FIGS. 1A to 1E is a wafer before performing a dicing process. In the present embodiment, a case where a silicon substrate is used as the semiconductor substrate 1 is illustrated.

まず、半導体基板１における貫通孔形成予定部位を反応性イオンエッチング装置や誘導結合プラズマ（ＩＣＰ）型のドライエッチング装置などを利用してドライエッチングすることで半導体基板１の厚み方向に貫通する貫通孔２を形成する貫通孔形成工程を行うことにより、図１（ａ）に示す構造を得る。ここにおいて、貫通孔形成工程では、貫通孔２の形状が、半導体基板１の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となる（言い換えれば、半導体基板１の厚み方向の中間位置から離れるほど内径が徐々に大きくなる形状となる）ように、半導体基板１の一表面側（図１（ａ）における上面側）および他表面側（図１（ａ）における下面側）それぞれからドライエッチングを行う。なお、貫通孔形成工程では、当該ドライエッチング前に貫通孔形成予定部位に対応する開孔窓を有するエッチングマスク層を形成することは勿論であり、図１（ａ）は当該ドライエッチング後にエッチングマスク層を除去した状態を示している。また、上述のような形状の貫通孔２は、例えば反応性イオンエッチング装置やＩＣＰ型のドライエッチング装置などを用いてドライエッチングを行う際のエッチング条件を適宜設定することにより形成することができる。   First, a through-hole penetrating in the thickness direction of the semiconductor substrate 1 by dry-etching a through-hole formation scheduled portion in the semiconductor substrate 1 using a reactive ion etching apparatus or an inductively coupled plasma (ICP) type dry etching apparatus. The structure shown in FIG. 1A is obtained by performing the through hole forming step for forming 2. Here, in the through-hole forming step, the shape of the through-hole 2 becomes a shape in which the opening area gradually decreases from the both sides in the thickness direction of the semiconductor substrate 1 toward the intermediate position (in other words, the thickness direction of the semiconductor substrate 1). 1) (the upper surface side in FIG. 1A) and the other surface side (the lower surface side in FIG. 1A) so that the inner diameter gradually increases as the distance from the intermediate position increases. Perform dry etching from each. In the through-hole forming step, it is a matter of course that an etching mask layer having an opening window corresponding to a through-hole formation scheduled site is formed before the dry etching. FIG. 1A shows an etching mask after the dry etching. The state where the layer is removed is shown. The through hole 2 having the above-described shape can be formed by appropriately setting the etching conditions when performing dry etching using, for example, a reactive ion etching apparatus or an ICP type dry etching apparatus.

貫通孔形成工程の後、熱酸化法やＣＶＤ法などによって半導体基板１の上記一表面および上記他表面および貫通孔２の内周面にシリコン酸化膜からなる絶縁層３を形成する絶縁層形成工程を行うことにより、図１（ｂ）に示す構造を得る。なお、絶縁層形成工程では、絶縁層３を形成した後も貫通孔２の内側では半導体基板１の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となるように絶縁層３を成膜する。また、絶縁層３をＣＶＤ法によって形成する場合には、絶縁層３をシリコン酸化膜に限らず、シリコン窒化膜により構成するようにしてもよい。   After the through hole forming step, an insulating layer forming step of forming the insulating layer 3 made of a silicon oxide film on the one surface and the other surface of the semiconductor substrate 1 and the inner peripheral surface of the through hole 2 by a thermal oxidation method, a CVD method or the like To obtain the structure shown in FIG. In the insulating layer forming step, the insulating layer is formed so that the opening area gradually decreases from the both sides in the thickness direction of the semiconductor substrate 1 toward the intermediate position after the insulating layer 3 is formed. 3 is formed. Further, when the insulating layer 3 is formed by the CVD method, the insulating layer 3 is not limited to the silicon oxide film, but may be formed of a silicon nitride film.

続いて、ＣＶＤ法、スパッタ法、真空蒸着法などによって配線材料（例えば、銅、ニッケルなどの金属材料）よりなる金属層４を絶縁層３のうち半導体基板１の上記一表面および貫通孔２の内周面に形成されている部位の表面に被着する金属層形成工程を行うことにより、図１（ｃ）に示す構造を得る。このような金属層４を形成するには、ＣＶＤ法、スパッタ法、真空蒸着法などの成膜方法があるが、ＣＶＤ法を採用すれば、金属層４をスパッタ法や真空蒸着法などによって形成する場合に比べて、貫通孔２の内側での絶縁層３の表面に対する金属層４の被覆性を向上させることができる。   Subsequently, the metal layer 4 made of a wiring material (for example, a metal material such as copper or nickel) is formed on the one surface of the semiconductor substrate 1 and the through hole 2 of the insulating layer 3 by a CVD method, a sputtering method, a vacuum deposition method, or the like. The structure shown in FIG. 1C is obtained by performing a metal layer forming step for depositing on the surface of the portion formed on the inner peripheral surface. There are film formation methods such as CVD, sputtering, and vacuum deposition to form such a metal layer 4, but if the CVD method is employed, the metal layer 4 is formed by sputtering or vacuum deposition. Compared with the case where it does, the coverage of the metal layer 4 with respect to the surface of the insulating layer 3 inside the through-hole 2 can be improved.

上述の金属層４を形成した後、金属層４をシード層として電解メッキ法によって、貫通孔２の内側が埋め込まれるように配線材料（例えば、銅、ニッケルなど）からなる金属部５を析出させる電解メッキ工程を行うことにより、図１（ｄ）に示す構造を得る。ここで、電解メッキ工程において金属層４をシード層として金属部５を析出させる際には、貫通孔２の中間位置近傍にて貫通孔２が塞がるまではコンフォーマル成長で金属部５が析出し、引き続いて半導体基板１の上記一表面側および上記他表面側それぞれへ金属部が成長していき貫通孔２の内側が金属部５によって隙間なく埋め込まれることとなり、貫通孔２の内側が金属部５によって完全に埋め込まれないうちに半導体基板１の上記一表面側や上記他表面側において貫通孔２の開口面が金属部５によって塞がれるのを防止することができる。   After the metal layer 4 is formed, the metal portion 5 made of a wiring material (for example, copper, nickel, etc.) is deposited by electrolytic plating using the metal layer 4 as a seed layer so that the inside of the through hole 2 is embedded. By performing the electrolytic plating process, the structure shown in FIG. Here, when the metal part 5 is deposited using the metal layer 4 as a seed layer in the electrolytic plating process, the metal part 5 is deposited by conformal growth until the through hole 2 is closed in the vicinity of the intermediate position of the through hole 2. Subsequently, a metal part grows on each of the one surface side and the other surface side of the semiconductor substrate 1 so that the inside of the through hole 2 is buried without any gap by the metal part 5, and the inside of the through hole 2 is the metal part. It is possible to prevent the opening surface of the through hole 2 from being blocked by the metal portion 5 on the one surface side or the other surface side of the semiconductor substrate 1 before being completely embedded by the semiconductor substrate 5.

上述の電解メッキ工程の後、半導体基板１の上記一表面側および上記他表面側それぞれの不要部分をＣＭＰによって除去する研磨工程を行うことにより、図１（ｅ）に示す構造を得る。ここにおいて、研磨工程では、半導体基板１の上記一表面側において絶縁層３が露出するまでＣＭＰを行うことにより金属部５および金属層４それぞれの不要部分を除去し、また、半導体基板１の上記他表面側において絶縁層３のうち金属部５により覆われている部位の表面が露出するまでＣＭＰを行うことにより金属部５の不要部分を除去しており、金属部５の残りの部分と金属層４の残りの部分とで貫通配線６を構成している。   After the electrolytic plating process described above, a polishing process is performed in which unnecessary portions on the one surface side and the other surface side of the semiconductor substrate 1 are removed by CMP, thereby obtaining the structure shown in FIG. Here, in the polishing step, unnecessary portions of the metal portion 5 and the metal layer 4 are removed by performing CMP until the insulating layer 3 is exposed on the one surface side of the semiconductor substrate 1, The unnecessary portion of the metal portion 5 is removed by CMP until the surface of the portion of the insulating layer 3 covered with the metal portion 5 is exposed on the other surface side, and the remaining portion of the metal portion 5 and the metal The remaining part of the layer 4 constitutes the through wiring 6.

なお、研磨工程の後は、例えば、半導体基板１の上記一表面側で貫通配線６に電気的に接続されるパッドを形成したり、半導体基板１の上記他表面側で貫通配線６に電気的に接続されるパッドを形成したりすればよい。   After the polishing step, for example, a pad that is electrically connected to the through wiring 6 on the one surface side of the semiconductor substrate 1 is formed, or the through wiring 6 is electrically connected to the other surface side of the semiconductor substrate 1. A pad connected to the substrate may be formed.

以上説明した半導体基板１への貫通配線６の形成方法によれば、従来のボトムアップ成長により金属部５を析出させる場合に比べて絶縁層３のうち貫通孔２の内側に形成されている部位と貫通配線６との密着性を向上させることができ、しかも、貫通孔２の内側が金属部５によって完全に埋め込まれないうちに半導体基板１の上記一表面側や上記他表面側において貫通孔２の開口面が金属部５によって塞がれるのを防止することができるから、半導体基板１に貫設される貫通孔２の内側への埋め込み性が良好で且つ貫通孔２の内周面に形成された絶縁層３との密着性が良好な貫通配線６を形成可能になる。   According to the method for forming the through wiring 6 in the semiconductor substrate 1 described above, the portion of the insulating layer 3 formed inside the through hole 2 as compared with the case where the metal portion 5 is deposited by conventional bottom-up growth. The through hole can be improved on the one surface side or the other surface side of the semiconductor substrate 1 before the inside of the through hole 2 is completely filled with the metal portion 5. 2 can be prevented from being blocked by the metal portion 5, so that the embedding property inside the through hole 2 penetrating the semiconductor substrate 1 is good and the inner peripheral surface of the through hole 2 is formed. The through wiring 6 having good adhesion with the formed insulating layer 3 can be formed.

また、本実施形態では、電解メッキ工程において金属部５を成長させる実質的な距離が半導体基板１の厚み寸法よりも小さくなるので、従来のボトムアップ成長により金属部を成長させる方法に比べてメッキ処理時間を大幅に短縮することが可能となる。   In the present embodiment, the substantial distance for growing the metal part 5 in the electrolytic plating step is smaller than the thickness dimension of the semiconductor substrate 1, so that the plating is performed as compared with the conventional method for growing the metal part by bottom-up growth. Processing time can be greatly reduced.

（参考例）
以下、本参考例における半導体基板への貫通配線の形成方法について図２に基づいて説明するが、図２（ａ）〜（ｈ）における半導体基板１はダイシング工程を行う前のウェハである。また、本参考例では、半導体基板１としてシリコン基板を用いる場合について例示する。 (Reference example)
Hereinafter, a method for forming the through wiring to the semiconductor substrate definitive the present embodiment will be described with reference to FIG. 2, the semiconductor substrate 1 in FIG. 2 (a) ~ (h) is a wafer prior to the dicing step. Further, in this reference example, a case where a silicon substrate is used as the semiconductor substrate 1 is illustrated.

まず、半導体基板１の一表面（図２（ａ）の上面）における貫通孔形成予定部位に有底孔（凹部）１ｂを形成する有底孔形成工程を行うことにより、図２（ａ）に示す構造を得る。ここで、有底孔形成工程では、反応性イオンエッチング装置やＩＣＰ型のドライエッチング装置などを利用して半導体基板１の上記一表面から貫通孔形成予定部位を途中までドライエッチングすることにより有底孔１ｂを形成する。なお、有底孔形成工程では、当該ドライエッチング前に貫通孔形成予定部位に対応する第１の開孔窓を有する第１のエッチングマスク層を形成することは勿論であり、図２（ａ）は当該ドライエッチング後に第１のエッチングマスク層を除去した状態を示している。   First, by performing a bottomed hole forming step of forming a bottomed hole (recessed portion) 1b at a through hole formation scheduled portion on one surface of the semiconductor substrate 1 (the upper surface of FIG. 2A), FIG. Get the structure shown. Here, in the bottomed hole forming step, the bottomed hole forming process is performed by dry-etching a portion where the through-hole is to be formed from the one surface of the semiconductor substrate 1 using a reactive ion etching apparatus or an ICP type dry etching apparatus. Hole 1b is formed. In the bottomed hole forming step, it is a matter of course that the first etching mask layer having the first aperture window corresponding to the through-hole formation scheduled site is formed before the dry etching, as shown in FIG. Shows a state in which the first etching mask layer is removed after the dry etching.

有底孔形成工程の後、ＣＶＤ法などによって半導体基板１の上記一表面および有底孔１ｂの内面にシリコン酸化膜からなる第１の絶縁層３ａを形成する第１の絶縁層形成工程を行うことにより、図２（ｂ）に示す構造を得る。なお、第１の絶縁層３ａはＣＶＤ法に限らず、熱酸化法により形成してもよい。また、第１の絶縁層３ａをＣＶＤ法によって形成する場合には、第１の絶縁層３ａをシリコン酸化膜に限らず、シリコン窒化膜により構成するようにしてもよい。   After the bottomed hole forming step, a first insulating layer forming step of forming a first insulating layer 3a made of a silicon oxide film on the one surface of the semiconductor substrate 1 and the inner surface of the bottomed hole 1b is performed by a CVD method or the like. As a result, the structure shown in FIG. The first insulating layer 3a is not limited to the CVD method, and may be formed by a thermal oxidation method. Further, when the first insulating layer 3a is formed by the CVD method, the first insulating layer 3a is not limited to the silicon oxide film, but may be formed of a silicon nitride film.

上述の第１の絶縁層形成工程の後、ＣＶＤ法、スパッタ法、真空蒸着法などによって配線材料（例えば、銅、ニッケルなどの金属材料）よりなる金属層４を第１の絶縁層３ａの表面に被着する金属層形成工程を行うことにより、図２（ｃ）に示す構造を得る。このような金属層４を形成するには、ＣＶＤ法、スパッタ法、真空蒸着法などの成膜方法があるが、ＣＶＤ法を採用すれば、金属層４をスパッタ法や真空蒸着法などによって形成する場合に比べて、貫通孔２の内側での絶縁層３の表面に対する金属層４の被覆性を向上させることができる。   After the first insulating layer forming step, the metal layer 4 made of a wiring material (for example, a metal material such as copper or nickel) is formed on the surface of the first insulating layer 3a by CVD, sputtering, vacuum deposition, or the like. The structure shown in FIG. 2C is obtained by performing a metal layer forming process to be deposited on. There are film formation methods such as CVD, sputtering, and vacuum deposition to form such a metal layer 4, but if the CVD method is employed, the metal layer 4 is formed by sputtering or vacuum deposition. Compared with the case where it does, the coverage of the metal layer 4 with respect to the surface of the insulating layer 3 inside the through-hole 2 can be improved.

上述の金属層形成工程の後、金属層４をシード層として電解メッキ法によって有底孔１ｂの内側が埋め込まれるように配線材料（例えば、銅、ニッケルなど）からなる第１の金属部５ａを析出させる第１の電解メッキ工程を行うことにより、図２（ｄ）に示す構造を得る。   After the above-described metal layer forming step, the first metal portion 5a made of a wiring material (for example, copper, nickel, etc.) is embedded so that the inside of the bottomed hole 1b is embedded by electrolytic plating using the metal layer 4 as a seed layer. The structure shown in FIG. 2D is obtained by performing the first electrolytic plating step for precipitation.

続いて、半導体基板１の上記他表面において有底孔１ｂに重なる部位を上記他表面から金属層４が露出するまでエッチングすることで半導体基板１の厚み方向に貫通する貫通孔２を形成する貫通孔形成工程を行うことにより、図２（ｅ）に示す構造を得る。ここで、貫通孔形成工程では、反応性イオンエッチング装置やＩＣＰ型のドライエッチング装置などを利用して半導体基板１の上記他表面から有底孔１ｂに重なる部位（つまり、貫通孔形成予定部位）をドライエッチングすればよい。なお、貫通孔形成工程では、当該ドライエッチング前に貫通孔形成予定部位に対応する第２の開孔窓を有する第２のエッチングマスク層を形成することは勿論であり、図２（ｅ）は当該ドライエッチング後に第２のエッチングマスク層を除去した状態を示している。   Subsequently, a portion that overlaps the bottomed hole 1b on the other surface of the semiconductor substrate 1 is etched until the metal layer 4 is exposed from the other surface, thereby forming a through hole 2 that penetrates the semiconductor substrate 1 in the thickness direction. By performing the hole forming step, the structure shown in FIG. Here, in the through hole forming step, a portion that overlaps the bottomed hole 1b from the other surface of the semiconductor substrate 1 using a reactive ion etching device, an ICP type dry etching device, or the like (that is, a through hole formation scheduled portion). May be dry-etched. In the through-hole forming step, it is a matter of course that a second etching mask layer having a second aperture window corresponding to the through-hole formation scheduled site is formed before the dry etching, and FIG. A state in which the second etching mask layer is removed after the dry etching is shown.

上述の貫通孔形成工程の後、ＣＶＤ法などによって半導体基板１の上記他表面および貫通孔２の内面の露出部位にシリコン酸化膜からなる第２の絶縁層３ｂを形成する第２の絶縁層形成工程を行うことにより、図２（ｇ）に示す構造を得る。ここで、第２の絶縁層形成工程では、図２（ｆ）に示すように、半導体基板１の上記他表面および貫通孔２の内面および金属層４および第１の絶縁層３ａの露出部位にシリコン酸化膜からなる第２の絶縁層３ｂを成膜する成膜プロセスと、当該成膜プロセスの後で、金属層４を露出させるように第２の絶縁層３ｂの不要部分を除去するパターニングプロセスとを備えている。なお、成膜プロセスでは、第１の金属部５ａの露出表面が酸化されないように低温でのシリコン酸化膜の成膜が可能なＣＶＤ法を採用することが望ましい。また、成膜プロセスにおいて第１の金属部５ａの露出表面にも絶縁層が形成される場合には、当該絶縁層をエッチングなどにより除去する必要がある。   After the above-described through-hole forming step, second insulating layer formation for forming a second insulating layer 3b made of a silicon oxide film on the exposed portion of the other surface of the semiconductor substrate 1 and the inner surface of the through-hole 2 by CVD or the like. By performing the process, the structure shown in FIG. Here, in the second insulating layer forming step, as shown in FIG. 2 (f), the other surface of the semiconductor substrate 1, the inner surface of the through hole 2, the exposed portion of the metal layer 4 and the first insulating layer 3a are formed. A film forming process for forming the second insulating layer 3b made of a silicon oxide film, and a patterning process for removing unnecessary portions of the second insulating layer 3b so as to expose the metal layer 4 after the film forming process. And. In the film forming process, it is desirable to employ a CVD method capable of forming a silicon oxide film at a low temperature so that the exposed surface of the first metal portion 5a is not oxidized. Further, when an insulating layer is also formed on the exposed surface of the first metal portion 5a in the film forming process, it is necessary to remove the insulating layer by etching or the like.

そして、上述の第２の絶縁層形成工程の後、金属層４のうち貫通孔２内で表面が露出している部位をシード層として電解メッキ法により貫通孔２の内側の充足されていない空間を埋め込む第２の金属部５ｂであり金属層４と第１の金属部５ａとともに貫通配線を構成する第２の金属部５ｂを析出させる第２の電解メッキ工程を行うことにより、図２（ｈ）に示す構造を得る。   And after the above-mentioned second insulating layer forming step, the space that is exposed in the through-hole 2 in the through-hole 2 in the metal layer 4 is used as a seed layer and the unfilled space inside the through-hole 2 by electrolytic plating. 2 (h) by depositing a second metal portion 5b that embeds the metal layer 4 and the second metal portion 5b constituting the through wiring together with the metal layer 4 and the first metal portion 5a. ) Is obtained.

上述の第２の電解メッキ工程の後は、実施形態１と同様に研磨工程を行うことにより、第１の金属部５ａおよび第２の金属部５ｂそれぞれの不要部分を除去すればよい。また、研磨工程の後は、例えば、半導体基板１の上記一表面側で貫通配線に電気的に接続されるパッドを形成したり、半導体基板１の上記他表面側で貫通配線に電気的に接続されるパッドを形成したりすればよい。   After the second electrolytic plating step described above, unnecessary portions of the first metal portion 5a and the second metal portion 5b may be removed by performing a polishing step as in the first embodiment. Further, after the polishing step, for example, a pad that is electrically connected to the through wiring on the one surface side of the semiconductor substrate 1 is formed, or is electrically connected to the through wiring on the other surface side of the semiconductor substrate 1. A pad to be formed may be formed.

しかして、本参考例の半導体基板１への貫通配線の形成方法によれば、第１の金属部５ａと金属層４と第２の金属部５ｂとで貫通配線が構成されるので、図３の従来例のように有底孔１ａの内側の金属層４と当該金属層４をシード層としてコンフォーマル成長により析出した金属部５とで貫通配線６を構成する場合に比べて、有底孔１ｂの深さ寸法を小さくできて有底孔１ｂのアスペクト比を低減できるので、有底孔１ｂの内側が第１の金属部５ａによって完全に埋め込まれないうちに半導体基板１の上記一表面側において有底孔１ｂの開口面が第１の金属部５ａによって塞がれるのを防止することができる。しかも、第２の金属部５ｂはボトムアップ成長により析出するからボイドが発生しにくく、その上、図５や図６の従来例のようにボトムアップ成長により半導体基板１の厚み方向の全長に亘って金属部５を析出させる場合に比べて絶縁層３ａ，３ｂのうち貫通孔２の内側に形成されている部位と貫通配線との密着性を向上させることができ、半導体基板１に貫設される貫通孔２の内側への埋め込み性が良好で且つ貫通孔２の内周面に形成された絶縁層３ａ，３ｂとの密着性が良好な貫通配線を形成可能になる。また、本参考例では、メッキ処理の回数は従来に比べて増えるが、１回のメッキ処理において対象となる空間の深さを半減することが可能となるので、図５や図６の従来例のようにボトムアップ成長により半導体基板１の厚み方向の全長に亘って金属部５を析出させる場合に比べて工程が容易なるとともに、メッキ処理の時間の短縮が可能となる。 Therefore, according to the method for forming the through wiring in the semiconductor substrate 1 of the present reference example , the first metal portion 5a, the metal layer 4, and the second metal portion 5b constitute the through wiring. Compared to the case where the through wiring 6 is constituted by the metal layer 4 inside the bottomed hole 1a and the metal part 5 deposited by conformal growth using the metal layer 4 as a seed layer as in the conventional example of FIG. Since the depth dimension of 1b can be reduced and the aspect ratio of the bottomed hole 1b can be reduced, the one surface side of the semiconductor substrate 1 before the inside of the bottomed hole 1b is completely filled with the first metal portion 5a. In this case, the opening surface of the bottomed hole 1b can be prevented from being blocked by the first metal portion 5a. In addition, since the second metal portion 5b is deposited by bottom-up growth, voids are unlikely to occur, and over the entire length in the thickness direction of the semiconductor substrate 1 by bottom-up growth as in the conventional examples of FIGS. Compared with the case where the metal part 5 is deposited, the adhesion between the portion of the insulating layers 3a and 3b formed inside the through hole 2 and the through wiring can be improved. It is possible to form a through-wiring having a good burying property inside the through-hole 2 and good adhesion to the insulating layers 3a and 3b formed on the inner peripheral surface of the through-hole 2. Further, in this reference example, the number of plating processes is increased as compared with the conventional case, but the depth of the target space can be halved in one plating process. Compared with the case where the metal part 5 is deposited over the entire length of the semiconductor substrate 1 by bottom-up growth as in the example, the process becomes easier and the plating process time can be shortened.

なお、上記実施形態１および参考例では、半導体基板１としてシリコン基板を採用しているが、半導体基板１はシリコン基板に限らず、例えば、ガリウム砒素基板、インジウム燐基板などを採用してもよい。 In the above real施形condition 1 and Reference Example, but the silicon substrate is adopted as the semiconductor substrate 1, the semiconductor substrate 1 is not limited to a silicon substrate, for example, a gallium arsenide substrate, such as indium phosphide substrate employing May be.

実施形態１における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。FIG. 6 is a main process cross-sectional view for explaining the method of forming the through wiring on the semiconductor substrate in the first embodiment. 参考例における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。Is a main cross-sectional views for illustrating a method of forming a through-wiring to the semiconductor substrate definitive Reference Example. 従来例における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the penetration wiring to the semiconductor substrate in a prior art example. 同上における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the penetration wiring to the semiconductor substrate in the same as the above. 他の従来例における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。It is principal process sectional drawing for demonstrating the formation method of the penetration wiring to the semiconductor substrate in another prior art example. 別の従来例における半導体基板への貫通配線の形成方法を説明するための主要工程断面図である。It is main process sectional drawing for demonstrating the formation method of the penetration wiring to the semiconductor substrate in another prior art example.

符号の説明Explanation of symbols

１ 半導体基板
２ 貫通孔
３ 絶縁層
４ 金属層
５ 金属部
６ 貫通配線 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Through-hole 3 Insulating layer 4 Metal layer 5 Metal part 6 Through wiring

Claims (1)

半導体基板への貫通配線の形成方法であって、半導体基板に厚み方向に貫通し前記厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる貫通孔を形成する貫通孔形成工程と、半導体基板の一表面および他表面および貫通孔の内周面に絶縁層を形成する絶縁層形成工程と、半導体基板の前記他表面側を除いて前記一表面側および貫通孔の内側で絶縁層の表面に金属層を被着する金属層形成工程と、金属層をシード層として電解メッキ法により貫通孔の内側を埋め込む金属部であり金属層とともに貫通配線を構成する金属部を析出させる電解メッキ工程とを備え、絶縁層形成工程では、絶縁層を形成した後も貫通孔の内側では半導体基板の厚み方向の両側から中間位置に近づくにつれて開口面積が徐々に小さくなる形状となるように絶縁層を成膜することを特徴とする半導体基板への貫通配線の形成方法。 A through hole forming step for forming a through wiring on a semiconductor substrate, wherein a through hole is formed in the semiconductor substrate in the thickness direction and the opening area gradually decreases as the position approaches the intermediate position from both sides of the thickness direction; An insulating layer forming step of forming an insulating layer on one surface and the other surface of the semiconductor substrate and an inner peripheral surface of the through hole; and an insulating layer formed on the one surface side and inside the through hole except for the other surface side of the semiconductor substrate. A metal layer forming step for depositing a metal layer on the surface, and an electroplating step for depositing a metal portion that embeds the inside of the through-hole by an electrolytic plating method using the metal layer as a seed layer and that forms a through-wire together with the metal layer In the insulating layer forming step, the opening area gradually decreases from the both sides in the thickness direction of the semiconductor substrate toward the intermediate position inside the through hole even after the insulating layer is formed. Method for forming a through-wiring to the semiconductor substrate, characterized by forming an insulating layer so.
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