CN111863754A - A through-silicon via interconnect structure with an inner confinement ring and a method for forming the same - Google Patents

Abstract

A through silicon via interconnect structure with an internal retaining ring and a method of forming the same, the through silicon via interconnect structure comprising: the device comprises a substrate, a first insulating layer and a second insulating layer, wherein at least one through hole is formed in the substrate; a first insulating layer disposed on an upper end face and a lower end face of the substrate; a second insulating layer disposed on an inner wall of the through-hole; the seed layer is arranged on the surface of the second insulating layer in the through hole; the metal layer is filled and arranged on the inner side of the seed layer; and the limiting part is arranged on the through hole, the second insulating layer, the seed layer and the metal layer. The invention has simple process, lower cost and high reliability, and the manufactured silicon through hole structure has higher thermomechanical reliability and higher practical value due to the existence of the internal limiting ring.

Description

A through-silicon via interconnect structure with an inner confinement ring and a method for forming the same

technical field

The invention relates to the field of microelectronic packaging, in particular to a through-silicon via interconnection structure with an inner confinement ring and a method for forming the same.

Background technique

With the continuous development of MEMS to miniaturization, high density and three-dimensional stacking technology, interconnection technology using through silicon vias has become one of the advanced technologies in the semiconductor industry. Through silicon via interconnection technology is a high-density packaging technology, which is gradually replacing the current wire bonding technology with relatively mature technology, and is considered to be the fourth-generation packaging technology. The so-called through-silicon via interconnection technology establishes a vertical electrical connection from the front to the back of the silicon wafer through the through holes of the silicon wafer, thereby realizing the vertical conduction between the multi-layer stack of chips and chips, wafers and wafers. The packaging density and degrees of freedom are greatly improved, providing a method for three-dimensional stacking technology. This technology can be used not only in the field of microelectronics, but also in the fields of mechanics, acoustics, fluids, optoelectronics, biomedicine, etc. This new technology is often developed on a separate chip due to rapidly growing market demands for pressure sensors, accelerometers and gyroscopes, projected micromirrors, inkjet printheads, etc.

TSVs are usually tens of microns in diameter, with aspect ratios up to 50, and are usually filled with copper. Since the current fabrication technology of the seed layer is not perfect enough to realize the deposition of the deep hole seed layer, the current through-silicon via structure fabricated by the metal filling method cannot meet the needs of MEMS packaging. At the same time, due to the mismatch of the coefficient of thermal expansion (CTE) between the copper metal layer filled with the TSV and the silicon material outside the hole, when the heat in the TSV interconnect structure area in the device increases (the heat can come from the service as a signal channel) The through-silicon via interconnect structure is self-heating, and it can also come from an environmental heat source), and the thermomechanical stress caused by the mismatch of the thermal expansion coefficient of the material in the through-silicon via interconnect structure area is further aggravated, usually manifested as the copper metal layer bulging out, increasing the chip There is a risk of localized delamination that could eventually lead to device failure. Therefore, the realization of deep hole metal filling and the reduction of damage caused by thermal stress of TSVs are urgent problems to be solved.

In order to solve the above problems, it is currently considered to reduce the temperature around the TSV interconnect structure by means of external heat dissipation, thereby reducing the degree of thermal expansion coefficient mismatch. However, the method of external heat dissipation is expensive, and the heat dissipation effect is not ideal. Therefore, it is very necessary to develop a TSV interconnect structure fabrication process with better heat dissipation effect, deeper via filling and lower cost, so as to prevent the copper metal layer filled with TSV from expanding outward after being heated and destroying the internal structure of the chip. connection point between.

SUMMARY OF THE INVENTION

In order to effectively solve the above-mentioned deficiencies of the background technology, an internal limit ring structure is formed inside the through hole by a step-by-step deep silicon etching process to replace the traditional etching process, and the through hole metal is completely filled by a double-sided blind hole electroplating process. , a fabrication process of a TSV structure with an internal limiting ring is designed. The internal limit ring structure can effectively fix the filler metal in a high temperature environment. Specifically, the temperature causes the metal to expand, and the internal limit ring structure fixes the metal to prevent the metal from detaching from the TSV, thereby prolonging the life of the chip in a high temperature environment.

A through-silicon via interconnection structure with an inner confinement ring can work stably in a high temperature environment of 300° C. for a long time, and the through-silicon via interconnection structure includes:

a substrate, at least one through hole is formed on the substrate;

a first insulating layer, the first insulating layer is disposed on the upper end face and the lower end face of the substrate;

a second insulating layer, the second insulating layer is disposed on the inner wall of the through hole;

a seed layer, the seed layer is arranged on the surface of the second insulating layer in the through hole;

a metal layer, the metal layer is filled and arranged inside the seed layer;

and a limiting portion disposed on the through hole, the second insulating layer, the seed layer and the metal layer.

Optionally, the limiting portion includes: a first concave portion disposed on the inner wall of the through hole, and the inner wall of the through hole is provided with at least one annular first concave portion disposed on the second insulating layer The second concave part, the third concave part arranged on the seed layer and the limiting ring arranged on the first metal layer.

Optionally, the second concave portion is positioned corresponding to the first concave portion of the through hole and the shape is adapted to the first concave portion, and the third concave portion corresponds to the second concave portion of the second insulating layer. The position is set and the shape is adapted to the second recess, and the limit ring is positioned corresponding to the position of the third recess of the seed layer and the shape is adapted to the third recess.

Optionally, the through holes are distributed in an array, and the array distribution of the through holes includes: circle, ring, sector, rectangle, parallelogram or trapezoid.

Optionally, the first concave parts are evenly arranged on the upper part, the middle part and/or the lower part of the inner wall of the through hole.

Optionally, the first concave parts are non-uniformly arranged on the inner wall of the through hole, and the first concave parts have a symmetric or asymmetric structure.

Optionally, the limiting ring is integrally formed on the surface of the metal layer, the number of the limiting ring is at least one, and the limiting ring is a symmetrical or asymmetrical structure.

A method for forming a through-silicon via interconnect structure with an inner confinement ring, the method comprising the steps of:

S1. Provide a semiconductor substrate, use a deep silicon etching process to etch blind holes on the surface of the substrate, and use a step-by-step deep silicon etching process to form a first recess during the etching process;

S2, using a dry-wet dry-oxidation process to make a first insulating layer and a second insulating layer on the surface of the substrate and the through holes, respectively;

S3, using a magnetron sputtering process to deposit a seed layer on the surface of the second insulating layer in the through hole;

S4, using a double-sided blind hole electroplating process to fill the space inside the seed layer in the through hole to form a metal layer;

S5, using a chemical mechanical polishing process to remove the metal layers on the two end faces of the substrate to make the end faces flat.

Optionally, the step-by-step deep silicon etching process in the step S1 is specifically: using the Bosch process to perform deep silicon etching on the substrate on which the photolithography process has been completed, according to the target depth of the etching and the etching rate of the etching equipment. Set the etching time, and make the etching depth reach the set value through multiple and segmented etching. After each deep silicon etching is completed, the gas remaining in the etching chamber is completely discharged, and after a short wait For the next etch, repeat the above steps until the target depth is reached and then stop.

Optionally, the step S4 double-sided blind hole electroplating process includes the following steps:

S4.1. Use the electroplating process to fill the blind hole with metal material from one end of the substrate;

S4.2. Use the thinning and polishing process to leak out the blind hole on the other end face of the substrate;

S4.3. Use an electroplating process to fill the blind hole with metal material from the other end of the substrate, so that the metal pillars filled on the two end faces form a whole.

The beneficial effect of the present invention is that the present invention forms a unique confinement ring structure in the through hole through multiple deep silicon etchings, so that the through hole interconnection structure has a higher adhesion ability to the metal column and greatly reduces heat Under the influence of stress, it can work stably in a high temperature environment of 300 ° C for a long time, and is suitable for the electrical interconnection of various chips working in high temperature environments. The use of double-sided blind hole electroplating to realize safe filling of deep holes makes the through-hole interconnection structure fabricated. With a depth of more than 200 μm, it can be widely used in MEMS packaging, three-dimensional packaging of integrated circuit devices, etc.

The process of the invention is simple, the cost is low, and the reliability is high, and the fabricated through-silicon via structure has high thermo-mechanical reliability and high practical value due to the existence of the inner limit ring.

Description of drawings

1 is an external schematic diagram of the through-silicon via interconnection structure of the present invention;

FIG. 2 is an internal schematic diagram of the through-silicon via interconnection structure of the present invention;

FIG. 3 is a schematic structural diagram of a plurality of limiting rings in the TSV of the present invention;

4 is a schematic bottom view of the through-silicon via interconnection structure of the present invention;

FIG. 5 is a schematic diagram of a partially enlarged structure of the through-silicon via interconnection structure of the present invention;

As shown in the figure, the list of reference numerals is as follows:

1-substrate; 2,3-first insulating layer; 8,9-second insulating layer; 4,6,7-seed layer; 5-metal layer; 10,11,12-limiting ring; 13-pass hole; 14-first recess; 15-second recess; 16-third recess.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", etc. is based on the attached The orientation or positional relationship shown in the figures is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated combination or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a reference to the present invention. Invention limitations. In addition, during the description of the embodiments of the present invention, the positional relationships of components such as "up", "down", "front", "rear", "left", and "right" in all figures are based on FIG. 1 .

In the description of the present invention, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication between the two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

The present invention will be further described below in conjunction with the accompanying drawings:

As shown in FIG. 1-2, which is a perspective view of the appearance of the first embodiment of the present invention, a through-silicon via interconnection structure with an inner limit ring is provided, which can work stably in a high temperature environment of 300°C for a long time. Via interconnect structures include:

Substrate 1, at least one through hole 13 is formed on the substrate 1;

first insulating layers 2, 3, the first insulating layers 2, 3 are arranged on the upper end face and the lower end face of the substrate 1;

second insulating layers 8, 9, the second insulating layers 8, 9 are disposed on the inner walls of the through holes 13;

Seed layers 4, 6, 7, the seed layers 4, 6, 7 are arranged on the surfaces of the second insulating layers 8, 9 in the through hole 13;

Metal layer 5, the metal layer 5 is filled and arranged inside the seed layers 4, 6, 7;

And the limiting parts provided on the through holes 13 , the second insulating layers 8 , 9 , the seed layers 4 , 6 , 7 and the metal layer 5 .

As shown in FIGS. 2 , 3 and 5 , the limiting portion includes: a first concave portion 14 disposed on the inner wall of the through hole 13 , and at least one annular first concave portion 14 is disposed on the inner wall of the through hole 13 , the second recesses 15 arranged on the second insulating layers 8 and 9 , the third recesses 16 arranged on the seed layers 4 , 6 and 7 , and the limiter arranged on the first metal layer 5 Bit rings 10, 11, 12.

As shown in FIGS. 2 , 3 and 5 , the second concave portion 15 is positioned corresponding to the first concave portion 14 of the through hole 13 and the shape is adapted to the first concave portion 14 , and the third concave portion 16 corresponds to the first concave portion 14 . The second concave portions 15 of the second insulating layers 8 and 9 are positioned and adapted in shape to the second concave portions 15 , and the limiting rings 10 , 11 and 12 correspond to the third The position of the recessed portion 16 is set and the shape is adapted to the third recessed portion 16 .

As shown in FIG. 1 , the substrate 1 as a whole can be in any three-dimensional geometric shape, including: cylinder, cube, cuboid and other shapes, which are not specifically limited. In the accompanying drawings of the present invention, only the cuboid structure is shown.

As shown in FIG. 1 , the through hole 13 provided on the substrate 1 is used to fabricate a through silicon via interconnection structure, and the shape of the through hole 13 includes but is not limited to: circle, rectangle or parallelogram. The through holes 13 may also be distributed in an array, and the array distribution of the through holes 13 may be circular, annular, fan-shaped, rectangular, parallelogram or trapezoidal. The material of the substrate 1 can be made of Si material. Preferably, the substrate 1 is made of high-resistance silicon. The inside of the through hole 13 is filled with the second insulating layers 8 , 9 , the seed layers 4 , 6 , 7 , and the metal layer 5 sequentially from the outside to the inside.

As shown in FIGS. 2 , 3 and 5 , the first concave portion 14 is formed on the inner wall of the through hole 13 through a distributed etching process. The first concave parts 14 may be uniformly arranged on the upper part, the middle part and/or the lower part of the inner wall of the through hole 13 . The first concave parts 14 may also be non-uniformly arranged on the inner wall of the through hole 13 . The first concave portion 14 may be one, two or more. The shape of the first concave portion 14 includes, but is not limited to, a circle, a rectangle or a parallelogram adapted to the cross-sectional shape of the through hole 13 . The distribution of the first recesses 14 in the through holes 13 may be symmetrical or asymmetrical.

As shown in FIGS. 2 , 3 and 5 , the first insulating layers 2 and 3 and the second insulating layers 8 and 9 are attached to the substrate 1 through a high-temperature thermal oxidation process, and the first insulating layer formed by the high-temperature thermal oxidation process 2, 3 and the second insulating layers 8, 9 can be closely attached to the surface of the substrate 1, not easy to fall off, and can completely cover the interior of the through hole 13. Preferably, the first insulating layers 2 and 3 are formed on the upper end surface and the lower end surface of the substrate 1 by a dry-wet dry oxidation process, and the second insulating layers 8 and 9 are formed on the through holes by a dry-wet dry oxidation process. 13 on the inner wall. The first insulating layers 2 and 3 and the second insulating layers 8 and 9 can be made of SiO ₂ , SiN, SiON or other low-K materials. The covering of the first insulating layers 2 and 3 and the second insulating layers 8 and 9 insulates the substrate 1 and provides certain protection to the substrate 1 at the same time.

Since the through hole 13 of the substrate 1 has the first concave portion 14 , when the second insulating layers 8 and 9 are formed on the inner wall of the through hole 13 , they will be attached to the inner wall of the first concave portion 14 to form a fitting The second recess 15 in the shape of the first recess 14 .

As shown in FIGS. 2 , 3 and 5 , the seed layers 4 , 6 and 7 can be attached to the surfaces of the second insulating layers 8 and 9 by a magnetron sputtering process, and the seed layers 4 , 6 and 7 can be Including one or more of TaN, Ta, TiN, and Ti materials. Since the second insulating layers 8 and 9 have the second recesses 15 , when the seed layers 4 , 6 and 7 are formed on the second insulating layers 8 and 9 , they will be attached to the inner walls of the second recesses 15 . , forming a third recessed portion 16 adapted to the shape of the second recessed portion 15 .

As shown in FIGS. 2-5 , the metal layer 5 is completely filled in the annular space defined by the second insulating layers 8 , 9 and the seed layers 4 , 6 , 7 , and the metal layer 5 can pass through The double-sided blind hole electroplating process is formed, and the metal layer 5 is deposited and filled inside the seed layers 4 , 6 , and 7 . The metal layer 5 can be made of Cu, Al or W material. Through the double-sided blind hole electroplating process, the metal filling of deep holes can be realized, the thickness of the metal that can be filled can be increased, and the thickness of the silicon wafer substrate 1 after the through silicon via structure is also increased, so that it can meet the requirements of MEMS packaging for silicon wafer lining. The reliability requirements of bottom 1;

As shown in FIGS. 2 , 3 and 5 , the limiting rings 10 , 11 and 12 are integrally formed on the surface of the metal layer 5 . Since the seed layers 4 , 6 and 7 have third recesses 16 , the During the formation process of the metal layer 5 inside the seed layers 4 , 6 , and 7 , the metal layer 5 will completely fill the third recess 16 , so that the surface of the metal layer 5 forms an annular limit adapted to the shape of the third recess 16 . Bit raised. The limiting rings 10 , 11 , 12 are adapted to fit the third concave portion 16 , which may be one or more, and the limiting rings 10 , 11 , 12 may be distributed symmetrically or asymmetrically. The limiting rings 10 , 11 , and 12 can improve the fixation of the metal layer 5 in the through hole 13 and achieve better effects.

When the chip is in a high temperature environment, due to the different properties of the constituent materials of each part, thermal mismatch will occur, and the metal layer 5 in the TSV interconnect structure expands. The existence of the third recessed portion 16 and the limiting rings 10 , 11 , and 12 makes the metal layer 5 fixed in the through silicon via interconnection structure and cannot be detached, which improves the working time and upper limit of the working temperature of the chip in a high temperature environment, and ensures that the The electrical interconnection of each part of the chip is realized, so that the chip can work stably in a high temperature environment for a long time.

A method for forming a through-silicon via interconnect structure with an inner confinement ring, the method comprising the steps of:

S1. Provide a semiconductor substrate, use a deep silicon etching process to etch blind holes on the surface of the substrate, and use a step-by-step deep silicon etching process to form a first recess during the etching process;

S2, using a dry-wet dry-oxidation process to form a first insulating layer and a second insulating layer on the surface of the substrate and in the blind holes, respectively;

S3, using a magnetron sputtering process to deposit a seed layer on the surface of the second insulating layer in the blind hole;

S4, using a double-sided blind hole electroplating process to fill the space inside the seed layer in the blind hole to form a metal layer;

S5, using a chemical mechanical polishing process to remove the metal layers on the two end faces of the substrate to make the end faces flat.

The deep silicon etching process in the step S1 is specifically: using the Bosch process to perform conventional deep silicon etching on the substrate on which the photolithography process has been completed.

The step-by-step deep silicon etching process in the step S1 is specifically as follows: using the Bosch process to perform deep silicon etching on the substrate on which the photolithography process is completed, and setting the etching according to the target depth of the etching and the etching rate of the etching equipment The etching depth reaches the set value through multiple and segmented etchings. After each deep silicon etching is completed, the residual gas in the etching chamber is completely discharged, and the next etching is performed after a short wait. etch, repeat the above steps until the target depth is reached and stop.

The step-by-step deep silicon etching process may be divided into two-step, three-step or multi-step deep silicon etching to etch the substrate 1 .

The step S4 double-sided blind hole electroplating process includes the following steps:

S4.1. Use the electroplating process to fill the blind hole with metal material from one end of the substrate;

S4.2. Use the thinning and polishing process to leak out the blind hole on the other end face of the substrate;

S4.3. Use an electroplating process to fill the blind hole with metal material from the other end of the substrate, so that the metal pillars filled on the two end faces form a whole.

The metal material includes: Cu, Al or W material.

When the through-silicon via interconnection structure is filled by the double-sided blind-hole electroplating method, the bottom of the through-hole 13 is in a closed state during the two electroplating times, and the whole is open at one end.

The principle of the present invention is:

Taking advantage of the feature that each etching of the Bosch process will expand the etching window, a deep silicon etching to reach the target depth is replaced with multiple deep silicon etchings to reach the target depth, and a direction will be formed between two adjacent deep silicon etchings. In the inner recessed annular structure, the metal layer formed after the metal filling is completed will be embedded in the through hole. Through the step-by-step deep silicon etching method, the TSV structure forms an internal confinement ring structure, which improves the fixing ability of the filler metal, greatly reduces the damage to the structure due to thermal stress, and prolongs the TSV structure in high temperature environments. The working time can be applied to extremely harsh high temperature working environment, which improves the high temperature reliability of the chip, thereby improving the working life of the chip. It is a very ideal high temperature resistant TSV structure.

The beneficial effects of the present invention are:

The invention forms a unique limiting ring structure in the through hole through multiple deep silicon etching, so that the through hole interconnection structure has a high adhesion ability to the metal column, greatly reduces the influence of thermal stress, and can work stably for a long time In the high temperature environment of 300 ℃, it is suitable for the electrical interconnection of various chips working in high temperature environment. The double-sided blind hole electroplating is used to realize the safe filling of deep holes, so that the through-hole interconnection structure can reach a depth of more than 200 μm. Widely used in MEMS packaging, three-dimensional packaging of integrated circuit devices, etc.

The process of the invention is simple, the cost is low, and the reliability is high, and the fabricated through-silicon via structure has high thermo-mechanical reliability and high practical value due to the existence of the inner limit ring.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," or the like, is meant to incorporate the embodiment. A particular feature, structure, material, or characteristic described by an example or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, The scope of the invention is defined by the claims and their equivalents.

Claims (10)

1. A through-silicon via interconnect structure with an internal limiting ring, capable of long-term stable operation in a high temperature environment of 300 ℃, the through-silicon via comprising:

the device comprises a substrate (1), wherein at least one through hole (13) is formed in the substrate (1);

first insulating layers (2, 3), the first insulating layers (2, 3) being provided on upper and lower end faces of the substrate (1);

a second insulating layer (8, 9), the second insulating layer (8, 9) being disposed on an inner wall of the through-hole (13);

a seed layer (4, 6, 7), the seed layer (4, 6, 7) being disposed on a surface of the second insulating layer (8, 9) within the via hole (13);

the metal layer (5) is filled in the seed layers (4, 6, 7);

and a limiting part arranged on the through hole (13), the second insulating layers (8, 9), the seed layers (4, 6, 7) and the metal layer (5).

2. The tsv interconnect structure with an internal stopper ring according to claim 1, wherein the stopper portion comprises: the seed layer structure comprises a first sunken part (14) arranged on the inner wall of the through hole (13), at least one annular first sunken part (14) arranged on the inner wall of the through hole (13), a second sunken part (15) arranged on the second insulating layer (8, 9), a third sunken part (16) arranged on the seed layer (4, 6, 7) and a limiting ring (10, 11, 12) arranged on the second metal layer (5).

3. The TSV interconnect structure with an internal retaining ring according to claim 2, wherein the second recess (15) is located and form-fitted to the first recess (14) of the via (13), the third recess (16) is located and form-fitted to the second recess (15) of the second insulating layer (8, 9), and the retaining ring (10, 11, 12) is located and form-fitted to the third recess (16) of the seed layer (4, 6, 7).

4. The through-silicon-via interconnect structure with internal retaining ring according to claim 1, wherein the through-holes (13) are distributed in an array, and the array distribution of the through-holes (13) comprises: circular, annular, fan-shaped, rectangular, parallelogram or trapezoidal arrangement.

5. The TSV interconnect structure having an internal limiting ring according to claim 2, wherein the first recesses (14) are uniformly arranged at upper, middle and/or lower portions of the inner wall of the through hole (13).

6. The TSV interconnect structure with an internal retaining ring according to claim 2, wherein the first recesses (14) are non-uniformly arranged on the inner wall of the through hole (13), and the first recesses (14) are symmetrical or asymmetrical.

7. The TSV interconnect structure with an internal retaining ring according to claim 2, wherein the retaining rings (10, 11, 12) are integrally formed on the surface of the metal layer (5), the number of the retaining rings (10, 11, 12) is at least one, and the retaining rings (10, 11, 12) are symmetrical or asymmetrical.

8. A method for forming a through silicon via interconnection structure with an internal limiting ring is characterized by comprising the following steps:

s1, providing a semiconductor substrate, etching the surface of the substrate by using a deep silicon etching process to manufacture a blind hole, and forming a first concave part by adopting a step-by-step deep silicon etching process in the etching process;

s2, manufacturing a first insulating layer and a second insulating layer on the surface of the substrate and the through hole respectively by using a dry-wet dry oxidation process;

s3, depositing a seed layer on the surface of the second insulating layer in the through hole by using a magnetron sputtering process;

s4, filling the space inside the seed layer in the through hole by using a double-sided blind hole electroplating process to form a metal layer;

and S5, removing the metal layers on the two end faces of the substrate by using a chemical mechanical polishing process to make the end faces flat.

9. The method for forming the through-silicon-via interconnection structure with the internal limiting ring according to claim 8, wherein the step-by-step deep silicon etching process in the step S1 specifically comprises: and carrying out deep silicon etching on the substrate which is subjected to the photoetching process by using a Bosch process, setting etching time according to the etching target depth and the etching rate of etching equipment, enabling the etching depth to reach a set value by carrying out multiple times of segmented etching, completely discharging gas remained in an etching chamber after the deep silicon etching is finished each time, carrying out next etching after short waiting, and repeating the steps until the target depth is reached.

10. The method for forming a through silicon via interconnection structure with an internal limiting ring according to claim 8, wherein the step S4 double-sided blind hole electroplating process comprises the following steps:

s4.1, filling the blind hole with a metal material from one end face of the substrate by using an electroplating process;

s4.2, leaking the blind hole on the other end face of the substrate by using a thinning and polishing process;

and S4.3, filling the blind hole with a metal material from the other end face of the substrate by using an electroplating process, so that the metal columns filled on the two end faces form a whole.

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