CN212934602U

CN212934602U - Through-silicon-via interconnection structure with internal limiting ring

Info

Publication number: CN212934602U
Application number: CN202021831461.0U
Authority: CN
Inventors: 王俊强; 李孟委; 李明浩
Original assignee: North University of China
Current assignee: North University of China
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2021-04-09
Anticipated expiration: 2030-08-28

Abstract

A through silicon via interconnect structure having an internal retaining ring, the through silicon via interconnect structure comprising: the device comprises a substrate, a first insulating layer and a second insulating layer, wherein at least one through hole is formed in the substrate; a first insulating layer disposed on an upper end face and a lower end face of the substrate; a second insulating layer disposed on an inner wall of the through-hole; the seed layer is arranged on the surface of the second insulating layer in the through hole; the metal layer is filled and arranged on the inner side of the seed layer; and the limiting part is arranged on the through hole, the second insulating layer, the seed layer and the metal layer. The utility model discloses simple process, the cost is lower, and the reliability is high, and the through-silicon via structure of preparation has higher thermomechanical reliability because the existence of inside spacing ring, has very high practical value.

Description

Through-silicon-via interconnection structure with internal limiting ring

Technical Field

The utility model relates to a microelectronics packaging field, concretely relates to through-silicon via interconnect structure with inside spacing ring.

Background

With the development of micro-electromechanical systems towards miniaturization, high density and three-dimensional stacking technologies, the interconnection technology using through silicon vias has become one of the advanced technologies in the semiconductor industry. Through silicon via interconnection is a high-density packaging technology, and is gradually replacing the mature wire bonding technology in the current technology, which is considered as a fourth generation packaging technology. The through silicon via interconnection technology is to establish vertical electrical connection from the front side to the back side of a silicon wafer through a through hole of the silicon wafer, so that vertical conduction between chips and between wafers and between wafer and wafer multilayer stacking is realized, the packaging density and the degree of freedom are greatly improved, and a method is provided for the three-dimensional stacking technology. This technology can be used not only in the field of microelectronics, but also in the fields of mechanics, acoustics, fluidics, optoelectronics, biomedicine, etc. Due to the rapidly growing market demand for pressure sensors, accelerometers and gyroscopes, projection micromirrors, inkjet printheads, and the like, this new technology is often developed on a separate chip.

Through-silicon vias typically have a diameter of tens of microns and an aspect ratio of up to 50, and are typically filled with copper. Because the current seed layer manufacturing technology is not perfect enough, the seed layer deposition of the deep hole cannot be realized, and the silicon through hole structure manufactured by the current metal filling mode cannot meet the requirement of MEMS packaging. Meanwhile, due to the problem of Coefficient of Thermal Expansion (CTE) mismatch between the copper metal layer filled in the through silicon via and the extra-via silicon material, when the heat of the through silicon via interconnection structure area in the device is increased (the heat can be self-heated from the through silicon via interconnection structure serving as a signal channel or from an environmental heat source), the thermomechanical stress caused by the CTE mismatch of the material in the through silicon via interconnection structure area is further increased, which is usually manifested as the copper metal layer bulging, the risk of local chip delamination is increased, and finally the device failure may be caused. Therefore, the implementation of deep hole metal filling and the reduction of damage caused by thermal stress of the through silicon via are problems to be solved urgently.

In order to solve the above problems, it is currently considered to reduce the temperature around the tsv interconnect structure by means of external heat dissipation, so as to reduce the degree of thermal expansion coefficient mismatch. However, the external heat dissipation method is costly and the heat dissipation effect is not ideal. Therefore, it is necessary to develop a manufacturing process of a through silicon via interconnection structure with better heat dissipation effect, deeper through hole filling and lower cost, and the copper metal layer filled in the through silicon via is prevented from expanding outwards after being heated to damage connection points between chips.

SUMMERY OF THE UTILITY MODEL

In order to effectively solve the defects of the background technical problem, an internal limiting ring structure is formed inside a through hole through a step-by-step deep silicon etching process to replace the traditional etching process, and through hole metal is completely filled through a double-sided blind hole electroplating process, so that the manufacturing process of the silicon through hole structure with the internal limiting ring is designed. Inside spacing ring structure can be under high temperature environment fixed filler metal effectively, and specifically the temperature leads to the metal expansion, and inside spacing ring structure is fixed with the metal, avoids the metal to break away from the through-silicon via to the life-span of chip under the extension high temperature environment.

A through silicon via interconnect structure with an internal limiting ring, which can stably operate in a high temperature environment of 300 ℃ for a long time, the through silicon via interconnect structure comprising:

the device comprises a substrate, a first insulating layer and a second insulating layer, wherein at least one through hole is formed in the substrate;

a first insulating layer disposed on an upper end face and a lower end face of the substrate;

a second insulating layer disposed on an inner wall of the through-hole;

the seed layer is arranged on the surface of the second insulating layer in the through hole;

the metal layer is filled and arranged on the inner side of the seed layer;

and the limiting part is arranged on the through hole, the second insulating layer, the seed layer and the metal layer.

Optionally, the limiting portion includes: the first sunken part is arranged on the inner wall of the through hole, at least one annular first sunken part, a second sunken part, a third sunken part and a limiting ring are arranged on the metal layer, wherein the first sunken part, the second sunken part, the third sunken part and the limiting ring are arranged on the second insulating layer.

Optionally, the second recess is disposed corresponding to the first recess of the through hole and is shape-matched to the first recess, the third recess is disposed corresponding to the second recess of the second insulating layer and is shape-matched to the second recess, and the limiting ring is disposed corresponding to the third recess of the seed layer and is shape-matched to the third recess.

Optionally, the through holes are distributed in an array, and the array distribution of the through holes includes: circular, annular, fan-shaped, rectangular, parallelogram or trapezoidal arrangement.

Optionally, the first concave parts are uniformly distributed on the upper part, the middle part and/or the lower part of the inner wall of the through hole.

Optionally, the first recesses are non-uniformly arranged on the inner wall of the through hole, and the first recesses are of a symmetrical or asymmetrical structure.

Optionally, the limiting ring is integrally formed on the surface of the metal layer, the number of the limiting rings is at least one, and the limiting ring has a symmetrical or asymmetrical structure.

The beneficial effects of the utility model reside in that, the utility model discloses a dark silicon etching forms unique spacing ring structure in the through-hole many times for this through-hole interconnect structure has higher adhesive force to the metal column, greatly reduce the influence of thermal stress, can work in 300 ℃ high temperature environment for a long time steadily, be applicable to the electricity interconnection of various work in high temperature environment's chip, utilize the safe filling of two-sided blind hole electroplating realization deep hole to make the through-hole interconnect structure of preparation reach the degree of depth more than 200 mu m, can be applied to MEMS encapsulation widely, the three-dimensional encapsulation of integrated circuit device etc.

The utility model discloses simple process, the cost is lower, and the reliability is high, and the through-silicon via structure of preparation has higher thermomechanical reliability because the existence of inside spacing ring, has very high practical value.

Drawings

FIG. 1 is an external schematic view of a through-silicon via interconnect structure of the present invention;

FIG. 2 is an internal schematic view of a through-silicon via interconnect structure of the present invention;

FIG. 3 is a schematic structural view of a plurality of limiting rings in a through-silicon-via of the present invention;

fig. 4 is a schematic bottom view of the through-silicon via interconnection structure of the present invention;

FIG. 5 is a schematic diagram of a partial enlarged structure of a through-silicon-via interconnection structure of the present invention;

as shown in the figures, the list of reference numbers is as follows:

1-a substrate; 2. 3-a first insulating layer; 8. 9-a second insulating layer; 4. 6, 7-seed layer; 5-a metal layer; 10. 11, 12-a spacing ring; 13-a through hole; 14-a first recess; 15-a second recess; 16-third recess.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the combination or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. In addition, in the description process of the embodiment of the present invention, the position relationships of the devices such as "up", "down", "front", "back", "left", "right" in all the drawings all use fig. 1 as a standard.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The present invention will be further explained with reference to the accompanying drawings:

as shown in fig. 1-2, for the perspective view of the first embodiment of the present invention, a through silicon via interconnection structure with an internal limiting ring is provided, which can stably operate in a high temperature environment of 300 ℃ for a long time, the through silicon via interconnection structure includes:

the structure comprises a substrate 1, wherein at least one through hole 13 is formed in the substrate 1;

first

insulating layers

2, 3, the first

insulating layers

2, 3 being provided on upper and lower end faces of the substrate 1;

second

insulating layers

8, 9, the second

insulating layers

8, 9 being disposed on inner walls of the through holes 13;

seed layers

4, 6, 7, wherein the

seed layers

4, 6, 7 are arranged on the surfaces of the second

insulating layers

8, 9 in the through hole 13;

the metal layer 5 is filled inside the

seed layers

4, 6 and 7;

and a stopper portion provided on the through hole 13, the second

insulating layers

8, 9, the

seed layers

4, 6, 7 and the metal layer 5.

As shown in fig. 2, 3 and 5, the stopper portion includes: the first concave part 14 is arranged on the inner wall of the through hole 13, the inner wall of the through hole 13 is provided with at least one annular first concave part 14, the second concave part 15 is arranged on the second

insulating layers

8 and 9, the third concave part 16 is arranged on the

seed layers

4, 6 and 7, and the limiting

rings

10, 11 and 12 are arranged on the metal layer 5.

As shown in fig. 2, 3 and 5, the second recess 15 is located and shaped to fit the first recess 14 of the through hole 13, the third recess 16 is located and shaped to fit the second recess 15 of the second

insulating layer

8, 9, and the

stopper rings

10, 11 and 12 are located and shaped to fit the third recess 16 of the

seed layer

4, 6 and 7.

As shown in fig. 1, the substrate 1 may have any solid geometry as a whole, including: cylinder, cube, cuboid wait shape to do not specifically limit, in the utility model discloses the drawing, only shown the cuboid structure.

As shown in fig. 1, a through hole 13 is disposed on the substrate 1 for making a through silicon via interconnection structure, and the shape of the through hole 13 includes but is not limited to: circular, rectangular or parallelogram. The through holes 13 may also be distributed in an array, and the array distribution of the through holes 13 is circular, annular, fan-shaped, rectangular, parallelogram or trapezoidal. The substrate 1 can be made of a Si material, and preferably, the substrate 1 is made of high-resistance silicon. The through hole 13 is filled with the second insulating

layers

8 and 9, the seed layers 4, 6 and 7 and the metal layer 5 from outside to inside in sequence.

As shown in fig. 2, 3 and 5, the first recess 14 is formed on the inner wall of the through hole 13 by a distributed etching process. The first recesses 14 may be uniformly arranged at upper, middle and/or lower portions of the inner wall of the through-hole 13. The first recesses 14 may be non-uniformly arranged on the inner wall of the through hole 13. The first recess 14 may be one, two or more. The shape of the first recess 14 includes, but is not limited to, a circle, a rectangle, or a parallelogram to fit the cross-sectional shape of the through-hole 13. The distribution of the first recesses 14 in the through-hole 13 may be symmetrical or asymmetrical.

As shown in fig. 2, 3 and 5, the first insulating

layers

2, 3 and the second insulating

layers

8, 9 are attached to the substrate 1 by a high-temperature thermal oxidation process, and the first insulating

layers

2, 3 and the second insulating

layers

8, 9 formed by the high-temperature thermal oxidation process can be closely attached to the surface of the substrate 1, are not easily detached, and can completely cover the inside of the through hole 13. Preferably, the first insulating

layers

2 and 3 are formed on the upper and lower end surfaces of the substrate 1 by a dry-wet dry oxidation process, and the second insulating

layers

8 and 9 are formed on the inner walls of the through holes 13 by a dry-wet dry oxidation process. The first insulating

layers

2, 3 and the second insulating

layers

8, 9 may be made of SiO₂、SiN、SiON or other low K material. The coverage of the first 2, 3 and second 8, 9 insulating layers insulates the substrate 1 while providing some protection to the substrate 1.

Since the through hole 13 of the substrate 1 has the first concave portion 14 therein, when the second insulating

layers

8 and 9 are formed on the inner wall of the through hole 13, they will adhere to the inner wall of the first concave portion 14, and form the second concave portion 15 adapted to the shape of the first concave portion 14.

As shown in fig. 2, 3 and 5, the seed layers 4, 6 and 7 may be attached to the surfaces of the second insulating

layers

8 and 9 by a magnetron sputtering process, and the seed layers 4, 6 and 7 may be made of one or more materials including TaN, Ta, TiN and Ti. Since the second insulating

layers

8 and 9 have the second recesses 15, the seed layers 4, 6 and 7 formed on the second insulating

layers

8 and 9 will adhere to the inner walls of the second recesses 15 to form third recesses 16 adapted to the shape of the second recesses 15.

As shown in fig. 2 to 5, the metal layer 5 is completely filled in the annular space defined by the second insulating

layers

8 and 9 and the seed layers 4, 6 and 7, the metal layer 5 may be formed by a double-sided blind via electroplating process, and the metal layer 5 is deposited and filled inside the seed layers 4, 6 and 7. The metal layer 5 can be made of Cu, Al or W material. Through the double-sided blind hole electroplating process, metal filling of deep holes can be realized, the thickness of the metal capable of being filled is increased, and the thickness of the silicon wafer substrate 1 after the silicon through hole structure is completed is also increased, so that the reliability requirement of MEMS packaging on the silicon wafer substrate 1 can be met;

as shown in fig. 2, 3 and 5, the position-limiting

rings

10, 11 and 12 are integrally formed on the surface of the metal layer 5, and since the seed layers 4, 6 and 7 have the third concave portions 16, the metal layer 5 will completely fill the third concave portions 16 during the formation process of the metal layer 5 inside the seed layers 4, 6 and 7, so that the surface of the metal layer 5 forms the annular position-limiting protrusions adapted to the shape of the third concave portions 16. The number of the limiting

rings

10, 11, 12 adapted to the third recessed portion 16 may be one or more, and the limiting

rings

10, 11, 12 may be distributed symmetrically or asymmetrically. The limiting rings 10, 11 and 12 can improve the fixation of the metal layer 5 in the through hole 13, and achieve a better effect.

When the chip is in a high-temperature environment, due to the fact that the performance of the materials of all the parts is different, thermal mismatch is caused, the metal layer 5 in the through silicon via interconnection structure expands, due to the fact that the first concave portion 14, the second concave portion 15, the third concave portion 16 and the limiting

rings

10, 11 and 12 are arranged inside the through silicon via interconnection structure, the metal layer 5 is fixed in the through silicon via interconnection structure and cannot be separated, the upper limit of the working time and the working temperature of the chip in the high-temperature environment is improved, electrical interconnection of all the parts of the chip is guaranteed, and therefore the chip can stably work in the high-temperature environment for a long time.

A method of forming a through silicon via interconnect structure with an internal retaining ring, the method comprising:

s1, providing a semiconductor substrate, etching the surface of the substrate by using a deep silicon etching process to manufacture a blind hole, and forming a first concave part by adopting a step-by-step deep silicon etching process in the etching process;

s2, manufacturing a first insulating layer and a second insulating layer in the surface of the substrate and the blind holes respectively by using a dry-wet dry oxidation process;

s3, depositing a seed layer on the surface of the second insulating layer in the blind hole by using a magnetron sputtering process;

s4, filling the space inside the seed layer in the blind hole by using a double-sided blind hole electroplating process to form a metal layer;

and S5, removing the metal layers on the two end faces of the substrate by using a chemical mechanical polishing process to make the end faces flat.

The deep silicon etching process in the step S1 specifically comprises the following steps: the substrate on which the photolithography process is performed is subjected to a conventional deep silicon etch using a Bosch process.

The step-by-step deep silicon etching process in the step S1 specifically comprises the following steps: and carrying out deep silicon etching on the substrate which is subjected to the photoetching process by using a Bosch process, setting etching time according to the etching target depth and the etching rate of etching equipment, enabling the etching depth to reach a set value by carrying out multiple times of segmented etching, completely discharging gas remained in an etching chamber after the deep silicon etching is finished each time, carrying out next etching after short waiting, and repeating the steps until the target depth is reached.

The step-by-step deep silicon etching process can be divided into two steps, three steps or multiple steps of deep silicon etching to etch the substrate 1.

The step S4 double-sided blind hole electroplating process comprises the following steps:

s4.1, filling the blind hole with a metal material from one end face of the substrate by using an electroplating process;

s4.2, leaking the blind hole on the other end face of the substrate by using a thinning and polishing process;

and S4.3, filling the blind hole with a metal material from the other end face of the substrate by using an electroplating process, so that the metal columns filled on the two end faces form a whole.

The metal material includes: cu, Al or W material.

When the through-silicon-via interconnection structure is filled by using a double-sided blind hole electroplating method, the bottom of the through hole 13 is in a closed state during two times of electroplating, and the whole structure is in an open shape at one end.

The utility model discloses the principle is:

by utilizing the characteristic that the etching window can be enlarged by each etching of the Bosch process, the target depth achieved by one-time deep silicon etching is replaced by the target depth achieved by multiple times of deep silicon etching, an inward-concave annular structure can be formed between two adjacent times of deep silicon etching, and a metal layer formed after metal filling is completed can be embedded into the through hole. The silicon through hole structure forms an internal limiting ring structure through a step-by-step deep silicon etching method, so that the fixing capacity of filling metal is improved, the damage of thermal stress to the structure is greatly reduced, the working time of the silicon through hole structure in a high-temperature environment is prolonged, the silicon through hole structure can be applied to extremely severe high-temperature working environment, and the high-temperature reliability of a chip is improved, so that the service life of the chip is prolonged, and the silicon through hole structure is an ideal high-temperature resistant silicon through hole structure.

The utility model has the advantages that:

the utility model discloses a dark silicon etching forms unique spacing ring structure in the through-hole many times for this through-hole interconnect structure has higher adhesive force to the metal column, greatly reduce the influence of thermal stress, can work in 300 ℃ of high temperature environment for a long time steadily, be applicable to the electricity interconnection of various work in high temperature environment's chip, utilize two-sided blind hole to electroplate the safe filling that realizes the deep hole and make the through-hole interconnect structure of preparation reach the degree of depth more than 200 mu m, can be applied to MEMS encapsulation widely, the three-dimensional encapsulation of integrated circuit device etc.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims

1. A through-silicon via interconnect structure with an internal limiting ring, capable of long-term stable operation in a high temperature environment of 300 ℃, the through-silicon via comprising:

the device comprises a substrate (1), wherein at least one through hole (13) is formed in the substrate (1);

first insulating layers (2, 3), the first insulating layers (2, 3) being provided on upper and lower end faces of the substrate (1);

a second insulating layer (8, 9), the second insulating layer (8, 9) being disposed on an inner wall of the through-hole (13);

a seed layer (4, 6, 7), the seed layer (4, 6, 7) being disposed on a surface of the second insulating layer (8, 9) within the via hole (13);

the metal layer (5) is filled in the seed layers (4, 6, 7);

and a limiting part arranged on the through hole (13), the second insulating layers (8, 9), the seed layers (4, 6, 7) and the metal layer (5);

the spacing portion includes: the metal layer structure comprises a first sunken part (14) arranged on the inner wall of the through hole (13), at least one annular first sunken part (14) arranged on the inner wall of the through hole (13), a second sunken part (15) arranged on the second insulating layer (8, 9), a third sunken part (16) arranged on the seed layer (4, 6, 7) and limiting rings (10, 11, 12) arranged on the metal layer (5).

2. The TSV interconnect structure with an internal retaining ring according to claim 1, wherein the second recess (15) is located and form-fitted to the first recess (14) of the via (13), the third recess (16) is located and form-fitted to the second recess (15) of the second insulating layer (8, 9), and the retaining ring (10, 11, 12) is located and form-fitted to the third recess (16) of the seed layer (4, 6, 7).

3. The through-silicon-via interconnect structure with internal retaining ring according to claim 1, wherein the through-holes (13) are distributed in an array, and the array distribution of the through-holes (13) comprises: circular, annular, fan-shaped, rectangular, parallelogram or trapezoidal arrangement.

4. The TSV interconnect structure having an internal limiting ring according to claim 1, wherein the first recesses (14) are uniformly arranged at upper, middle and/or lower portions of the inner wall of the through hole (13).

5. The TSV interconnect structure with an internal retaining ring according to claim 1, wherein the first recesses (14) are non-uniformly arranged on the inner wall of the through hole (13), and the first recesses (14) are symmetrical or asymmetrical.

6. The TSV interconnect structure with an internal retaining ring according to claim 1, wherein the retaining rings (10, 11, 12) are integrally formed on the surface of the metal layer (5), the number of the retaining rings (10, 11, 12) is at least one, and the retaining rings (10, 11, 12) are symmetrical or asymmetrical.