CN117637716A - Deep trench capacitor structure and manufacturing method thereof - Google Patents
Deep trench capacitor structure and manufacturing method thereof Download PDFInfo
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- CN117637716A CN117637716A CN202311757803.7A CN202311757803A CN117637716A CN 117637716 A CN117637716 A CN 117637716A CN 202311757803 A CN202311757803 A CN 202311757803A CN 117637716 A CN117637716 A CN 117637716A
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Abstract
The invention relates to a deep trench capacitor structure and a method of fabricating the same. The deep trench capacitor structure includes a silicon interposer configured to internally dispose a plurality of metal traces; a deep trench capacitor configured to be mounted to a first surface of the silicon interposer; the deep trench capacitor comprises a wafer, a plurality of contact through holes arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer and a plastic layer which are arranged on the first surface of the wafer; the deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact via. The electrode and the dielectric layer are deposited on the deep trench array formed by etching, and the deep trench capacitor is manufactured in a plastic package mode and is integrated on the silicon intermediate layer, so that the silicon via has better compatibility, the manufacturing process is simpler, and the compatibility with the existing process is higher.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a deep trench capacitor structure and a manufacturing method thereof.
Background
With the continuous improvement of chip integration, the adoption of deep trench capacitors (deep trench capacitor, DTCs) instead of conventional chip capacitors has become a trend. Deep trench capacitors can be formedA very small but very large capacitor is widely used in the integrated circuit field such as memories, power supply devices, etc. The process of fabricating deep trench capacitors on a semiconductor is: etching out the trench array region and then thermally growing SiO 2 The layers are used as protective layers, then electrode layers and dielectric layers are alternately deposited through low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or atomic layer deposition (atomiclayer deposition, ALD) processes, then photoetching layers are coated to form through hole cavities, and finally the interconnection dielectric layers and the metal pad structures are formed. Since the through silicon vias (Through Silicon Vias, TSVs) and the deep trench capacitors can exist on the same silicon wafer at the same time, there are two methods that can be used to form the deep trench capacitors in the silicon interposer. One is a DTC-first process, the DTC is not affected by the previous process, but since the deep trench is formed before the TSV process, this approach needs to ensure that the TSV thermal budget in the TSV process does not affect the DTC. Another approach is TSV-first, making TSVs with standard TSV flow, and then forming DTCs.
The greater the capacitance density of the deep trench capacitor, the better the power integrity improvement effect, and some process problems may occur when forming the deep trench capacitor in the semiconductor device, such as poor film uniformity caused by large sidewall roughness, such as Cu bump easily generated when DTC and TSV are fabricated on the same silicon wafer.
Disclosure of Invention
In view of some or all of the problems in the prior art, the present invention provides a deep trench capacitor structure comprising:
a silicon interposer configured to internally dispose a plurality of metal traces;
a deep trench capacitor configured to be mounted to a first surface of the silicon interposer;
the deep trench capacitor comprises a wafer, a deep trench formed on the first surface of the wafer, a plurality of contact through holes arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer and a plastic sealing layer arranged on the first surface of the wafer;
the deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact via.
Further, the silicon interposer has a plurality of through silicon vias therein.
Further, the plastic sealing layer coats the first dielectric layer, the upper electrode, the lower electrode and the second dielectric layer.
Further, the second dielectric layer is preferably one of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide or a combination thereof.
The invention also provides a manufacturing method of the deep trench capacitor structure, which comprises the following steps:
bonding the second surface of the wafer to the first surface of the first carrier by a first bonding material;
etching the first surface of the wafer to form a deep trench array region;
thermally growing a first dielectric layer serving as a protective layer in the deep trench array region;
sequentially depositing a lower electrode layer, a second dielectric layer and an upper electrode layer on the first surface of the first dielectric layer;
etching the first dielectric layer, the lower electrode layer, the second dielectric layer and the upper electrode layer to form a plurality of first deep trench capacitor arrays;
the areas where the plurality of first deep trench capacitor arrays are located are subjected to plastic packaging to form a plastic packaged deep trench capacitor array;
bonding is removed, and the first carrier sheet and the first bonding material are peeled off;
turning over the plastic-sealed deep trench capacitor array, and bonding the first surface of the plastic-sealed layer with the first surface of the second slide glass through the second bonding material;
etching the second surface of the wafer to form a plurality of through hole cavities;
coating photoresist on the second surface of the wafer, exposing the photoresist to expose a plurality of first through hole cavities, and etching the upper electrode layer and the second dielectric layer in the first through hole cavities to form a plurality of first contact through holes;
removing the photoresist to expose a plurality of second through hole cavities, filling metal in the first contact through holes and the second through hole cavities, and cutting the wafer and the plastic sealing layer;
and de-bonding, and stripping the second carrier and the second bonding material to form a plurality of independent deep trench capacitors.
The deep trench capacitor is attached to a first surface of a silicon interposer that includes a through silicon via.
Further, the etching is preferably a Bosch etching process.
Further, the deep trench array cross section is:
one of a circle, square, tripod, hexagon, octagon, cross, or a combination thereof.
Further, the lower electrode layer, the second dielectric layer and the upper electrode layer are deposited by low-pressure chemical vapor deposition or atomic layer deposition.
Further, the plastic package is preferably injection molding, and the material of the plastic package is preferably epoxy resin.
Further, mounting the array of deep trench capacitors to the first surface of the silicon interposer containing through silicon vias further comprises:
the deep trench capacitor is electrically connected with a plurality of metal wires in the silicon interposer through the contact via.
Compared with the prior art, the invention has the following advantages:
1. the deep trench capacitor provided by the invention has the advantages of simple manufacturing process, low cost and high compatibility with the existing process.
2. The invention deposits the metal dielectric layer on the deep groove array formed by etching to manufacture the deep groove capacitor, the transmission rate of gaseous reagent and product is better during the lamination deposition, and better film uniformity can be realized.
3. The invention avoids slotting on the silicon intermediate layer and has better compatibility to the silicon through hole.
4. The deep trench capacitor is manufactured in a plastic package mode and is integrated on the silicon medium layer, so that the reliability is higher than that of the traditional deep trench capacitor.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
Figure 1 is a schematic structural view of a deep trench capacitor structure in accordance with one embodiment of the present invention;
figure 2 is a flow chart of a method of fabricating a deep trench capacitor structure in accordance with one embodiment of the present invention; and
figures 3a-3m are schematic cross-sectional views of a process for forming a deep trench capacitor structure in accordance with one embodiment of the present invention.
Detailed Description
In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.
Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.
In this specification, unless specifically indicated otherwise, "disposed on …", "disposed over …" and "disposed over …" do not preclude the presence of an intermediate therebetween. Furthermore, "disposed on or above" … merely indicates the relative positional relationship between the two components, but may also be converted to "disposed under or below" …, and vice versa, under certain circumstances, such as after reversing the product direction.
In this specification, unless specifically indicated otherwise, "first surface" and "second surface" are used only to describe surfaces that distinguish the same component. Furthermore, the terms "first," "second," and "third" are used for distinguishing between descriptions and not between dimensions.
In this specification, the adjectives "a" and "an" do not exclude a scenario of multiple elements, unless specifically indicated.
It should be noted that the embodiments of the present invention describe the steps of the method in a specific order, however, this is merely for the purpose of illustrating the specific embodiments, and not for limiting the order of the steps. In contrast, in different embodiments of the present invention, the sequence of each step may be adjusted according to the adjustment of the actual requirement.
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Figure 1 is a schematic structural diagram of a deep trench capacitor structure in accordance with one embodiment of the present invention. As shown in fig. 1, the deep trench capacitor structure includes a wafer 12, a first dielectric layer 13, an electrode and dielectric layer 14, a molding layer 15, a silicon interposer 19, and metal traces 20.
The silicon interposer 19 has a plurality of metal traces 20 disposed therein. And, the silicon interposer has a plurality of through silicon vias (Through Silicon Vias, TSVs) therein.
The wafer 12, the first dielectric layer 13, the electrode and dielectric layer 14, and the plastic layer 15 constitute a deep trench capacitor. As shown in fig. 1, deep trenches are formed in a first surface of the wafer. As shown in fig. 1, the deep trench capacitor is configured to be mounted to a first surface of the silicon interposer, i.e., an upper surface of the silicon interposer 19 shown in fig. 1.
The wafer is internally provided with a plurality of contact through holes, and the deep trench capacitor is electrically connected with the plurality of metal wires in the silicon interposer through the contact through holes. In one embodiment of the present invention, the material of the wafer is preferably one of silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or a combination thereof.
As shown in fig. 1, a first dielectric layer 13, an electrode and dielectric layer 14, and a plastic sealing layer 15 are disposed on a first surface of the wafer, i.e., the upper surface of the wafer 12 shown in fig. 1. In one embodiment of the present invention, the first dielectric layer is preferably one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
The electrode and dielectric layer 14 includes an upper electrode, a lower electrode, and a second dielectric layer. In one embodiment of the present invention, the upper and lower electrodes are preferably one of copper, tungsten, aluminum, copper alloy, titanium, or a combination thereof. In one embodiment of the present invention, the material of the second dielectric layer is preferably a material with a high dielectric constant, such as one of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, or a combination thereof.
As shown in fig. 1, the plastic sealing layer encapsulates the first dielectric layer, the upper electrode, the lower electrode and the second dielectric layer. In one embodiment of the present invention, the plastic package is preferably injection Molding, and the material of the plastic package is preferably epoxy resin.
Fig. 2 is a flow chart of a method of fabricating a deep trench capacitor structure in accordance with one embodiment of the present invention. Figures 3a-3m are schematic cross-sectional views of a process for forming a deep trench capacitor structure in accordance with one embodiment of the present invention. The method of fabricating the deep trench capacitor structure of the present invention is described below in conjunction with fig. 2 and 3.
First, the second surface of the wafer is bonded to the first surface of the first carrier by the first bonding material. As shown in fig. 3a, a wafer 12 is bonded to a first surface of a first carrier 10 by a first bonding material 11. In one embodiment of the present invention, the material of the wafer is preferably one of silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or a combination thereof. In one embodiment of the present invention, the first bonding material is a bonding glue, which may be TMAT, BSI, 3M (excluding separation), and DuPont's bonding agent. In one embodiment of the invention, the first slide is preferably glass or silicon wafer.
Next, the first surface of the wafer is etched to form a deep trench array region. As shown in fig. 3b, the wafer is etched to form an array of deep trenches, i.e., a wafer cylinder array. In one embodiment of the invention, the etch is preferably a Bosch etch process. In one embodiment of the present invention, the deep trench array cross section may be one of circular, square, tripod-shaped, hexagonal, octagonal, cross-shaped, or a combination thereof.
Next, thermally growing a first dielectric layer as a protective layer in the deep trench array region. As shown in fig. 3c, a first dielectric layer 14 is thermally grown over the deep trench array. In one embodiment of the present invention, first dielectric layer 14 is formed by low pressure chemical vapor deposition or atomic layer deposition. In one embodiment of the present invention, the first dielectric layer is preferably one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
And then, sequentially depositing a lower electrode layer, a second dielectric layer and an upper electrode layer on the first surface of the first dielectric layer. As shown in fig. 3d, the electrode and dielectric layer 14 includes an upper electrode, a lower electrode, and a second dielectric layer. In one embodiment of the present invention, the upper and lower electrodes are preferably one of copper, tungsten, aluminum, copper alloy, titanium, or a combination thereof. In one embodiment of the present invention, the second dielectric layer is preferably one of alumina, zirconia, or a combination thereof. In one embodiment of the invention, the lower electrode layer, the second dielectric layer, and the upper electrode layer are deposited by low pressure chemical vapor deposition or atomic layer deposition.
And etching the first dielectric layer, the lower electrode layer, the second dielectric layer and the upper electrode layer to form a plurality of first deep trench capacitor arrays. As shown in fig. 3e, the first dielectric layer, the lower electrode layer, the second dielectric layer, and the upper electrode layer are separated by etching. In one embodiment of the invention, the etch is preferably a Bosch etch process.
And then, the areas where the plurality of first deep trench capacitor arrays are located are subjected to plastic package to form a plastic packaged deep trench capacitor array. As shown in fig. 3f, the plastic layer 15 encapsulates the first dielectric layer, the upper electrode, the lower electrode and the second dielectric layer. In one embodiment of the present invention, the plastic package is preferably injection Molding, and the material of the plastic package is preferably epoxy resin.
Next, the bonding is released and the first carrier sheet and the first bonding material are peeled off. As shown in fig. 3g, the first carrier sheet 10 and the first bonding material 11 are removed. In one embodiment of the invention, the de-bonding is by mechanical separation, thermal slip, or laser separation.
And then, turning over the plastic-sealed deep groove capacitor array, and bonding the first surface of the plastic-sealed layer with the first surface of the second slide glass through the second bonding material. As shown in fig. 3h, the array of deep trench capacitors is bonded to the first surface of the second carrier 17 by the second bonding material 16. In one embodiment of the present invention, the second bonding material is a bonding paste, which may be TMAT, BSI, 3M (excluding separation), and DuPont's bonding agent. In one embodiment of the invention, the second slide is preferably glass or silicon wafer.
Next, a second surface of the wafer is etched to form a plurality of via cavities. As shown in fig. 3i, the etch forms a via cavity A, B, C, D. In one embodiment of the invention, the etch is preferably a Bosch etch process.
And coating photoresist on the second surface of the wafer, exposing the photoresist to expose a plurality of first through hole cavities, and etching the upper electrode layer and the second dielectric layer in the first through hole cavities to form a plurality of first contact through holes. As shown in fig. 3j, A, C is a first via, and after etching the upper electrode layer and the second dielectric layer in the first via cavity A, C, the surface of the via A, C is a lower electrode film. In one embodiment of the invention, the etch is preferably a Bosch etch process.
And removing the photoresist to expose a plurality of second through hole cavities, filling metal in the first contact through holes and the second through hole cavities, and cutting the wafer and the plastic sealing layer. As shown in fig. 3k, B, D is a second through hole, and the surface of the through hole B, D is an upper electrode film layer. In one embodiment of the present invention, the filler metal is preferably one of copper, tungsten, aluminum, copper alloy, titanium, or a combination thereof.
Next, the bonding is broken and the second carrier and the second bonding material are stripped to form a plurality of individual deep trench capacitors. As shown in fig. 3l, the second carrier sheet 17 and the second bonding material 16 are removed. In one embodiment of the invention, the de-bonding is by mechanical separation, thermal slip, or laser separation.
Finally, the deep trench capacitor is attached to the first surface of the silicon interposer containing the through silicon via. As shown in fig. 3m, the deep trench capacitor is arranged in the manner of SMD (Surface Mounted Devices surface mounted device) on the silicon interposer 19 containing the through silicon via. The deep trench capacitor is electrically connected to a plurality of metal traces 20 in the silicon interposer through the contact via. In one embodiment of the invention, the silicon interposer has a plurality of through silicon vias therein.
The invention provides a deep trench capacitor structure and a manufacturing method thereof, which are characterized in that an electrode and a dielectric layer are deposited on a deep trench array formed by etching, a deep trench capacitor is manufactured in a plastic package mode, and is integrated on a silicon intermediate layer, so that the deep trench capacitor structure has better compatibility with a silicon through hole, and the manufacturing process is simpler and has higher compatibility with the existing process.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Claims (10)
1. A deep trench capacitor structure, comprising:
a silicon interposer configured to internally dispose a plurality of metal traces;
a deep trench capacitor configured to be mounted to a first surface of the silicon interposer;
the deep trench capacitor comprises a wafer, a deep trench formed on the first surface of the wafer, a plurality of contact through holes arranged in the wafer, and a first dielectric layer, an upper electrode, a lower electrode, a second dielectric layer and a plastic sealing layer arranged on the first surface of the wafer;
the deep trench capacitor is electrically connected to the plurality of metal traces in the silicon interposer through the contact via.
2. The deep trench capacitor structure of claim 1, wherein said silicon interposer has a plurality of through silicon vias therein.
3. The deep trench capacitor structure of claim 1, wherein the plastic layer encapsulates the first dielectric layer, the upper electrode, the lower electrode, and the second dielectric layer.
4. The deep trench capacitor structure of claim 1, wherein the second dielectric layer is preferably one of aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, or a combination thereof.
5. A method of fabricating a deep trench capacitor structure, comprising the steps of:
bonding the second surface of the wafer to the first surface of the first carrier by a first bonding material;
etching the first surface of the wafer to form a deep trench array region;
thermally growing a first dielectric layer serving as a protective layer in the deep trench array region;
sequentially depositing a lower electrode layer, a second dielectric layer and an upper electrode layer on the first surface of the first dielectric layer;
etching the first dielectric layer, the lower electrode layer, the second dielectric layer and the upper electrode layer to form a plurality of first deep trench capacitor arrays;
the areas where the plurality of first deep trench capacitor arrays are located are subjected to plastic packaging to form a plastic packaged deep trench capacitor array;
bonding is removed, and the first carrier sheet and the first bonding material are peeled off;
turning over the plastic-sealed deep trench capacitor array, and bonding the first surface of the plastic-sealed layer with the first surface of the second slide glass through the second bonding material;
etching the second surface of the wafer to form a plurality of through hole cavities;
coating photoresist on the second surface of the wafer, exposing the photoresist to expose a plurality of first through hole cavities, and etching the upper electrode layer and the second dielectric layer in the first through hole cavities to form a plurality of first contact through holes;
removing the photoresist to expose a plurality of second through hole cavities, filling metal in the first contact through holes and the second through hole cavities, and cutting the wafer and the plastic sealing layer;
and de-bonding, and stripping the second carrier and the second bonding material to form a plurality of independent deep trench capacitors.
The deep trench capacitor is attached to a first surface of a silicon interposer that includes a through silicon via.
6. The method of manufacturing according to claim 5, characterized in that the etching is preferably a Bosch etching process.
7. The method of manufacturing of claim 5, wherein the deep trench array cross section is:
one of a circle, square, tripod, hexagon, octagon, cross, or a combination thereof.
8. The method of claim 5, wherein the lower electrode layer, the second dielectric layer, and the upper electrode layer are deposited by low pressure chemical vapor deposition or atomic layer deposition.
9. The method of manufacturing according to claim 5, wherein the plastic package is preferably injection molded, and the material of the plastic package is preferably epoxy resin.
10. The method of manufacturing of claim 5, wherein attaching the array of deep trench capacitors to the first surface of the silicon interposer comprising through silicon vias further comprises:
the deep trench capacitor is electrically connected with a plurality of metal wires in the silicon interposer through the contact via.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311757803.7A CN117637716A (en) | 2023-12-19 | 2023-12-19 | Deep trench capacitor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311757803.7A CN117637716A (en) | 2023-12-19 | 2023-12-19 | Deep trench capacitor structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117637716A true CN117637716A (en) | 2024-03-01 |
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