CN111293079A - Manufacturing method of super-thick adapter plate - Google Patents
Manufacturing method of super-thick adapter plate Download PDFInfo
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- CN111293079A CN111293079A CN202010186946.7A CN202010186946A CN111293079A CN 111293079 A CN111293079 A CN 111293079A CN 202010186946 A CN202010186946 A CN 202010186946A CN 111293079 A CN111293079 A CN 111293079A
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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Abstract
The invention discloses a method for manufacturing an ultra-thick adapter plate, which comprises the following steps: the adapter plate adopts a silicon wafer with an SOI layer, a silicon through hole is formed at the bottom of the silicon wafer with the SOI layer, a passivation layer and a seed layer are deposited, and then metal is electroplated; making a through silicon via on the top of the silicon wafer with the bottom electroplated with metal, wherein the through silicon via is a top through silicon via; depositing a passivation layer on the top silicon through hole of the silicon wafer with the silicon through hole on the top, etching to open the passivation layer, then making an electroplating seed layer, and electroplating a filling metal on the surface of the top silicon through hole; and depositing a seed layer, electroplating filling metal, and removing the metal layers on the two sides of the adapter plate through polishing to obtain the ultra-thick adapter plate. According to the invention, different TSV holes are formed in the surface of the silicon wafer, so that the upper surface and the lower surface of the silicon wafer can be electrically interconnected, the depth of the formed TSV holes is larger, the silicon wafer can be conveniently manufactured without a temporary bonding process, the manufacturing cost of the adapter plate is greatly reduced, and the popularization of the adapter plate is powerfully promoted.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an ultra-thick adapter plate.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
In the background of the era of post moore's law, it has become more difficult to increase the degree of integration by means of conventional shrinking transistor dimensions. The existing electronic system is developing towards miniaturization, diversification and intellectualization, and finally a high-integration-level low-cost integrated electronic system with integration of multiple functions such as perception, communication, processing, transmission and the like is formed. The core technology of the multifunctional integrated electronic system is integration, and the multifunctional integrated electronic system is developing from plane integration to three-dimensional integration and from chip level to system level integration with higher integration level and complexity. The three-dimensional integrated system-in-package can solve the problem of integrating more transistors in the same area, and is a development direction in the future.
The structure of making the support plate or the cover plate to make the system-in-package through the adapter plate can change the plane layout of a chip into a stacked layout on the framework, and can integrate systems such as passive devices or discrete elements and the like to construct, so that the precision and the density are increased, the performance is greatly improved, the development trend of the future radio frequency integrated circuit technology is represented, and great advantageous characteristics exist in multiple aspects:
a) the three-dimensional heterogeneous integrated system-in-package adopts a chip shell to complete all interconnection of a system, so that the total welding spots are greatly reduced, the connecting line distance of elements is shortened, and the electrical property is improved.
b) Two or more chips are stacked in the same adapter plate chip in the three-dimensional heterogeneous integrated system-in-package (SIP) mode, the space in the Z direction is also utilized, package pins do not need to be added, the area ratio of the two chips stacked in the same shell to the chips is larger than 100%, and the stacking of the three chips can be increased to 250%;
c) small physical size and light weight. For example, the most advanced technology can realize the ultrathin thickness of 4-layer stacked chips with the thickness of only 1mm, and the weight of three-layer stacked chips is reduced by 35%;
different technologies (such as MEMS technology, SiGe HBT, SiGe BiCMOS, Si CMOS, III-V (InP, GaN, GaAs) MMIC technology and the like) and chips (such as radio frequency, biological, micro-electro-mechanical and photoelectric chips and the like) made of different materials (such as Si, GaAs and InP) and having different functions are assembled to form a system, so that the system has good compatibility and can be combined with integrated passive elements. There is data showing that passive components currently used in radio and portable electronic machines can be embedded at least 30-50%.
However, in practical application, the application of the adapter plate is not widely popularized, mainly because the process for manufacturing the adapter plate is too complex, and the thickness of the adapter plate is usually not more than 200um, a temporary bonding process is required in the manufacturing process, the input cost and the manufacturing cost are high, and the development of the adapter plate in the civil field is limited.
Disclosure of Invention
The invention provides a manufacturing method of an ultra-thick adapter plate, which is characterized in that different TSV holes are manufactured on the surface of a silicon wafer, so that the upper surface and the lower surface of the silicon wafer can be electrically interconnected, the depth of the manufactured TSV holes is larger, the silicon wafer can be conveniently manufactured without a temporary bonding process, and the manufacturing cost of the adapter plate is greatly reduced.
A manufacturing method of an ultra-thick adapter plate comprises the following steps:
a: the adapter plate adopts a silicon wafer with an SOI layer, a Through Silicon Via (TSV) is formed at the bottom of the silicon wafer with the SOI layer, the TSV penetrates through the SOI layer and stops on a silicon material, a passivation layer and a seed layer are deposited on the surface of the TSV, and then metal is electroplated to obtain a silicon wafer with electroplated metal at the bottom;
b: making a through silicon via at the top of the silicon wafer with the bottom electroplated with metal, wherein the through silicon via is a top through silicon via, and the bottom of the through silicon via is communicated with the metal layer in the bottom through silicon via to obtain the silicon wafer with the top provided with the through silicon via;
c: depositing a passivation layer on a top silicon through hole of a silicon wafer with the top silicon through hole, etching to open the passivation layer, then making an electroplating seed layer, electroplating filling metal on the surface of the top silicon through hole, and obtaining the silicon wafer with the top silicon through hole partially filled with metal on the filling part of the top silicon through hole;
d: and depositing a seed layer on the residual silicon through holes on the top of the silicon wafer with the top silicon through holes partially filled with metal, then electroplating the filled metal, and then removing the metal layers on the two sides of the adapter plate through polishing to obtain the ultra-thick adapter plate.
In the step A, the Through Silicon Via (TSV) is manufactured through photoetching and etching processes. The diameter of Through Silicon Via (TSV) is 1um to 1000 um.
The passivation layer is silicon oxide or silicon nitride or is formed in a thermal oxidation mode, and the thickness range of the passivation layer is 10nm to 100 um.
The seed layer is manufactured above the insulating layer through a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper at 200-500 ℃ to the electroplating metal to enable the copper metal to cover the surface of the TSV, and densifying at 200-500 ℃ to enable the copper to be more dense;
in the step B, the opening of the top silicon through hole can be circular, oval or square, the diameter or side length range of the opening is 10nm to 1000um, and the depth range of the opening is 10nm to 1000 um;
in the step C, electroplating copper by using the electroplating filling metal at 200-500 ℃ to enable the copper metal to cover the surface of the TSV, and densifying at 200-500 ℃ to enable the copper to be more compact;
in the step D, the seed layer adopts a PVD (Physical Vapor Deposition) process. The thickness range of the seed layer is 1nm to 100um, the seed layer can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
electroplating copper at 200-500 deg.C for the filler metal, and densifying at 200-500 deg.C to make the copper more dense;
removing copper on the surface of the silicon wafer by a copper CMP (Chemical Mechanical Polishing) process to obtain an ultra-thick adapter plate; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved.
Another method for manufacturing an ultra-thick adapter plate comprises the following steps:
a: the method comprises the following steps that a silicon wafer with double SOI layers is adopted for an adapter plate, a first SOI layer and a second SOI layer are sequentially arranged from the top to the bottom of the adapter plate, a primary Through Silicon Via (TSV) is formed in the top of the adapter plate, the primary Through Silicon Via (TSV) is etched to penetrate through the first SOI layer, the through silicon via is continuously etched at the position of the primary Through Silicon Via (TSV), the primary Through Silicon Via (TSV) is continuously etched, the primary Through Silicon Via (TSV) is etched and stopped on the second SOI layer to form a first through silicon via, the primary Through Silicon Via (TSV) is etched and enlarged and then stopped on the first SOI layer to form a second through silicon via, the diameter of the second through silicon via is larger than that of the first through silicon via, and after the first through silicon via and the second through silicon via are formed, a passivation layer is manufactured on the silicon wafer to obtain the silicon wafer with the first through silicon via and the;
b: continuously manufacturing a through silicon hole at the position, opposite to the first through silicon hole, of the bottom of the silicon wafer with the first through silicon hole and the second through silicon hole to form a third through silicon hole, etching the third through silicon hole to stop on the second SOI layer, then manufacturing a passivation layer on the surface of the third through silicon hole, depositing a seed layer, and then electroplating filling metal on the third through silicon hole to obtain the silicon wafer with the metal layer filled at the bottom;
c: opening the bottom of a first silicon through hole of the silicon wafer with the metal layer filled at the bottom to expose metal in a third silicon through hole, and then electroplating metal in the first silicon through hole to fill the first silicon through hole with the metal so as to obtain the silicon wafer with the first silicon through hole filled with the metal;
opening the bottom passivation layer of the TSV in the first step to expose the bottom of the TSV filled with the thinned surface, and using the TSV metal layer for electroplating to enable the metal to fill the bottom of the TSV in the first step;
as shown in fig. 19, the bottom passivation layer of the TSV in the first step is opened by a dry etching process to expose the bottom of the TSV filled in the thinned surface, and the TSV metal layer is used for electroplating to fill the bottom of the TSV in the first step with metal;
d: a seed layer is made on a silicon wafer with the first silicon through hole filled with metal, then the second silicon through hole is filled with metal through electroplating, and finally metal layers on two sides are polished to obtain the super-thick adapter plate;
in the step A, the diameter range of the first Through Silicon Via (TSV) is 10nm to 1000um, and the depth range of the first Through Silicon Via (TSV) is 10nm to 1000 um;
the primary Through Silicon Via (TSV) is manufactured on the surface of the silicon wafer through photoetching and etching processes;
the passivation layer is silicon oxide or silicon nitride formed by deposition or is formed by direct thermal oxidation, and the thickness of the passivation layer ranges from 10nm to 100 um.
In the step B, the opening of the third through silicon via can be circular, oval or square, the diameter range of the third through silicon via is 10nm to 1000um, and the depth range of the third through silicon via is 10nm to 1000 um;
the thickness range of the passivation layer is 10nm to 1000um, and the material of the passivation layer can be silicon oxide or silicon nitride.
The thickness of the seed layer ranges from 1nm to 100um, the seed layer can be a layer or a plurality of layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
And the third through silicon via is electroplated and filled with one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like.
Compared with the prior art, the invention has the following advantages:
according to the manufacturing method of the ultra-thick adapter plate, different TSV holes are manufactured in the surface of the wafer, so that the upper surface and the lower surface of the wafer can be electrically interconnected, the depth of the manufactured TSV holes is large, the wafer can be conveniently manufactured without a temporary bonding process, the manufacturing cost of the adapter plate is greatly reduced, the popularization of the adapter plate is powerfully promoted, good economic benefits are achieved, the market popularization and utilization are facilitated, and the wide application prospect is achieved.
Drawings
FIG. 1 is a schematic view showing the structure of a silicon wafer having an SOI layer in example 1;
FIG. 2 is a schematic structural diagram of etching a TSV on a silicon wafer having an SOI layer in embodiment 1;
FIG. 3 is a schematic diagram showing a structure of depositing a passivation layer on a silicon wafer according to example 1;
FIG. 4 is a schematic structural diagram illustrating a seed layer formed on a silicon wafer in embodiment 1;
FIG. 5 is a schematic view showing the structure of copper electroplating on a silicon wafer according to example 1;
FIG. 6 is a schematic structural diagram of fabricating a TSV on the other side of the silicon wafer in example 1;
FIG. 7 is a schematic view showing a structure of depositing a seed layer on a silicon wafer according to example 1;
FIG. 8 is a schematic diagram showing a structure of electroplating a filler metal on a silicon wafer according to example 1;
FIG. 9 is a schematic view showing a structure of a seed layer deposited by a PVD process on a silicon wafer according to example 1;
FIG. 10 is a schematic structural diagram of filling metal into a TSV on a silicon wafer by front-side electroplating in example 1;
FIG. 11 is a schematic structural diagram of an ultra-thick interposer obtained by removing copper from the surface of a silicon wafer in example 1;
FIG. 12 is a schematic structural view of an interposer silicon wafer of a double SOI silicon oxide layer in example 2;
FIG. 13 is a schematic structural diagram of TSV fabrication on the interposer silicon wafer surface of the double SOI silicon oxide layer in example 2;
fig. 14 is a schematic structural diagram of the continued fabrication of TSVs on the surface of the interposer silicon wafer with the double SOI silicon oxide layer in embodiment 2;
FIG. 15 is a schematic structural view of a passivation layer deposited over a silicon wafer in example 2;
fig. 16 is a schematic structural diagram of forming a TSV in the back surface of the thinned silicon wafer in embodiment 2;
FIG. 17 is a schematic structural diagram illustrating a passivation layer formed on the surface of a TSV in embodiment 2;
FIG. 18 is a schematic structural view of depositing a seed layer and electroplating filled TSVs in example 2;
FIG. 19 is a schematic structural diagram illustrating a TSV metal layer is used for electroplating and a TSV metal layer is used for electroplating in embodiment 2;
fig. 20 is a schematic structural diagram illustrating a seed layer formed on the TSV surface in the first step in embodiment 2;
FIG. 21 is a schematic structural view of an ultra-thick interposer obtained by polishing two metal layers in example 2;
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments described in the present invention, and that other drawings can be obtained from these drawings by a person skilled in the art without inventive effort.
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely for simplicity and clarity of describing the present invention, and are not intended to represent any correlation between the various embodiments and/or structures discussed.
Reference numerals in the various embodiments of the invention with respect to steps are merely for convenience of description and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention discloses a method for manufacturing an ultra-thick adapter plate, which comprises the following steps:
example 1
A manufacturing method of an ultra-thick adapter plate specifically comprises the following steps:
a: the adapter plate adopts a Silicon wafer with an SOI (Silicon-On-Insulator, Silicon On an insulating substrate) layer, TSV (through Silicon via) is formed On the surface of the Silicon wafer of the SOI adapter plate, the TSV stops below the SOI, a passivation layer and a seed layer are deposited On the surface of the TSV, and a layer of metal is electroplated On the surface of the TSV;
as shown in fig. 1 and fig. 2, an SOI adapter plate 101 is prepared, and a TSV103 is fabricated on the surface of a silicon wafer through photolithography and etching processes;
the TSV stops above the SOI102, where the TSV diameter is between 1um and 1000 um;
continuously etching the TSV103, and stopping etching on the silicon material below the SOI;
as shown in fig. 3, a passivation layer 104 of silicon oxide or silicon nitride is deposited on the silicon wafer, or directly thermally oxidized, and the thickness of the passivation layer 104 ranges from 10nm to 100 um;
as shown in fig. 4, a seed layer 105 is formed over the insulating layer by physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer 105 ranges from 1nm to 100um, and the seed layer may be one layer or multiple layers, and the metal material may be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;
as shown in fig. 5, copper is electroplated to make copper metal 105 cover the TSV surface, and densification is performed at 200 to 500 ℃ to make the copper denser;
b: thinning the other surface of the wafer, and continuously manufacturing TSV (through silicon via) on the surface to open the bottom of the metal layer in the TSV in the previous step;
as shown in fig. 6, the other side of the thinned wafer (i.e., the silicon wafer with the SOI layer) is thinned to a depth of 10um to 1000um, and then a TSV107 is formed on the thinned side by photolithography and etching, wherein an opening of the TSV can be circular, elliptical or square, the diameter or side length range of the TSV is 10nm to 1000um, and the depth range of the TSV is 10nm to 1000 um;
the bottom of the TSV is contacted with the bottom of the TSV in front, and metal at the bottom of the TSV is exposed;
c: depositing a passivation layer on the surface of the new TSV107, then etching and opening the passivation layer, using the electroplating metal layer on the other surface as an electroplating seed layer, and electroplating filling metal on the surface of the TSV;
as shown in fig. 7 and 8, depositing a passivation layer on the new TSV surface, opening the bottom passivation layer by dry etching, depositing a seed layer 108 on the front surface of the wafer, then electroplating a filler metal 109 on the TSV surface, electroplating copper to make the copper metal cover the TSV surface, and densifying at 200 to 500 ℃ to make the copper denser;
d: depositing a seed layer on the surface of the new TSV, then electroplating filling metal, and then removing metal layers on two sides of the adapter plate through polishing to obtain the ultra-thick adapter plate;
as shown in fig. 9, a seed layer 111 is deposited by PVD, the thickness of the seed layer 111 ranges from 1nm to 100um, and may be one layer or multiple layers, and the metal material may be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;
as shown in fig. 10, the TSV filler metal 112 is plated by front-side electroplating, and copper is plated to densify at 200 to 500 degrees to make the copper denser;
as shown in fig. 11, a copper CMP (Chemical Mechanical Polishing) process removes copper from the surface of the silicon wafer to obtain an ultra-thick interposer; the insulating layer on the surface of the silicon chip can be removed by a dry etching or wet etching process; the insulating layer on the surface of the silicon chip can also be reserved.
Example 2
A manufacturing method of an ultra-thick adapter plate specifically comprises the following steps:
a: making TSV on the surface of a double-layer SOI adapter plate silicon wafer, stopping the TSV below a first layer of SOI, continuously defining another TSV on the surface, stopping the TSV above a second layer of SOI, and depositing a passivation layer on the surface of the TSV;
as shown in fig. 12 and 13, an interposer silicon wafer with a double-layer SOI silicon oxide layer is prepared, and then TSVs are fabricated on the surface of the silicon wafer through photolithography and etching processes; the diameter range of the TSV is 10nm to 1000um, and the depth range of the TSV is 10nm to 1000 um;
here, TSV etching is stopped on the first layer of SOI, and then an SOI layer is continuously etched, so that TSV is stopped below the first layer of SOI;
as shown in fig. 14, the TSV is continuously fabricated on the surface of the silicon wafer through the photolithography and etching processes, and the TSV has a larger diameter than the TSV in fig. 13 and is coincident with the TSV for the first time, so that when a second TSV is etched, the first TSV is continuously etched, and finally the first TSV is etched and stopped on the second layer of SOI, and the second TSV is stopped on the first layer of SOI;
as shown in fig. 15, a passivation layer such as silicon oxide or silicon nitride is deposited on the silicon wafer, or is directly thermally oxidized, and the thickness of the passivation layer ranges from 10nm to 100 um;
b: thinning the back surface of the silicon chip, continuously manufacturing TSV at the position, overlapped with the opening surface of the TSV, of the other surface of the silicon chip, stopping etching the TSV on the SOI, manufacturing a passivation layer on the surface of the TSV, depositing a seed layer and then electroplating and filling the TSV;
as shown in fig. 16, the back surface of the silicon wafer is thinned, the thinning thickness is from 10um to 1000um, then the TSV is continuously made at the position where the thinned surface is overlapped with the open surface of the TSV in front through the processes of photoetching and etching, the opening of the groove can be circular, oval or square, the diameter range of the groove is from 10nm to 1000um, the depth range of the groove is from 10nm to 1000um, and the TSV is etched and stopped on the SOI;
as shown in fig. 17, a passivation layer is formed on the TSV surface, the thickness of the passivation layer ranges from 10nm to 1000um, and the passivation layer may be made of silicon oxide or silicon nitride;
as shown in fig. 18, a seed layer is deposited, the thickness of the seed layer ranges from 1nm to 100um, and the seed layer may be one layer or multiple layers, and the metal material may be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.; finally, TSV is filled through electroplating, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
c: opening the bottom passivation layer of the TSV in the first step to expose the bottom of the TSV filled with the thinned surface, and using the TSV metal layer for electroplating to enable the metal to fill the bottom of the TSV in the first step;
as shown in fig. 19, the bottom passivation layer of the TSV in the first step is opened by a dry etching process to expose the bottom of the TSV filled in the thinned surface, and the TSV metal layer is used for electroplating to fill the bottom of the TSV in the first step with metal;
d: a seed layer is made on the surface of the TSV in the first step, the TSV is filled with metal through electroplating, and finally the metal layers on the two sides are polished to obtain the ultra-thick adapter plate;
as shown in fig. 20, a seed layer is formed on the TSV surface in the first step;
as shown in fig. 21, electroplating to fill metal into the TSV, and finally polishing the metal layers on both sides to obtain an ultra-thick interposer;
it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A manufacturing method of an ultra-thick adapter plate is characterized by comprising the following steps:
a: the adapter plate adopts a silicon wafer with an SOI layer, a silicon through hole is formed in the bottom of the silicon wafer with the SOI layer, the silicon through hole penetrates through the SOI layer and stops on a silicon material, a passivation layer and a seed layer are deposited on the surface of the silicon through hole, and then metal is electroplated to obtain a silicon wafer with electroplated metal at the bottom;
b: making a through silicon via at the top of the silicon wafer with the bottom electroplated with metal, wherein the through silicon via is a top through silicon via, and the bottom of the through silicon via is communicated with the metal layer in the bottom through silicon via to obtain the silicon wafer with the top provided with the through silicon via;
c: depositing a passivation layer on a top silicon through hole of a silicon wafer with the top silicon through hole, etching to open the passivation layer, then making an electroplating seed layer, electroplating filling metal on the surface of the top silicon through hole, and obtaining the silicon wafer with the top silicon through hole partially filled with metal on the filling part of the top silicon through hole;
d: and depositing a seed layer on the residual silicon through holes on the top of the silicon wafer with the top silicon through holes partially filled with metal, then electroplating the filled metal, and then removing the metal layers on the two sides of the adapter plate through polishing to obtain the ultra-thick adapter plate.
2. The method for manufacturing an ultra-thick interposer according to claim 1, wherein in step a, the through-silicon via is manufactured by photolithography and etching processes, and the diameter of the through-silicon via is 1um to 1000 um.
3. The method of claim 1, wherein in step a, the passivation layer is silicon oxide or silicon nitride, or is formed by thermal oxidation, and the thickness of the passivation layer ranges from 10nm to 100 μm.
4. The method for manufacturing an ultra-thick interposer according to claim 1, wherein in the step a, the seed layer is manufactured above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer is in a range of 1nm to 100 μm, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel.
5. The method of claim 1, wherein the electroplating metal in step a is copper electroplating at a temperature of 200 to 500 ℃.
6. The method of claim 1, wherein in step B, the opening of the top through-silicon-via is circular, elliptical or square, with a diameter or side length ranging from 10nm to 1000um and a depth ranging from 10nm to 1000 um.
7. The method for manufacturing an ultra-thick interposer as claimed in claim 1, wherein in step C, the filler metal is electroplated with copper at 200 to 500 ℃;
in the step D, a physical vapor deposition process is adopted for the seed layer, the thickness of the seed layer ranges from 1nm to 100um, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel.
8. A manufacturing method of an ultra-thick adapter plate is characterized by comprising the following steps:
a: the method comprises the following steps that a silicon wafer with double SOI layers is adopted for an adapter plate, a first SOI layer and a second SOI layer are sequentially arranged from the top to the bottom of the adapter plate, a primary through silicon hole is formed in the top of the adapter plate, the primary through silicon hole is etched to penetrate through the first SOI layer, the through silicon hole is continuously etched at the position of the primary through silicon hole, the primary through silicon hole is continuously etched, the primary through silicon hole is etched and stopped on the second SOI layer to form a first through silicon hole, the primary through silicon hole is etched and enlarged and then stopped on the first SOI layer to form a second through silicon hole, the diameter of the second through silicon hole is larger than that of the first through silicon hole, after the first through silicon hole and the second through silicon hole are formed, a passivation layer is manufactured on the silicon wafer, and the silicon wafer with the first through silicon hole and the second;
b: continuously manufacturing a through silicon hole at the position, opposite to the first through silicon hole, of the bottom of the silicon wafer with the first through silicon hole and the second through silicon hole to form a third through silicon hole, etching the third through silicon hole to stop on the second SOI layer, then manufacturing a passivation layer on the surface of the third through silicon hole, then depositing a seed layer, and electroplating filling metal on the third through silicon hole to obtain the silicon wafer with the metal layer filled at the bottom;
c: opening the bottom of a first silicon through hole of the silicon wafer with the metal layer filled at the bottom to expose metal in a third silicon through hole, and then electroplating metal in the first silicon through hole to fill the first silicon through hole with the metal so as to obtain the silicon wafer with the first silicon through hole filled with the metal;
d: and (3) making a seed layer on the silicon wafer with the first through silicon via filled with metal, filling metal in the second through silicon via by electroplating, and finally polishing the metal layers on the two sides to obtain the ultra-thick adapter plate.
9. The method for manufacturing an ultra-thick interposer according to claim 8, wherein in step a, the diameter of the first through-silicon-via is in a range of 10nm to 1000um, and the depth thereof is in a range of 10nm to 1000 um;
the preliminary through silicon via is manufactured on the surface of the silicon wafer through photoetching and etching processes;
the passivation layer is silicon oxide or silicon nitride formed by deposition or is formed by direct thermal oxidation, and the thickness of the passivation layer ranges from 10nm to 100 um.
10. The method for manufacturing an ultra-thick interposer according to claim 8, wherein in step a, in step B, the opening of the third through-silicon-via is circular, elliptical or square, the diameter of the third through-silicon-via is 10nm to 1000um, and the depth of the third through-silicon-via is 10nm to 1000 um;
the thickness range of the passivation layer is 10nm to 1000um, and the passivation layer is made of silicon oxide or silicon nitride;
the thickness range of the seed layer is 1nm to 100um, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel;
and the third through silicon via is electroplated and filled with one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
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