CN111293079A - Manufacturing method of super-thick adapter plate - Google Patents

Abstract

The invention discloses a method for manufacturing an ultra-thick adapter plate, which comprises the following steps: the adapter plate adopts a silicon wafer with an SOI layer, a silicon through hole is formed at the bottom of the silicon wafer with the SOI layer, a passivation layer and a seed layer are deposited, and then metal is electroplated; making a through silicon via on the top of the silicon wafer with the bottom electroplated with metal, wherein the through silicon via is a top through silicon via; depositing a passivation layer on the top silicon through hole of the silicon wafer with the silicon through hole on the top, etching to open the passivation layer, then making an electroplating seed layer, and electroplating a filling metal on the surface of the top silicon through hole; and depositing a seed layer, electroplating filling metal, and removing the metal layers on the two sides of the adapter plate through polishing to obtain the ultra-thick adapter plate. According to the invention, different TSV holes are formed in the surface of the silicon wafer, so that the upper surface and the lower surface of the silicon wafer can be electrically interconnected, the depth of the formed TSV holes is larger, the silicon wafer can be conveniently manufactured without a temporary bonding process, the manufacturing cost of the adapter plate is greatly reduced, and the popularization of the adapter plate is powerfully promoted.

Description

A method of making an ultra-thick adapter plate

technical field

The invention relates to the technical field of semiconductors, in particular to a method for manufacturing an ultra-thick adapter plate.

Background technique

Microwave and millimeter-wave radio frequency integrated circuit technology is the foundation of modern defense weapons and equipment and the Internet industry. With the rapid rise of the "Internet +" economy such as smart communication, smart home, smart logistics, and smart transportation, microwaves that undertake data access and transmission functions There are also huge practical demands and potential markets for millimeter-wave radio frequency integrated circuits.

In the post-Moore's Law era, it has become more difficult to increase the level of integration through the traditional way of shrinking the size of transistors. The current electronic system is developing in the direction of miniaturization, diversification and intelligence, and finally forms a highly integrated and low-cost comprehensive electronic system with multi-functional integration of sensing, communication, processing, and transmission. The core technology of multi-functional integrated electronic system is integration, which is developing from plane integration to three-dimensional integration, and from chip level to system level integration with higher integration and complexity. Three-dimensional integrated system-in-package can solve the problem of integrating more transistors in the same area, which is the future development direction.

The structure of the system-in-package by using the adapter board as a carrier board or a cover plate can not only change the chip from a flat layout to a stacked layout in terms of architecture, but also integrate passive devices or discrete components and other system constructions. Increase, the performance is greatly improved, representing the future development trend of radio frequency integrated circuit technology, there are great advantages in many aspects:

a) Three-dimensional heterogeneous integrated system-in-package uses a chip shell to complete all interconnections of a system, which greatly reduces the total solder joints and shortens the wiring distance of components, thereby improving electrical performance.

b) Three-dimensional heterogeneous integrated system-in-package superimposes two or more chips in the same adapter board chip, and utilizes the space in the Z direction without adding package pins. The two chips are stacked in the same shell with The chip area ratio is greater than 100%, and the three-chip stacking can be increased to 250%;

c) Small physical size and light weight. For example, the state-of-the-art technology can achieve ultra-thin thickness of only 1mm thick for 4-layer stacked chips, and the weight of three-layer stacked chips is reduced by 35%;

Chips with different functions (such as radio frequency) made of different processes (such as MEMS process, SiGe HBT, SiGe BiCMOS, Si CMOS, III-V (InP, GaN, GaAs) MMIC process, etc.) and different materials (such as Si, GaAs, InP) , biological, microelectromechanical and optoelectronic chips, etc.) are assembled to form a system, which has good compatibility and can be combined with integrated passive components. Data shows that at least 30-50% of the passive components currently used in radios and portable electronics can be embedded.

However, in practical applications, the application of the adapter board has not been widely used, mainly because the process of making the adapter board is too complicated, and the thickness of the adapter board is often less than 200um, so the temporary bonding process must be used in the production process. The input cost and production cost are high, which limits the development of the adapter board in the civilian field.

SUMMARY OF THE INVENTION

The invention provides a method for making an ultra-thick transfer board. By making different TSV holes on the surface of the silicon wafer, the upper and lower surfaces of the silicon wafer can be electrically interconnected. The bonding process can also be easily manufactured, which greatly reduces the manufacturing cost of the adapter board.

A method for manufacturing an ultra-thick adapter board, comprising the following steps:

A: The transition board uses a silicon wafer with an SOI layer, and a through-silicon via (TSV) is made at the bottom of the silicon wafer with an SOI layer. The TSV passes through the SOI layer, stops on the silicon material, and is deposited on the surface of the TSV. Passivation layer and seed layer, and then electroplating metal to obtain a silicon wafer with metal electroplating at the bottom;

B: Make a through silicon hole on the top of the silicon wafer with metal plating at the bottom, which is a top through silicon hole, so that the bottom of the through silicon hole is connected with the metal layer in the bottom through silicon hole, and a silicon wafer with a through silicon hole on the top is obtained. ;

C: Deposit a passivation layer on the top of the silicon wafer with TSVs on the top, then etch to open the passivation layer, and then make an electroplating seed layer, electroplating and filling metal on the surface of the top TSVs, and on the top TSVs Filling the part to obtain a silicon wafer with the top TSV partially filled with metal;

D: Deposit a seed layer on the top remaining TSV of the silicon wafer with the top TSV partially filled with metal, then electroplate the filling metal, and then remove the metal layers on both sides of the interposer by polishing to obtain an ultra-thick interposer.

In step A, the through-silicon via (TSV) is fabricated through photolithography and etching processes. The diameter of the through silicon via (TSV) is 1 um to 1000 um.

The passivation layer is silicon oxide or silicon nitride, or the passivation layer is formed in the form of thermal oxidation, and the thickness of the passivation layer ranges from 10 nm to 100 μm.

The seed layer is fabricated on the insulating layer by physical sputtering, magnetron sputtering or evaporation process. The metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;

The electroplating metal is electroplated with copper at a temperature of 200 to 500 degrees, so that the copper metal covers the surface of the TSV, and densification at a temperature of 200 to 500 degrees makes the copper more dense;

In step B, the opening of the top through-silicon via can be circular, oval or square, the diameter or side length ranges from 10 nm to 1000 um, and the depth ranges from 10 nm to 1000 um;

In step C, the electroplating filler metal is electroplated with copper at 200 to 500°C, so that the copper metal covers the surface of the TSV, and the copper is densified at a temperature of 200 to 500°C to make the copper denser;

In step D, the seed layer adopts a PVD (Physical Vapor Deposition, physical vapor deposition) process. The thickness of the seed layer ranges from 1nm to 100um, which can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, Nickel, etc.;

The electroplating filler metal is electroplated with copper at 200 to 500 °C, and densified at 200 to 500 °C to make the copper denser;

The copper CMP (Chemical Mechanical Polishing) process removes copper from the surface of the silicon wafer to obtain an ultra-thick interposer; the insulating layer on the surface of the silicon wafer can be removed by dry etching or wet etching; the insulating layer on the surface of the silicon wafer can also be removed reserve.

Another method of making an ultra-thick adapter board includes the following steps:

A: The interposer adopts a silicon wafer with double SOI layers. From the top to the bottom of the interposer, the first SOI layer and the second SOI layer are in order. Preliminary through-silicon vias (TSVs) are made on the top of the interposer. Through silicon vias (TSVs) are etched through the first SOI layer, and TSVs continue to be etched at the positions of preliminary TSVs. The preliminary TSVs will be further etched. The (TSV) etching stops on the second layer of SOI to form the first TSV, and the preliminary TSV etching enlarges and stops on the first layer of SOI to form the second TSV, and the second TSV is formed. The diameter of each TSV is larger than the diameter of the first TSV. After the first TSV and the second TSV are formed, a passivation layer is fabricated on the silicon wafer to obtain the first TSV with the first TSV. and the silicon wafer for the second TSV;

B: Continue to make TSVs at the bottom of the silicon wafer with the first TSV and the second TSV directly opposite to the first TSV to form a third TSV, the third TSV The through-hole etching stops on the second SOI layer, and then a passivation layer is formed on the surface of the third through-silicon hole, and then a seed layer is deposited and metal is plated in the third through-silicon hole to obtain a silicon wafer filled with a metal layer at the bottom. ;

C: Open the bottom of the first TSV of the silicon wafer filled with the metal layer at the bottom to expose the metal in the third TSV, and then perform metal plating on the first TSV to fill the first silicon hole with metal. Through holes, obtaining a silicon wafer with metal filling the first through silicon hole;

Open the bottom passivation layer of the first step TSV to expose the bottom of the TSV filled with the thinned surface, and use the TSV metal layer for electroplating to fill the bottom of the first step TSV with metal;

As shown in Figure 19, the bottom passivation layer of the first step TSV is opened by a dry etching process, so that the bottom of the TSV filled with the thinned surface is exposed, and the TSV metal layer is used for electroplating to fill the bottom of the first step TSV with metal;

D: Make a seed layer on the silicon wafer where the first TSV is filled with metal, then fill the second TSV with metal by electroplating, and finally polish the metal layers on both sides to obtain an ultra-thick interposer;

In step A, the diameter of the first through silicon via (TSV) ranges from 10nm to 1000um, and the depth ranges from 10nm to 1000um;

The preliminary through-silicon via (TSV) is fabricated on the surface of the silicon wafer by photolithography and etching;

The passivation layer is formed by deposition of silicon oxide or silicon nitride, or directly thermally oxidized to form a passivation layer, and the thickness of the passivation layer ranges from 10 nm to 100 μm.

In step B, the opening of the third through-silicon via may be circular, oval or square, with a diameter ranging from 10 nm to 1000 um and a depth ranging from 10 nm to 1000 um;

The thickness of the passivation layer ranges from 10 nm to 1000 um, and the material thereof can be silicon oxide or silicon nitride.

The thickness of the seed layer ranges from 1nm to 100um, which can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, Nickel etc.

One or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc. are used for the third through silicon hole electroplating and filling metal.

Compared with the prior art, the present invention has the following advantages:

The present invention is a method for making an ultra-thick adapter board. By making different TSV holes on the surface of the wafer, the upper and lower surfaces of the wafer can be electrically interconnected. The process can also be convenient to manufacture, greatly reduces the manufacturing cost of the adapter board, effectively promotes the popularization of the adapter board, has good economic benefits, is conducive to market promotion and utilization, and has broad application prospects.

Description of drawings

1 is a schematic structural diagram of a silicon wafer with an SOI layer in Example 1;

2 is a schematic structural diagram of etching TSV on a silicon wafer with an SOI layer in Example 1;

3 is a schematic structural diagram of depositing a passivation layer on a silicon wafer in Example 1;

4 is a schematic structural diagram of a seed layer fabricated on a silicon wafer in Example 1;

5 is a schematic structural diagram of electroplating copper on a silicon wafer in Example 1;

6 is a schematic structural diagram of a TSV on the other side of a silicon wafer in Example 1;

7 is a schematic structural diagram of depositing a seed layer on a silicon wafer in Example 1;

8 is a schematic structural diagram of electroplating filling metal on a silicon wafer in Example 1;

9 is a schematic structural diagram of a seed layer deposited by a PVD process on a silicon wafer in Example 1;

10 is a schematic structural diagram of filling metal with TSV on a silicon wafer by front-side electroplating in Example 1;

11 is a schematic structural diagram of an ultra-thick interposer obtained by removing copper on the surface of a silicon wafer in Example 1;

12 is a schematic structural diagram of an interposer silicon wafer with dual SOI silicon oxide layers in Example 2;

13 is a schematic view of the structure of the TSV fabricated on the surface of the silicon wafer of the interposer board with dual SOI silicon oxide layers in Example 2;

FIG. 14 is a schematic structural diagram of continuing to fabricate TSVs on the silicon wafer surface of the interposer with dual SOI silicon oxide layers in Example 2;

15 is a schematic structural diagram of depositing a passivation layer over a silicon wafer in Example 2;

16 is a schematic structural diagram of a TSV on the backside of a thinned silicon wafer in Example 2;

17 is a schematic structural diagram of a passivation layer made on the surface of TSV in Example 2;

Fig. 18 is the structural schematic diagram of depositing seed layer and electroplating filling TSV in Example 2;

19 is a schematic structural diagram of utilizing the TSV metal layer for electroplating and utilizing the TSV metal layer for electroplating in Example 2;

Fig. 20 is the structural representation that makes seed layer on the surface of first step TSV in embodiment 2;

21 is a schematic structural diagram of an ultra-thick adapter plate obtained by polishing two-sided metal layers in Example 2;

Detailed ways

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that are required in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments described in the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

The present invention will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and structural, method, or functional changes made by those skilled in the art according to these embodiments are all included in the protection scope of the present invention.

Furthermore, repeated reference numbers or designations may be used in different embodiments. These repetitions are for simplicity and clarity of description of the present invention and do not represent any association between the different embodiments and/or structures discussed.

The numbers related to the steps mentioned in the various embodiments of the present invention are only for the convenience of description, and have no substantial sequence connection. Different steps in each specific embodiment can be combined in different sequences to achieve the purpose of the present invention.

A method of making an ultra-thick adapter plate introduced by the present invention:

Example 1

A method for manufacturing an ultra-thick adapter board, which specifically includes:

A: The adapter board uses a silicon wafer with SOI (Silicon-On-Insulator, silicon on insulating substrate) layer, and TSV (through silicon via) is made on the surface of the SOI adapter board silicon wafer. The TSV stops under the SOI, and the TSV A passivation layer and a seed layer are deposited on the surface, and a layer of metal is plated on the surface of the TSV;

As shown in FIG. 1 and FIG. 2, prepare the SOI adapter board 101, and fabricate the TSV 103 on the surface of the silicon wafer through photolithography and etching processes;

TSV stops on SOI102, where the diameter of TSV is between 1um and 1000um;

Continue to etch TSV103, and the etching stops on the silicon material under the SOI;

As shown in FIG. 3 , a passivation layer 104 such as silicon oxide or silicon nitride is deposited on the silicon wafer, or directly thermally oxidized, and the thickness of the passivation layer 104 is between 10nm and 100um;

As shown in FIG. 4 , a seed layer 105 is fabricated on the insulating layer by physical sputtering, magnetron sputtering or evaporation process. The thickness of the seed layer 105 ranges from 1 nm to 100 um, which can be one layer or multiple layers. The material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;

As shown in Fig. 5, electroplating copper, so that the copper metal 105 covers the surface of the TSV, and densification at a temperature of 200 to 500 degrees makes the copper more dense;

B: Thin the other side of the wafer, and continue to make TSV (through silicon via) on the surface, so that the bottom of the TSV (through silicon via) opens the bottom of the metal layer in the previous TSV;

As shown in Figure 6, the other side of the wafer (ie silicon wafer with SOI layer) is thinned to a depth of 10um to 1000um, and then TSV107 is made on the thinned surface by photolithography and etching, and the opening of TSV Can be round, oval and square, with a diameter or side length ranging from 10nm to 1000um, and a depth ranging from 10nm to 1000um;

The bottom of the TSV is in contact with the bottom of the front TSV, exposing the bottom metal of the TSV;

C: Deposit a passivation layer on the surface of the new TSV107 and then etch to open the passivation layer, use the electroplating metal layer on the other side as the electroplating seed layer, and electroplating the filling metal on the surface of the TSV;

As shown in FIG. 7 and FIG. 8 , a passivation layer is deposited on the surface of the new TSV, the bottom passivation layer is opened by dry etching, a seed layer 108 is deposited on the front side of the wafer, and then a filler metal 109 is electroplated on the surface of the TSV, and the electroplating Copper, make the copper metal cover the surface of the TSV, and densify the copper at a temperature of 200 to 500 degrees to make the copper denser;

D: Use to deposit a seed layer on the surface of the new TSV, then electroplate the filler metal, and then remove the metal layers on both sides of the adapter board by polishing to obtain an ultra-thick adapter board;

As shown in FIG. 9 , the seed layer 111 is deposited by a PVD process, and the thickness of the seed layer 111 ranges from 1 nm to 100 um, which can be one layer or multiple layers, and the metal material can be titanium, copper, aluminum, silver, palladium, gold , thallium, tin, nickel, etc.;

As shown in FIG. 10, the TSV is filled with metal 112 by front electroplating, copper is electroplated, and the copper is densified at a temperature of 200 to 500 degrees to make the copper denser;

As shown in Figure 11, the copper CMP (Chemical Mechanical Polishing, chemical mechanical polishing) process removes copper on the surface of the silicon wafer to obtain an ultra-thick interposer; the insulating layer on the surface of the silicon wafer can be removed by dry etching or wet etching process; silicon The sheet surface insulating layer may also remain.

Example 2

A method for manufacturing an ultra-thick adapter board, which specifically includes:

A: Do TSV on the surface of the silicon wafer of the double-layer SOI adapter board, the TSV stops under the first layer of SOI, continue to define another TSV on the surface, the TSV stops on the second layer of SOI, and deposit a passivation layer on the surface of the TSV;

As shown in Figure 12 and Figure 13, prepare an interposer silicon wafer with a double-layer SOI silicon oxide layer, and then fabricate TSV on the surface of the silicon wafer through photolithography and etching processes; the diameter of TSV ranges from 10nm to 1000um, and its depth The range is 10nm to 1000um;

Here, the TSV etching stops on the first layer of SOI, and then continues to etch the SOI layer, so that the TSV stops under the first layer of SOI;

As shown in Figure 14, continue to fabricate TSV on the surface of the silicon wafer through photolithography and etching process, and the diameter of the TSV is larger than that of the TSV in Figure 13, and the position coincides with the first TSV, so that the second TSV is etched During TSV, the first TSV will continue to be etched, and finally the first TSV will stop on the second layer of SOI, while the second TSV will stop on the first layer of SOI;

As shown in Figure 15, a passivation layer such as silicon oxide or silicon nitride is deposited on the silicon wafer, or directly thermally oxidized, and the thickness of the passivation layer is between 10nm and 100um;

B: Thin the back of the silicon wafer, and then continue to do TSV at the position where the other side of the silicon wafer coincides with the opening surface of the TSV. The TSV etching stops on the SOI, and then a passivation layer is formed on the surface of the TSV, and then the seed layer is deposited. Electroplating filled TSV;

As shown in Figure 16, the backside of the silicon wafer is thinned to a depth of 10um to 1000um, and then continue to do TSV at the position where the thinned surface overlaps with the front TSV opening surface through photolithography and etching processes. The openings can be circular, oval and square, with diameters ranging from 10nm to 1000um and depths ranging from 10nm to 1000um, and the TSV etching stops on SOI;

As shown in FIG. 17 , a passivation layer is fabricated on the surface of the TSV with a thickness ranging from 10nm to 1000um, and the material can be silicon oxide or silicon nitride;

As shown in Figure 18, a seed layer is deposited. The thickness of the seed layer ranges from 1nm to 100um. It can be one layer or multiple layers. The metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, Nickel, etc.; Finally, the TSV is electroplated and filled, and the metal material can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc.;

C: Open the bottom passivation layer of the first step TSV to expose the bottom of the TSV filled with the thinned surface, and use the TSV metal layer for electroplating to fill the bottom of the first step TSV with metal;

As shown in Figure 19, the bottom passivation layer of the first step TSV is opened by a dry etching process, so that the bottom of the TSV filled with the thinned surface is exposed, and the TSV metal layer is used for electroplating to fill the bottom of the first step TSV with metal;

D: Make a seed layer on the surface of the TSV in the first step, fill the TSV with metal through electroplating, and finally polish the metal layers on both sides to obtain an ultra-thick adapter plate;

As shown in Figure 20, a seed layer is made on the surface of the TSV in the first step;

As shown in Figure 21, electroplating is performed to fill the TSV with metal, and finally the metal layers on both sides are polished to obtain an ultra-thick adapter plate;

It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, but that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments are to be regarded in all respects as illustrative and not restrictive, and the scope of the invention is to be defined by the appended claims rather than the foregoing description, which are therefore intended to fall within the scope of the claims. All changes within the meaning and scope of the equivalents of , are included in the present invention. Any reference signs in the claims shall not be construed as limiting the involved claim.

In addition, it should be understood that although this specification is described in terms of embodiments, not each embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole , the technical solutions in each embodiment can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

1. the manufacture method of a super-thick adapter plate, is characterized in that, comprises the following steps: A: The transition board adopts silicon wafer with SOI layer, through silicon hole is made at the bottom of the silicon wafer with SOI layer, the through silicon hole passes through the SOI layer, stops on the silicon material, and a passivation layer is deposited on the surface of the through silicon hole and seed layer, and then electroplating metal to obtain a silicon wafer with metal electroplating at the bottom; B: Make a through silicon hole on the top of the silicon wafer with metal plating at the bottom, which is a top through silicon hole, so that the bottom of the through silicon hole is connected with the metal layer in the bottom through silicon hole, and a silicon wafer with a through silicon hole on the top is obtained. ; C: Deposit a passivation layer on the top of the silicon wafer with TSVs on the top, then etch to open the passivation layer, and then make an electroplating seed layer, electroplating and filling metal on the surface of the top TSVs, and on the top TSVs Filling the part to obtain a silicon wafer with the top TSV partially filled with metal; D: Deposit a seed layer on the top remaining TSV of the silicon wafer with the top TSV partially filled with metal, then electroplate the filling metal, and then remove the metal layers on both sides of the interposer by polishing to obtain an ultra-thick interposer. 2. The method for making an ultra-thick interposer according to claim 1, wherein in step A, the through-silicon hole is fabricated by photolithography and an etching process, and the diameter of the through-silicon hole is 1um to 1000um. 3. The method for making an ultra-thick interposer according to claim 1, wherein in step A, the passivation layer is silicon oxide or silicon nitride, or the passivation layer is formed by thermal oxidation , the thickness of the passivation layer ranges from 10nm to 100um. 4. The method for making an ultra-thick adapter plate according to claim 1, wherein in step A, the seed layer is made above the insulating layer by physical sputtering, magnetron sputtering or evaporation process, The thickness of the seed layer ranges from 1 nm to 100 um, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel. 5 . The method for manufacturing an ultra-thick adapter plate according to claim 1 , wherein, in step A, the electroplating metal is electroplated with copper at a temperature of 200 to 500 degrees. 6 . 6. The method for making an ultra-thick adapter board according to claim 1, wherein in step B, the opening of the top through silicon hole is a circle, an ellipse or a square, and its diameter or side length ranges It is 10nm to 1000um, and its depth range is 10nm to 1000um. 7. The method for making an ultra-thick adapter plate according to claim 1, wherein in step C, the electroplating filler metal adopts copper electroplating at 200 to 500°C; In step D, the seed layer adopts a physical vapor deposition process, the thickness of the seed layer ranges from 1 nm to 100 μm, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel. 8. A method of making an ultra-thick adapter plate, characterized in that, comprising the following steps: A: The interposer is made of silicon wafers with double SOI layers. From the top to the bottom of the interposer, the first SOI layer and the second SOI layer are in order. Preliminary TSVs are made on the top of the interposer. Etch through the first SOI layer, continue to etch the TSV at the position of the preliminary TSV, the preliminary TSV will continue to be etched, and the preliminary TSV etching will stop on the second layer of SOI to form the first TSV. One TSV, the initial TSV etching and expansion stops on the first layer of SOI to form a second TSV, the diameter of the second TSV is larger than the diameter of the first TSV, the first After the first TSV and the second TSV are formed, a passivation layer is formed on the silicon wafer to obtain a silicon wafer with the first TSV and the second TSV; B: Continue to make TSVs at the bottom of the silicon wafer with the first TSV and the second TSV directly opposite to the first TSV to form a third TSV, the third silicon The through-hole etching stops on the second SOI layer, and then a passivation layer is formed on the surface of the third through-silicon hole, and then a seed layer is deposited, and metal is plated in the third through-silicon hole to obtain a silicon wafer filled with a metal layer at the bottom. ; C: Open the bottom of the first TSV of the silicon wafer filled with the metal layer at the bottom to expose the metal in the third TSV, and then perform metal plating on the first TSV to fill the first silicon hole with metal. Through holes, obtaining a silicon wafer with metal filling the first through silicon hole; D: Make a seed layer on the silicon wafer filled with metal in the first TSV, then fill the second TSV with metal by electroplating, and finally polish the metal layers on both sides to obtain an ultra-thick interposer. 9 . The method for manufacturing an ultra-thick interposer according to claim 8 , wherein in step A, the diameter of the first through silicon hole ranges from 10 nm to 1000 um, and the depth ranges from 10 nm to 1000 um. 10 . ; The preliminary through-silicon vias are fabricated on the surface of the silicon wafer through photolithography and etching processes; The passivation layer is formed by deposition of silicon oxide or silicon nitride, or directly thermally oxidized to form a passivation layer, and the thickness of the passivation layer ranges from 10 nm to 100 μm. 10 . The method for manufacturing an ultra-thick interposer according to claim 8 , wherein in step A and step B, the opening of the third TSV is circular, oval or square, and the 10 . The diameter ranges from 10nm to 1000um, and its depth ranges from 10nm to 1000um; The thickness of the passivation layer ranges from 10nm to 1000um, and its material is silicon oxide or silicon nitride; The thickness of the seed layer ranges from 1 nm to 100 um, and the metal material of the seed layer is titanium, copper, aluminum, silver, palladium, gold, thallium, tin or nickel; One or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel are used as the filling metal for plating in the third through silicon hole.

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