CN104143544A - Wafer silicon through hole structure and preparation method thereof - Google Patents
Wafer silicon through hole structure and preparation method thereof Download PDFInfo
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- CN104143544A CN104143544A CN201410232738.0A CN201410232738A CN104143544A CN 104143544 A CN104143544 A CN 104143544A CN 201410232738 A CN201410232738 A CN 201410232738A CN 104143544 A CN104143544 A CN 104143544A
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Abstract
The invention belongs to the field of micro electronic techniques and discloses a wafer silicon through hole structure. The wafer silicon through hole structure comprises a through hole, a front passivation layer, a through hole passivation layer, a back passivation layer and a cavity in the periphery of the through hole passivation layer. The through hole is formed in a silicon substrate of a wafer, the through hole passivation layer is arranged on the lateral wall in the through hole, the front passivation layer and the back passivation layer are arranged on the front face and the back face of the silicon substrate and are respectively connected with the through hole passivation layer, and the cavity is formed in the periphery of the through hole passivation layer and in the silicon substrate. The thermal stress effect caused by large difference between coefficients of thermal expansion of through hole metal and silicon materials is reduced by forming the cavity outside the through hole in the wafer silicon substrate. Meanwhile, electric field density of the periphery of the through hole is greatly reduced so as to reduce high frequency loss of the through hole.
Description
Technical field
The present invention relates to microelectronics technology, particularly a kind of wafer through-silicon via structure.
Background technology
Along with consumption market strengthens electronic product small size, multi-functional, low-power consumption, high performance demand, planar integrated circuit faces huge challenge, and the characteristic size of CMOS is approached physics limit gradually." super mole ", the 2.5 peacekeeping 3 dimension integrated technologies based on silicon through hole (Throuth-silicon-Via TSV) are expected to become the new power that promotes the development of electronics integrated technology.The aspects such as the structural design of silicon through hole, preparation technology, physical parameter extraction and modeling all become study hotspot.
Because silicon is semi-conducting material, energy gap is 1.12eV only, even if intrinsic silicon at room temperature also has certain conductivity, and in actual use, can be also that silicon materials present better conductivity by mixing alms giver or acceptor impurity conventionally.The resistivity of more common silicon chip is several ohm to tens ohm of zero points.So, different from the conductive through hole (as pcb board and LTCC plate) in dielectric-slab, in the structure of silicon through hole, silicon materials and conductive through hole are filled also has the electrify insulating barrier of buffer action of one deck between metal, this insulating layer material is silicon dioxide normally, and thickness is in hundreds of nanometer to micron; This insulating layer material also can be selected organic polymer material, and thickness can be to tens microns; Between silicon and conductive through hole filling metal (normally copper), thermal expansion coefficient difference is larger, causes silicon through hole to have larger stress around; Silicon is as a kind of semi-conducting material, electromagnetic field existing dielectric polarization loss in silicon materials, there is a conduction loss again, in Sinusoidal Electromagnetic Field situation, for low-resistance silicon materials, conduction loss is very serious, cause the silicon through hole on low-resistance silicon materials to have larger Insertion Loss to high speed signal, affect its frequency applications.
Chip clock and I/O speed break through GHz, and the raising that keeps, and the high frequency performance of silicon through hole becomes one of factor of its application of restriction.Solution open and report has the High Resistivity Si of employing and thickens insulating barrier at present.High Resistivity Si price is more expensive, is only applicable to the silicon keyset of 2.5D simultaneously, is not suitable for the silicon through hole of the active chip of 3D.The thickness of silicon dioxide insulating layer increases limited space, and for thermal oxidation silicon dioxide, thickness is greater than after 1 micron, and oxidation rate is just very slow, the silicon dioxide of PECVD growth, and thickness increases can cause stress and be full of cracks problem.
Because the difference of thermal expansion coefficients of copper and silicon is larger, the thermal stress producing can cause the strain on silicon materials around of silicon through hole, even causes the delamination at silicon through hole interface and the cracking of silicon materials around.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of through-silicon via structure that can reduce the high-frequency loss of silicon through hole, thermal stress effects.
For solving the problems of the technologies described above, the invention provides a kind of wafer through-silicon via structure, described wafer through-silicon via structure comprises: the cavity of through hole, front passivation layer, through hole passivation layer, backside passivation layer and through hole passivation layer periphery; Described through hole is opened on the silicon substrate of described wafer; On described through hole madial wall, through hole passivation layer is set; Described front passivation layer and described backside passivation layer are arranged on described silicon substrate front and back; Described front passivation layer and described backside passivation layer are connected with described through hole passivation layer respectively; In described silicon substrate, described through hole passivation layer periphery arranges cavity.
Further, front passivation layer be take as cutoff layer in described cavity top, and backside passivation layer be take as cutoff layer in described cavity bottom.
Further, in described backside passivation layer, offer through hole; Described through hole connects described cavity.
Further, described through hole is a plurality of independently holes, is looped around around the through hole of described silicon substrate.
Further, described through hole is that annulus hole shape structure ring is around the through hole of described silicon substrate.
Further, described through hole is that semicircular ring hole shape structure ring is around the through hole of described silicon substrate.
Further, the chamber wall thickness scope of described cavity is 1um～100um; The through-hole aperture scope of described silicon substrate is 1um～100um; Hole depth 20um～the 300um of described through hole.
Further, described cavity forms by the silicon substrate material of through hole passivation layer periphery described in etching; Comprise: completely described in etching the silicon substrate material of through hole passivation layer periphery form Perfect Ring around the cavity of described silicon through hole or the silicon substrate material forming section of partially-etched described through hole passivation layer periphery the cavity around described silicon through hole.
Further, described front passivation layer, described through hole passivation layer, described backside passivation layer consist of one deck or multilayer material.
A preparation method for wafer silicon through hole, comprises the following steps:
, complete the wafer rear resist coating that wafer rear metal connects up again and wafer rear dimpling point is processed, on photoresist, make opening figure by lithography;
In the backside passivation layer of wafer, etch the figure of opening;
By the opening in backside passivation layer, adopt anisotropic etch process, in silicon substrate, form deep trouth;
Adopt isotropic etching technique, by deep trouth, in silicon substrate, form cavity.
Wafer through-silicon via structure provided by the invention, by the surrounding's formation cavity structure at silicon through hole, has greatly weakened through hole electric field density around, thereby has reduced high-frequency loss; Owing to having greatly reduced silicon through hole, contact with the effective of silicon substrate simultaneously, the thermal stress effects causing because thermal coefficient of expansion is inconsistent between the filling perforation metal of through hole and silicon substrate is significantly reduced, and then reduction stress, avoid the delamination at silicon through hole interface and the cracking of silicon materials around.
Accompanying drawing explanation
The profile of d/d silicon through hole on the silicon keyset that Fig. 1 provides for the embodiment of the present invention one;
The profile of d/d silicon through hole on the body silicon that Fig. 2 provides for the embodiment of the present invention two;
The profile of d/d silicon through hole on the soi chip that Fig. 3 provides for the embodiment of the present invention three;
On the silicon keyset that Fig. 4 provides for the embodiment of the present invention four, optionally carry out the profile of silicon through hole release;
The back side vertical view of the through hole that Fig. 5 (a), Fig. 5 (b), Fig. 6 (a) and Fig. 6 (b) provide for the embodiment of the present invention;
Preparation technology's schematic flow sheet that the silicon through hole that Fig. 7 (a) provides for the embodiment of the present invention to Fig. 7 (g) discharges;
Fig. 8: the sets of wafers that band discharges silicon through hole is contained in on-chip profile;
Wherein, 1-silicon substrate, 201-front passivation layer, 202-through hole passivation layer, 203-backside passivation layer; 3-wafer frontside metal is wiring layer again, 401-wafer frontside dimpling point, 402-wafer rear dimpling point, 501-through hole, 6-cavity, 7-opening, 8-active area, insulating barrier on 9-SOI sheet, top silicon layer on 10-SOI sheet, 11-substrate, the top-level metallic of 12-substrate 11,13-underfill, 14-slide glass, 15-photoresist.
Embodiment
The wafer of mentioning in the present embodiment refers to the silicon wafer that Si semiconductor production of integrated circuits is used and the various circuit elements that manufacture on silicon wafer and become and have the IC of certain electric sexual function device.The in the situation that of silicon keyset, silicon substrate 1 and on it passive component such as single chip integrated electric capacity, inductance, resistance can form wafer; Especially, while there is no integrated any components and parts on silicon substrate 1, simple silicon substrate 1, in this patent, also can be considered a wafer.In active chip situation, silicon substrate 1 and single chip integrated active area 8 formation wafers on it; When adopting SOI (Silicon-on-Isolator) sheet, the active area 8 on the silicon substrate 1 on SOI sheet, the insulating barrier 9 on SOI sheet, top silicon layer 10 and top silicon layer 10 forms wafer.
Embodiment mono-
As shown in Figure 1, wafer through-silicon via structure comprises: the cavity 6 of through hole 501, front passivation layer 201, through hole passivation layer 202, backside passivation layer 203 and through hole passivation layer periphery; Through hole 501 is opened on the silicon substrate 1 of wafer; On through hole 501 madial walls, through hole passivation layer 202 is set; Front passivation layer 201 and backside passivation layer 203 are arranged on the front and back of silicon substrate 1; Front passivation layer 201 and backside passivation layer 203 are connected with through hole passivation layer 202 respectively, by silicon substrate 1 and extraneous wiring layer isolation; In silicon substrate 1 inside, through hole passivation layer 202 peripheries arrange cavity 6, thereby the silicon substrate material in the peripheral certain limit of through hole 501 is hollowed out, and form cavity structure; Greatly reduce on the one hand filling metal and the contact area of silicon substrate material in through hole 501, thereby greatly weakened the inconsistent thermal stress effects causing of thermal coefficient of expansion due to both, avoided the delamination at silicon through hole interface or the problem that silicon substrate ftractures; On the other hand, because near electric field density through hole is very large, thereby high-frequency loss is larger, and peripheral cavity structure can greatly weaken near the electric field density of silicon through hole, greatly reduces high-frequency loss.
Silicon substrate 1 is conventional silicon chip, and silicon substrate 1 can be N-type doping, the doping of P type or intrinsic doping; The preferred monocrystalline silicon of silicon substrate 1; Also can be polysilicon or amorphous silicon.In the present embodiment, the front and back of silicon substrate 1 has respectively the passivation layer 201 of wafer frontside and the passivation layer 203 of wafer rear; Front passivation layer 201 be take as cutoff layer in the top of cavity 6, and backside passivation layer 203 be take as cutoff layer in the bottom of cavity 6.Face passivation layer 201 has wafer frontside metal wiring layer 3 more above, and backside passivation layer 203 has wafer rear metal wiring layer more below, wafer frontside metal again wiring layer 3 and wafer rear metal again wiring layer can be multilayer.
For simplicity's sake, the wafer rear metal in accompanying drawing 1 again wiring layer has only been drawn one deck, i.e. the metal line 303 in wiring layer again of wafer rear metal in accompanying drawing 1.Wafer frontside metal again wiring layer 3 by wafer frontside metal again the metal line 301 in wiring layer and wafer frontside metal again the insulating barrier 302 in wiring layer form; Silicon substrate 1 surface passivation is played at the front passivation layer 201 of silicon substrate 1 and the back side 203, and the metal line 301 in wiring layer and the wafer rear metal effect of the metal line 303 electricity isolation in wiring layer more again of silicon substrate 1 and wafer frontside metal.
The through hole 501 through-silicon substrates 1 of silicon substrate 1 are realized the wafer frontside metal metal line 301 in wiring layer and wafer rear metal conducting of the metal line 303 in wiring layer more again, through hole passivation layer 202 on silicon through-hole wall is positioned on the hole wall of silicon through hole 501, through hole passivation layer 202 is to complete in preparation technology's flow process of through hole 501, in preparation technology's flow process of through hole 501, through hole passivation layer 202 plays the hole wall of passivation silicon through hole 501, and the effect of the landfill metal of silicon through hole 501 and silicon substrate 1 electricity isolation.
Front passivation layer 201, through hole passivation layer 202 and backside passivation layer 203 can be that one or more layers inorganic material forms, and as silicon dioxide, silicon nitride, silicon oxynitride, but are not limited to this; Also can be that one or more layers organic material forms, as polyimides PI, BCB, but be not limited to this.Front passivation layer 201 and through hole passivation layer 202 can form at same processing step, also can form in different process step, and backside passivation layer 203 forms in wafer rear passivation technology step.
Wafer frontside metal is the metal line 301 in wiring layer and the wafer rear metal material copper normally of the metal line 303 in wiring layer more again, the wafer frontside metal again insulating barrier 302 in wiring layer can be that inorganic material forms, as silicon dioxide, silicon nitride, silicon oxynitride, and other advanced low-k materials, but be not limited to this; Also can be that organic material forms, as polyimides PI, BCB, but be not limited to this.
Wafer frontside dimpling point 401 is for wafer frontside metal being electrically connected between metal line 301 and chip placed on it or substrate or the support plate of wiring layer again, wafer rear dimpling point 402 for wafer rear metal again wiring layer metal line 303 be placed in being electrically connected between chip under it or substrate or support plate; Wafer frontside dimpling point 401 and wafer rear dimpling point 402 can be copper bumps, can be also copper/tin salient points, also can consist of other metal material, metal alloy, metal organic composite electric conducting material; The size dimension of wafer frontside dimpling point 401 and spacing are less than or equal to wafer rear dimpling point 402.According to practical situations, wafer frontside dimpling point 401 can not have.Generally wafer rear dimpling point 402 is absolutely necessary.
The silicon through hole 501 of through-silicon material, generally, its preparation flow comprises: the etching of silicon through hole; The passivation of hole wall, is used to form through hole passivation layer 202; Deposition plating seed layer; Electroplate filling vias; Surface chemistry mechanical polishing CMP.The metal material preferably copper of filling vias, tungsten, but be not limited to this.The preferred Ta/Cu of plating seed layer, TiW/Cu, Ti/Cu, but be not limited to this.
100um is arrived at 1um conventionally in the aperture of silicon through hole 501, and the hole depth of silicon through hole 501 arrives 300um at 20um conventionally.Silicon through hole 501 cavity 6 is around to form in silicon through hole release process process.The chamber wall thickness of silicon through hole cavity 6 around arrives 100um scope at 1um.Silicon through hole release process comprises: the passivation layer of whirl coating, photoetching, etching wafer rear, anisotropic dry are carved silicon, isotropism silicon at dry quarter, removed photoresist.If wafer rear metal again wiring layer is multilayer, before the passivation layer of etching wafer rear, need to etch away corresponding wafer rear metal insulating barrier and the metal level in wiring layer again.
Referring to Fig. 4, front passivation layer 201 be take as cutoff layer in silicon through hole cavity 6 cavity tops around, and backside passivation layer 203 be take as cutoff layer in cavity 6 bottoms, and the through hole passivation layer 202 on silicon through-hole wall is cutoff layer; Can optionally carry out the release of silicon through hole, i.e. the silicon through hole of releasing bearing high speed signal only, and connect power supply, and ground connection, the silicon through hole of carrying direct current signal and low speed signal can not discharge; On silicon through hole 501, carry high speed signal, on silicon through hole 502 and 503, can connect power supply, ground connection, carrying direct current signal and low speed signal, the frequency of common described low speed signal is less than 100MHz.
Referring to Fig. 5 (a), in backside passivation layer 203, offer through hole 7; Through hole 7 connects cavity 6 and extraneous space.Through hole 7 is positioned at wafer rear, in silicon through hole release process process, forms.Silicon through hole cavity 6 is around connected with outside air by through hole 7.Silicon through hole cavity 6 is around unsealed, and through hole 7 can be annular hole shape structure.
Referring to Fig. 5 (b), through hole 7 can be also that semicircular ring hole shape structure ring is around the through hole of described silicon substrate.When the back side of discharged silicon through hole dimpling point 402 is not under discharged silicon through hole, one section of metal line silicon through hole that connection discharges of needs and the with it back side dimpling point 402 of correspondence,
Referring to Fig. 6 (a) and Fig. 6 (b), through hole can be a plurality of independently holes, is looped around around the through hole of described silicon substrate.
Cavity 6 can Perfect Ring around silicon through hole 501, also can part around silicon through hole 501.
Embodiment bis-
Referring to Fig. 2, the present embodiment, on the basis of embodiment mono-, increases active area 8, is positioned at the upper strata of silicon substrate 1, and active area 8 comprises: the electronic circuits such as cmos circuit, BiCMOS circuit or HBT circuit; Can also comprise the optical circuit of light path, opto-electronic device or photonic device composition that photonic device forms, but be not limited to this.The silicon through hole 501 of through-silicon material is penetrated with source region 8.Silicon through hole cavity 6 is around penetrated with source region 8, and now to take through hole passivation layer 202 on silicon through-hole wall and the front passivation layer 201 of silicon substrate 1 be cutoff layer to cavity 6; Cavity 6 also can not be penetrated with source region 8.Now need to control the degree of depth of cavity 6, to guarantee that cavity 6 does not affect the performance of active area 8.Silicon through hole on body silicon can optionally carry out the release of silicon through hole equally.
Embodiment tri-
Referring to Fig. 3, the supplementary features of the present embodiment on the basis of embodiment bis-are, silicon substrate 1, insulating barrier 9 and top silicon layer 10 form a SOI (Silicon-on-Isolation) structure, active area 8 is positioned on top silicon layer 10, silicon through hole 501 through-silicon substrates 1, insulating barrier 9 and top silicon layer 10.Silicon through hole cavity 6 through-silicon substrates 1 around, passivation layer 202 and the top silicon layer 10 on SOI sheet that cavity 6 be take on silicon through-hole wall are cutoff layer.Silicon through hole on SOI sheet can optionally carry out the release of silicon through hole equally.
Embodiment tetra-
The preparation method of wafer silicon through hole, comprises the following steps:
, complete the wafer rear resist coating that wafer rear metal connects up again and wafer rear dimpling point is processed, on photoresist, make opening figure by lithography;
In the backside passivation layer of wafer, etch the figure of opening;
By the opening in backside passivation layer, adopt anisotropic etch process, in silicon substrate, form deep trouth;
Adopt isotropic etching technique, by deep trouth, in silicon substrate, form cavity.
Referring to Fig. 7 (a), wafer frontside has been completed to wafer frontside metal to connect up and wafer frontside dimpling point again, completed silicon through hole, and wafer rear has completed, and wafer rear metal connects up again and wafer frontside and slide glass 14 bondings of the wafer that wafer rear dimpling is selected.
Referring to Fig. 7 (b), wafer rear metal connects up again and the wafer rear resist coating 15 of wafer rear dimpling point completing.
Referring to 7 (c), on photoresist 15, make the figure of opening 7 by lithography, thereby offer through hole 7 for backside passivation layer 203, prepare.
Referring to Fig. 7 (d), on wafer rear passivation layer 203, etch through hole 7, silicon substrate 1 is out exposed; Lithographic method can be dry etching, also can be wet etching.
Referring to Fig. 7 (e), the through hole 7 of take on photoresist 15 and wafer rear passivation layer 203 is mask, adopts anisotropic etch process, and etched silicon substrate 1, to certain depth, forms deep trouth; The preferred dry etching of lithographic method.
Referring to Fig. 7 (f) and Fig. 7 (g), adopt isotropic etching technique, on the deep trouth basis of silicon substrate, form cavity 6; Lithographic method can be dry etching, also can be wet etching, and it is cutoff layer that cavity 6 be take through hole passivation layer 202 on silicon through-hole wall and the front passivation layer 201 of silicon substrate 1.
Wafer frontside is separated with slide glass 14, complete through-silicon via structure preparation.
Referring to Fig. 8, the sets of wafers that band discharges silicon through hole is contained on substrate 11, select again, silicon through hole and wafer rear metal connect up and select and the physical contact of the top-level metallic 12 of substrate 11 is realized and being electrically connected to by wafer rear dimpling by metal line, the wafer frontside dimpling in wiring layer for the front metal of described wafer, electrical connection can be copper copper bonding, copper tin bonding, but is not limited to this; Substrate 11 can be organic substrate, silicon substrate, ceramic substrate, glass substrate, can be also wafer or chip, and wafer or chip can be with silicon through hole also can not be with silicon through hole.Underfill 13 filling tapes discharge the gap of 11 of the wafer of silicon through holes and substrates, and underfill 13 discharges opening on the wafer of silicon through hole and is full of the cavity around silicon through hole by band, improved and be released silicon through hole reliability in actual applications; The fill method of underfill 13 can be that capillary is filled, can is also that vacuum-assisted is filled but is not limited to this.
This patent disclosed high speed low-stress silicon through-hole structure and preparation method are applicable to multiple different silicon through hole preparation method and preparation flow, comprise and first prepare silicon through hole (Via First), prepare silicon through hole (Via Middle), rear silicon through hole (Via Middle) and silicon keyset (Si Interposer) preparation method and the preparation flow prepared midway, only need in former flow process, increase by one " release of silicon through hole " technique, not affect all other technique and method in former flow process; Be applicable to the size and dimension of different silicon through holes; Be applicable to different silicon through hole embedding material and burying method, comprise that copper filling, tungsten are filled, scolder is filled, conducting resinl is filled and hole wall metal and organic polymer mixing filling, but be not limited to this.
Wafer through-silicon via structure provided by the invention, by the surrounding's formation cavity structure at silicon through hole, has greatly weakened through hole electric field density around, thereby has reduced high-frequency loss; Owing to having greatly reduced silicon through hole, contact with the effective of silicon substrate simultaneously, the thermal stress effects causing because thermal coefficient of expansion is inconsistent between the filling perforation metal of through hole and silicon substrate is significantly reduced, and then reduction stress, avoid the delamination at silicon through hole interface and the cracking of silicon materials around.
It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to example, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement technical scheme of the present invention, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (10)
1. a wafer through-silicon via structure, is characterized in that, described wafer through-silicon via structure comprises: the cavity of through hole, front passivation layer, through hole passivation layer, backside passivation layer and through hole passivation layer periphery; Described through hole is opened on the silicon substrate of described wafer; Described through hole passivation layer is through-hole wall, for completely cutting off absolutely of filling perforation metal and silicon substrate; Described front passivation layer and described backside passivation layer are arranged on described silicon substrate front and back; Described front passivation layer and described backside passivation layer are connected with described through hole passivation layer respectively; In described silicon substrate, in described through hole passivation layer periphery, cavity is set.
2. wafer through-silicon via structure as claimed in claim 1, is characterized in that: front passivation layer be take as cutoff layer in described cavity top, and backside passivation layer be take as cutoff layer in described cavity bottom.
3. wafer through-silicon via structure as claimed in claim 1, is characterized in that: in described backside passivation layer, offer through hole; Described through hole connects described cavity.
4. wafer through-silicon via structure as claimed in claim 3, is characterized in that: described through hole is a plurality of independently holes, is looped around around the through hole of described silicon substrate.
5. wafer through-silicon via structure as claimed in claim 3, is characterized in that: described through hole is that annulus hole shape structure ring is around the through hole of described silicon substrate.
6. wafer through-silicon via structure as claimed in claim 3, is characterized in that: described through hole is that semicircular ring hole shape structure ring is around the through hole of described silicon substrate.
7. the wafer through-silicon via structure as described in claim 1～6 any one, is characterized in that: the chamber wall thickness scope of described cavity is 1um～100um; The through-hole aperture scope of described silicon substrate is 1um～100um; Hole depth 20um～the 300um of described through hole.
8. wafer through-silicon via structure as claimed in claim 7, is characterized in that: described cavity forms by the silicon substrate material of through hole passivation layer periphery described in etching; Comprise: completely described in etching the silicon substrate material of through hole passivation layer periphery form Perfect Ring around the cavity of described silicon through hole or the silicon substrate material forming section of partially-etched described through hole passivation layer periphery the cavity around described silicon through hole.
9. wafer through-silicon via structure as claimed in claim 7, is characterized in that, described front passivation layer, described through hole passivation layer, described backside passivation layer consist of one deck or multilayer material.
10. a preparation method for wafer silicon through hole, is characterized in that, comprises the following steps:
, complete the wafer rear resist coating that wafer rear metal connects up again and wafer rear dimpling point is processed, on photoresist, make opening figure by lithography;
In the backside passivation layer of wafer, etch the figure of opening;
By the opening in backside passivation layer, adopt anisotropic etch process, in silicon substrate, form deep trouth;
Adopt isotropic etching technique, by deep trouth, in silicon substrate, form cavity.
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Cited By (4)
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| CN111293079A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Manufacturing method of super-thick adapter plate |
| CN113035810A (en) * | 2021-03-04 | 2021-06-25 | 复旦大学 | Through silicon via structure, packaging structure and manufacturing method thereof |
| CN113035797A (en) * | 2021-03-04 | 2021-06-25 | 复旦大学 | Package structure and method for manufacturing the same |
| US11581219B2 (en) | 2020-04-16 | 2023-02-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and forming method thereof |
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| US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| CN202924718U (en) * | 2012-09-29 | 2013-05-08 | 姜利军 | Double-material micro-cantilever and electromagnetic radiation detector |
| CN103178023A (en) * | 2013-02-28 | 2013-06-26 | 格科微电子（上海）有限公司 | Mixed substrate encapsulation method and mixed substrate encapsulation structure for semiconductor device |
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| US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| CN202924718U (en) * | 2012-09-29 | 2013-05-08 | 姜利军 | Double-material micro-cantilever and electromagnetic radiation detector |
| CN103178023A (en) * | 2013-02-28 | 2013-06-26 | 格科微电子（上海）有限公司 | Mixed substrate encapsulation method and mixed substrate encapsulation structure for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111293079A (en) * | 2020-03-17 | 2020-06-16 | 浙江大学 | Manufacturing method of super-thick adapter plate |
| CN111293079B (en) * | 2020-03-17 | 2023-06-16 | 浙江大学 | Manufacturing method of ultra-thick adapter plate |
| US11581219B2 (en) | 2020-04-16 | 2023-02-14 | Changxin Memory Technologies, Inc. | Semiconductor structure and forming method thereof |
| CN113035810A (en) * | 2021-03-04 | 2021-06-25 | 复旦大学 | Through silicon via structure, packaging structure and manufacturing method thereof |
| CN113035797A (en) * | 2021-03-04 | 2021-06-25 | 复旦大学 | Package structure and method for manufacturing the same |
| CN113035797B (en) * | 2021-03-04 | 2022-09-27 | 复旦大学 | Package structure and method for manufacturing the same |
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| CN104143544B (en) | 2016-08-24 |
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Effective date of registration: 20190430 Address after: 214135 China Sensor Network International Innovation Park D1, 200 Linghu Avenue, Wuxi New District, Jiangsu Province Patentee after: National Center for Advanced Packaging Co., Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co., Ltd. Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |