CN112420604B - Preparation method of TSV (through silicon Via) vertical electrical interconnection device based on thermocompression bonding - Google Patents
Preparation method of TSV (through silicon Via) vertical electrical interconnection device based on thermocompression bonding Download PDFInfo
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- CN112420604B CN112420604B CN202011316969.1A CN202011316969A CN112420604B CN 112420604 B CN112420604 B CN 112420604B CN 202011316969 A CN202011316969 A CN 202011316969A CN 112420604 B CN112420604 B CN 112420604B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
The invention provides a preparation method of a TSV (through silicon via) vertical electrical interconnection device based on thermocompression bonding, which comprises the following steps: s1, etching a through hole on a high-resistance silicon wafer (1); s2, carrying out thermal oxidation treatment on the high-resistance silicon wafer (1) to prepare an isolation layer (2); s3, etching the low-resistance silicon wafer (3) to prepare a movable structure area (4) and an ohmic contact area (5); s4, thermally bonding the high-resistance silicon wafer (1) and the low-resistance silicon wafer (3) to enable the ohmic contact region (5) to be located above the through hole; s5, sputtering a metal seed layer (6) on the inner wall of the through hole; s6, electroplating a metal filler layer (7) on the inner wall of the metal seed layer (6); and S7, thinning and polishing the back surface of the high-resistance silicon wafer (1) to obtain the TSV vertical electrical interconnection device. The preparation method can avoid the problems of size limitation, signal delay and the like caused by long wiring in wire bonding, reduce the capacitance/inductance, realize low power consumption among chips, and show excellent electrical performance in high-frequency and large-bandwidth circuits.
Description
Technical Field
The invention relates to the technical field of sensor manufacturing, in particular to a preparation method of a TSV vertical electrical interconnection device based on thermocompression bonding.
Background
Through-Silicon Via (TSV) technology is a new technical solution for realizing interconnection of stacked chips in a three-dimensional integrated circuit. The TSV can enable the stacking density of chips in the vertical direction to be maximum, the interconnection line between the chips to be shortest and the overall dimension to be minimum, compared with two-dimensional integrated packaging, the three-dimensional integrated technology based on the TSV can further reduce the area and the volume of chip integration, improve the integration level, greatly improve the speed and the low power consumption performance of the chips, become the most attractive technology in the existing electronic packaging technology, and are considered to be capable of realizing the continuation of the Moore's law in the post Moore's era.
The key process of the TSV technology comprises the following steps: through hole manufacturing, through hole film deposition, through hole filling, inter-wafer bonding, chemical mechanical polishing and the like, wherein the through hole manufacturing and inter-wafer bonding mode influences the subsequent thinning step and the layout position of the through holes. In the traditional TSV technology, electrical filling is carried out through etching blind holes, and then salient points are prepared and bonded with other wafers/substrates after thinning, grinding and polishing are carried out to filling interfaces, and the TSV needs to be thinned twice in this mode. The TSV wafer with the upper and lower through holes can be directly bonded with the target wafer by adopting hot-press bonding, then electroplating filling and back thinning are carried out, the steps are simple, the bonding quality is high, the cost is saved, and the manufacturing efficiency is improved.
Disclosure of Invention
Technical problem to be solved
Aiming at the problems, the invention provides a preparation method of a TSV vertical electrical interconnection device based on thermocompression bonding, which is used for at least partially solving the technical problems of complex process, low bonding quality and the like of the traditional TSV technology.
(II) technical scheme
The invention provides a preparation method of a TSV (through silicon via) vertical electrical interconnection device based on thermocompression bonding, which comprises the following steps: s1, etching a through hole on a high-resistance silicon wafer 1; s2, thermally oxidizing the high-resistance silicon wafer 1 to prepare an isolation layer 2; s3, etching the low-resistance silicon wafer 3 to prepare a movable structure region 4 and an ohmic contact region 5; s4, thermally pressing and bonding the high-resistance silicon wafer 1 and the low-resistance silicon wafer 3 to enable the ohmic contact region 5 to be located above the through hole; s5, sputtering a metal seed layer 6 on the inner wall of the through hole; s6, electroplating a metal filler layer 7 on the inner wall of the metal seed layer 6; and S7, thinning and polishing the back surface of the high-resistance silicon wafer 1 to obtain the TSV vertical electrical interconnection device.
Further, the step of separating the movable structure region 4 and the ohmic contact region 5 by photolithography, etching and release is also included in S3.
Further, the movable structure region 4 included in S3 is electrically connected to the ohmic contact region 5.
Further, the low-resistance silicon wafer 3 is an n-type low-resistance silicon material, and the thickness is 0.1-5 um.
Further, the isolation layer 2 is silicon dioxide with the thickness of 20 nm-1 um.
Further, the thickness of the metal seed layer 6 is 50 nm-1 um, and the material comprises copper and tungsten.
Further, the thickness of the metal filler layer 7 is 10 um-100 um, and the material includes copper and tungsten.
Further, the surface roughness of the back silicon layer 2 is less than 10nm after thinning and polishing.
Furthermore, the hot-pressing bonding condition is that the temperature is 400-450 ℃ and the pressure is 2000-3000 mbar.
Further, the method for etching the through hole in the S1 comprises ICP process etching.
(III) advantageous effects
According to the preparation method of the TSV vertical electrical interconnection device based on the thermocompression bonding, the upper layer of wafer and the lower layer of wafer are bonded together in advance through the thermocompression bonding, then the upper layer of wafer and the lower layer of wafer are electrically connected through electroplating filling metal, and the step of thinning, grinding and polishing the front surface in the traditional TSV technical route is simplified.
Drawings
Fig. 1 schematically illustrates a flow chart of a method of fabricating a thermocompression bonding based TSV vertical electrical interconnect device according to an embodiment of the present invention;
FIG. 2 schematically illustrates a structural schematic diagram of a TSV vertical electrical interconnection device based on thermocompression bonding according to an embodiment of the present invention;
FIG. 3 schematically illustrates a process flow diagram for etching vias in a thermal compression bonding based TSV vertical electrical interconnect device, in accordance with an embodiment of the present invention;
FIG. 4 schematically illustrates a process flow diagram of a thermal oxidation process in a thermocompression bonding based TSV vertical electrical interconnect device in accordance with an embodiment of the present invention;
fig. 5 schematically illustrates a process flow diagram for fabricating a movable structural region and an ohmic contact region in a thermocompression bonding based TSV vertical electrical interconnect device in accordance with an embodiment of the present invention;
FIG. 6 schematically illustrates a process flow diagram for thermocompression bonding in a thermocompression bonding based TSV vertical electrical interconnect device according to embodiments of the present invention;
fig. 7 schematically illustrates a process flow diagram for growing a metal seed layer in a thermocompression bonding based TSV vertical electrical interconnect device in accordance with an embodiment of the present invention;
description of the reference numerals
1. High-resistance silicon wafer
2. Hot oxygen layer
3. Low resistance silicon wafer
4. Movable structural section
5. Ohmic contact region
6. Seed layer
7. Filling layer
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments and the accompanying drawings.
An embodiment of the present invention provides a method for manufacturing a TSV vertical electrical interconnection device based on thermocompression bonding, please refer to fig. 1 and fig. 2, including: s1, etching a through hole on a high-resistance silicon wafer 1; s2, carrying out thermal oxidation treatment on the high-resistance silicon wafer 1 to prepare an isolation layer 2; s3, etching the low-resistance silicon wafer 3, and preparing a movable structure region 4 and an ohmic contact region 5; s4, thermally pressing and bonding the high-resistance silicon wafer 1 and the low-resistance silicon wafer 3 to enable the ohmic contact region 5 to be located above the through hole; s5, sputtering a metal seed layer 6 on the inner wall of the through hole; s6, electroplating a metal filler layer 7 on the inner wall of the metal seed layer 6; and S7, thinning and polishing the back surface of the high-resistance silicon wafer 1 to obtain the TSV vertical electrical interconnection device.
Preparing graphical photoresist on the high-resistance silicon wafer 1, using the photoresist as a mask, etching silicon by adopting a BOSCH process, and making through holes from top to bottom; carrying out thermal oxidation on the high-resistance silicon wafer in a high-temperature furnace to manufacture a thermal-oxygen isolation layer 2; preparing a patterned movable structure region 4 and an ohmic contact region 5 on a low-resistance silicon wafer 3 through photoetching, etching and releasing; bonding the low-resistance silicon wafer and the high-resistance silicon wafer together through hot-pressing alignment bonding, wherein the ohmic contact region is right above the TSV; sputtering a metal filler thin layer 6 in the through hole of the TSV as a seed layer by adopting magnetron sputtering; electroplating metal filler 7 in the TSV through hole in electroplating solution by adopting an electroplating method; and thinning and polishing the back surface of the high-resistance silicon wafer 1 by adopting a chemical mechanical polishing method.
The implementation mode of the invention is that a movable structure area and an ohmic contact area are prepared on a low-resistance silicon wafer by combining with an MEMS silicon processing technology, the high-resistance silicon wafer with the TSV through hole and the ohmic contact area are aligned and bonded together through hot-pressing bonding, the side wall protection is carried out through silicon dioxide, and then metal is electroplated in the through hole to complete the up-down electrical connection. The structure reduces the interconnection area and the wiring distance of the package, reduces the parasitic capacitance, reduces the power consumption and simplifies the steps of packaging the upper layer and the lower layer.
On the basis of the above embodiment, the step S3 further includes separating the movable structure region 4 and the ohmic contact region 5 by photolithography, etching, and release.
The specific steps of preparing the movable structure region 4 and the ohmic contact region 5 include defining the movable structure region 4 and the ohmic contact region 5 by patterned photolithography. The movable structure region 4 and the ohmic contact region 5 are separated by ICP etching and wet etching. The movable structure region 4 can perform an electrical signal detection function, such as capacitive and resistive signal detection.
On the basis of the above embodiment, the movable structure region 4 included in S3 is electrically connected to the ohmic contact region 5.
The movable structure region 4 and the ohmic contact region 5 are electrically connected through a low-resistance silicon structure reserved in the steps of photoetching and etching on a low-resistance silicon wafer, and the function of leading out an electrical signal of the movable structure region 4 can be realized.
On the basis of the above embodiment, the low-resistance silicon wafer 3 is an n-type low-resistance silicon material with a thickness of 0.1um to 5um.
The n-type low-resistance silicon material has the advantages of low resistance and high conductivity, and the thickness of the low-resistance silicon wafer 3 in the range has the technical effect of leading out electrical signals in the device with low power consumption.
On the basis of the above embodiment, the isolation layer 2 is silicon dioxide with a thickness of 20nm to 1um.
The isolation layer 2 serves as an electrical isolation and has a technical effect of isolating silicon from metal within this range of thickness.
On the basis of the above embodiment, the thickness of the metal seed layer 6 is 50nm to 1um, and the material includes copper and tungsten.
The metal seed layer plays a role in facilitating transition and metal growth, only a thin layer is needed, the material can be any metal material commonly used for electrical connection, and the material is not limited to copper and tungsten.
On the basis of the above embodiment, the thickness of the metal filler layer 7 is 10um to 100um, and the material includes copper and tungsten.
The metal filler layer continues to grow on the basis of the metal seed layer, the thickness is 10-100 um, the material can be any metal material commonly used for electrical connection, and the metal filler layer is not limited to copper and tungsten. The metal filler layer 4 does not necessarily completely fill the entire through-hole, as long as the metal can form a structure that penetrates the entire through-hole. In the step of electroplating the metal filler in the SOI through hole in the electroplating solution by adopting an electroplating method, the filling effect of the metal in the through hole is controlled by adjusting the proportion, the temperature and the time of the electrochemical solution.
On the basis of the above embodiment, the surface roughness of the back silicon layer 2 is less than 10nm after thinning and polishing.
Grinding and polishing the SOI back silicon layer by adopting chemical mechanical grinding and polishing to remove redundant copper on the surface; the surface roughness is less than 10nm, which is beneficial to improving the hot-pressing bonding quality.
On the basis of the above embodiment, the thermal compression bonding conditions are 400-450 ℃ and 2000-3000 mbar pressure.
The duration of the hot-pressing bonding is 2 hours, and then the hot-pressing bonding is completed after the high-temperature annealing at 1050 ℃ for two hours. The hot-press bonding has the technical effects of high adhesiveness, large bonding force and high yield under the condition.
On the basis of the above embodiment, the method for etching the through hole in S1 includes ICP process etching.
Common methods for etching through holes include laser drilling, ICP etching, DRIE etching, and the like. The ICP process adopted for etching has the advantages of high etching rate and good side wall protection.
According to the preparation method of the TSV vertical electrical interconnection device based on the thermocompression bonding, the movable structure region of the upper-layer low-resistance silicon wafer is electrically connected with the ohmic contact region, then the vertical electrical connection is achieved through the thermocompression bonding and the TSV through hole of the lower-layer high-resistance silicon wafer, the upper-layer wafer and the lower-layer wafer are bonded together in advance through the thermocompression bonding, and the steps of thinning and grinding the front side in the traditional TSV technical route are simplified.
The present invention is described in detail below with an embodiment, please refer to fig. 2 to 7, fig. 2 is a schematic diagram of a vertical electrical interconnection structure of a MEMS sensor, fig. 3 to 7 are schematic diagrams of a process, and the specific steps are as follows:
s1, preparing graphical photoresist on a high-resistance silicon wafer 1, using the photoresist as an etching mask, and etching the wafer by adopting an ICP BOSCH process to manufacture a TSV through hole which is vertically communicated, please refer to FIG. 3;
s2, thermally oxidizing the silicon dioxide layer 2 with the thickness of 200nm in a high-temperature furnace, and referring to a figure 4;
s3, preparing a movable structure area 4 and an ohmic contact area 5 on the low-resistance silicon wafer 3 by adopting the steps of photoetching, etching, corroding and the like, as shown in a figure 5;
s4, adopting hot-pressing alignment bonding to bond the two wafers together in an up-and-down alignment manner, please refer to FIG. 6;
s5, sputtering a 50nm metal copper thin layer 6 serving as a seed layer in the TSV through hole by adopting magnetron sputtering, and referring to fig. 7;
s6, electroplating metal copper 7 in the TSV through hole in electroplating solution by adopting an electroplating method;
and S7, grinding and polishing the back surface of the high-resistance silicon 1 by adopting chemical mechanical grinding and polishing to remove redundant copper on the surface, wherein the surface roughness is less than 10nm.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A preparation method of a TSV vertical electrical interconnection device based on thermocompression bonding comprises the following steps:
s1, etching a through hole on a high-resistance silicon wafer (1);
s2, carrying out thermal oxidation treatment on the high-resistance silicon wafer (1) to prepare an isolation layer (2);
s3, etching the low-resistance silicon wafer (3) to prepare a movable structure region (4) and an ohmic contact region (5);
s4, thermally pressing and bonding the high-resistance silicon wafer (1) and the low-resistance silicon wafer (3) to enable the ohmic contact region (5) to be located above the through hole;
s5, sputtering a metal seed layer (6) on the inner wall of the through hole;
s6, electroplating a metal filler layer (7) on the inner wall of the metal seed layer (6);
and S7, thinning and polishing the back surface of the high-resistance silicon wafer (1) to obtain the TSV vertical electrical interconnection device.
2. The method for preparing the TSV vertical electrical interconnection device based on thermocompression bonding as claimed in claim 1, wherein the step S3 further comprises separating the movable structure region (4) and the ohmic contact region (5) by photolithography, etching and release.
3. The method for preparing a thermocompression bonding-based TSV vertical electrical interconnection device according to claim 2, wherein the step S3 further comprises electrically connecting the movable structure region (4) with an ohmic contact region (5).
4. The method for preparing the TSV vertical electrical interconnection device based on thermocompression bonding according to claim 1, wherein the low resistance silicon wafer (3) is an n-type low resistance silicon material with a thickness of 0.1-5 um.
5. The method for preparing the TSV vertical electrical interconnection device based on thermocompression bonding according to claim 1, wherein the isolation layer (2) is silicon dioxide and has a thickness of 20nm to 1um.
6. The method for manufacturing the TSV vertical electrical interconnection device based on the thermocompression bonding as claimed in claim 1, wherein the thickness of the metal seed layer (6) is 50nm to 1um, and the material comprises copper and tungsten.
7. The method for preparing the TSV vertical electrical interconnection device based on thermocompression bonding according to claim 6, wherein the thickness of the metal filler layer (7) is 10-100 um, and the material comprises copper and tungsten.
8. The method for preparing the TSV vertical electrical interconnection device based on thermocompression bonding according to claim 1, wherein the surface roughness of the back surface of the high-resistance silicon wafer (1) is less than 10nm after thinning and polishing.
9. The method for preparing a TSV vertical electrical interconnection device based on thermocompression bonding as claimed in claim 1, wherein the thermocompression bonding is performed under the conditions of a temperature of 400-450 ℃ and a pressure of 2000-3000 mbar.
10. The method for manufacturing the TSV vertical electrical interconnection device based on thermocompression bonding as claimed in claim 1, wherein the method for etching the through hole in the S1 comprises ICP process etching.
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| JP2002204047A (en) * | 2000-12-28 | 2002-07-19 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing flexible printed wiring board |
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| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| CN102214624A (en) * | 2011-05-17 | 2011-10-12 | 北京大学 | Semiconductor structure with through holes and manufacturing method thereof |
| CN110622297A (en) * | 2017-05-31 | 2019-12-27 | 国际商业机器公司 | Superconducting metal of through-silicon via |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7183176B2 (en) * | 2004-08-25 | 2007-02-27 | Agency For Science, Technology And Research | Method of forming through-wafer interconnects for vertical wafer level packaging |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002204047A (en) * | 2000-12-28 | 2002-07-19 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing flexible printed wiring board |
| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| CN101483149A (en) * | 2009-02-13 | 2009-07-15 | 华中科技大学 | Production method for through wafer interconnection construction |
| CN102214624A (en) * | 2011-05-17 | 2011-10-12 | 北京大学 | Semiconductor structure with through holes and manufacturing method thereof |
| CN110622297A (en) * | 2017-05-31 | 2019-12-27 | 国际商业机器公司 | Superconducting metal of through-silicon via |
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