CN117766492A - Silicon bridge module integrated with passive device and manufacturing method thereof - Google Patents

Abstract

The invention provides a silicon bridge module of an integrated passive device, which comprises a substrate, a first insulating layer arranged on the first surface of the substrate, a capacitor arranged on the surface of the first insulating layer, a second insulating layer arranged on the surface of the capacitor and exposing at least part of electrodes of the capacitor, a first metal interconnection layer arranged on the surface of the second insulating layer and electrically connected with the capacitor, and an external bonding pad arranged on the outermost layer of the first metal interconnection layer and electrically connected with the first metal interconnection layer. Wherein the first metal interconnect layer includes one or more layers of conductive traces and an insulating medium disposed between the conductive traces and having an inductive device integrated therein. The silicon bridge module realizes the integrated integration of the interconnection lines and the passive devices among chips, integrates the processing function of a signal or power supply transmission network while realizing the high-speed transmission of signals, improves the integration level of the system, saves the packaging volume, and can be applied to the field of heterogeneous integrated products such as Chiplet and the like.

Description

Silicon bridge module integrated with passive device and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a silicon bridge module integrated with a passive device and a manufacturing method thereof.

Background

With the rapid increase of the demands of electronic devices for high performance and multifunctionality of chips and the gradual approach of integrated circuit manufacturing processes to the limit of physical dimensions, the development of moore's law is in the bottleneck, and the chip industry has entered the "post-moore" era, which has hardly met the demands of continuous improvement of chip performance by simply relying on feature size shrinkage. Under the background, the realization of systematic integration of multiple chips by advanced packaging becomes one of the important directions for improving the chip performance.

In the way of realizing heterogeneous integration of chips, the embedded silicon bridge can reduce the packaging area, reduce the process difficulty and cost of the packaging body, and realize high-density interconnection among chips at the same time, so that the embedded silicon bridge has been developed as a mainstream advanced packaging solution. However, the conventional silicon bridge can only realize planar interconnection, and communication in the vertical direction of the silicon bridge cannot be considered. Meanwhile, the existing silicon bridge fails to consider the requirements of the existing silicon bridge in terms of signal or power transmission processing, such as filtering, decoupling and other functions, and therefore, no implementation in terms of introducing passive devices such as capacitors, inductors and the like into the embedded silicon bridge is seen.

Meanwhile, passive devices play an important role in power and signal transmission of the package. For example, heterogeneous integration requires a robust power transfer network (PDN) to ensure stability of the operating states of the chips. However, these passive devices are often integrated in integrated circuits in the form of discrete devices, which limits efforts to heterogeneous integration of chips in terms of reducing overall area and volume, while they generally require longer trace lengths, which also brings about stronger parasitic effects, thereby limiting overall performance and stability of the package.

Disclosure of Invention

In order to solve some or all of the problems in the prior art, a first aspect of the present invention provides a silicon bridge module for integrating a passive device, which implements integrated three-dimensional integration of a silicon bridge and the passive device through a wafer-level process, and simultaneously integrates a TSV structure inside the three-dimensional silicon bridge, so as to implement vertical interconnection of power or signals, improve the integration level of a system, and facilitate high-reliability communication between high-performance chips, the silicon bridge module includes:

a substrate, the first surface of which is provided with a first insulating layer;

a capacitor disposed on the surface of the first insulating layer;

a second insulating layer disposed on a surface of the capacitor, but exposing at least a portion of the electrode of the capacitor;

the first metal interconnection layer is arranged on the surface of the second insulation layer and comprises one or more layers of conductive circuits and an insulation medium arranged between the conductive circuits, and the capacitor is electrically connected with the first metal interconnection layer;

an inductive device integrated in the metal interconnect layer; and

and the external bonding pad is arranged on the outermost layer of the first metal interconnection layer and is electrically connected with the first metal interconnection layer.

Further, the capacitor is a deep trench capacitor, which is disposed in a deep trench of the substrate, and the deep trench capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer, wherein the first electrode layer, and the second electrode layer are electrically connected with the first metal interconnection layer.

Further, the capacitor is a planar capacitor, and the planar capacitor is disposed on the surface of the insulating layer and includes a first electrode layer, a dielectric layer, and a second electrode layer, where the first electrode layer, and the second electrode layer are electrically connected to the first metal interconnection layer.

Further, the silicon bridge module further comprises a silicon through hole penetrating through the substrate, wherein a first end of the silicon through hole is electrically connected with the first metal interconnection layer, and a second end of the silicon through hole exposes a second surface of the substrate opposite to the first surface of the substrate.

Further, the silicon bridge module further comprises a second metal interconnection layer, wherein the second metal interconnection layer is arranged on the second surface of the substrate, the second metal interconnection layer comprises one or more layers of conductive circuits and an insulating medium arranged between the conductive circuits, and the second end of the silicon through hole is electrically connected with the second metal interconnection layer.

A second aspect of the present invention provides a method of manufacturing a silicon bridge module as described above, comprising:

depositing a first insulating layer on the surface of a silicon wafer, and forming a capacitor, wherein the capacitor comprises a first electrode layer, a dielectric layer and a second electrode layer;

depositing a second insulating layer on the surface of the second electrode layer, and windowing to lead out the first electrode layer and the second electrode layer;

forming a first metal interconnection layer on the surface of the second insulating layer, wherein the first metal interconnection layer comprises an inductance coil structure;

preparing an external bonding pad on the surface of the first metal interconnection layer; and

and thinning the back surface of the silicon wafer, and cutting to obtain a single silicon bridge.

Further, depositing a first insulating layer and forming a capacitor includes:

etching a deep silicon groove on the first surface of the silicon wafer;

depositing a first insulating layer on the first surface of the silicon wafer and the surface of the deep silicon groove; and

and sequentially filling the first electrode, the dielectric material and the second electrode in the deep silicon groove.

Further, depositing a first insulating layer and forming a capacitor includes:

depositing a first insulating layer on the surface of the silicon wafer;

preparing a first electrode layer and a part of circuits of a first metal interconnection layer on the surface of the first insulating layer;

depositing an intermediate insulating layer on the first electrode layer and the circuit surface, but exposing at least part of the surface of the first electrode layer to deposit a dielectric material;

windowing is carried out on the middle insulating layer so as to lead out the first electrode layer and an external bonding pad of a circuit; and

and forming a second electrode layer and a part of circuits of the first metal interconnection layer on the intermediate insulating layer.

Further, the manufacturing method further includes:

forming a through silicon via on the silicon wafer, wherein a first end of the through silicon via is electrically connected with the first metal interconnection layer; and/or

And grinding and thinning the second surface of the silicon wafer to enable the through silicon hole to be exposed, forming a second metal interconnection layer on the second surface of the silicon wafer, and electrically connecting the second end of the through silicon hole with the second metal interconnection layer.

A third aspect of the present invention provides a package structure comprising a silicon bridge module as described above.

The silicon bridge module for the integrated passive device provided by the invention has the advantages that the silicon bridge structure with the integrated passive device is prepared through the wafer-level process, the integrated integration of the inter-chip interconnection circuit and the passive device is realized, the signal high-speed transmission is realized, the processing function of a signal or power supply transmission network is integrated, the integration level of a system is improved, the packaging volume is saved, and the silicon bridge module is compatible with the existing packaging process and has the process realizability. The silicon bridge module can be applied to the field of heterogeneous integrated products such as Chiplet and the like.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.

Fig. 1 shows a schematic structure of a silicon bridge module integrated with a passive device according to an embodiment of the present invention;

fig. 2 shows a schematic structural diagram of a silicon bridge module integrated with a passive device according to another embodiment of the present invention;

fig. 3 shows a schematic structural diagram of a silicon bridge module integrated with a passive device according to still another embodiment of the present invention;

fig. 4 shows a schematic structural diagram of a silicon bridge module integrated with a passive device according to still another embodiment of the present invention;

FIGS. 5a to 5d are schematic structural views showing different package structures including silicon bridge modules according to various embodiments of the present invention;

FIG. 6 is a flow chart of a method of fabricating a silicon bridge module integrated with a passive device according to one embodiment of the invention;

figures 7a to 7e show a process schematic of a method of manufacturing a silicon bridge module for integrating passive devices according to one embodiment of the invention;

fig. 8a to 8e are process schematic diagrams showing a method for manufacturing a silicon bridge module integrated with a passive device according to still another embodiment of the present invention;

fig. 9a to 9e are process schematic diagrams showing a method of manufacturing a silicon bridge module integrated with a passive device according to still another embodiment of the present invention; and

fig. 10a to 10e are process diagrams showing a method of manufacturing a silicon bridge module integrated with a passive device according to still another embodiment of the present invention.

Detailed Description

In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

It should be noted that the embodiments of the present invention describe the process steps in a specific order, however, this is merely to illustrate the specific embodiment and not to limit the order of the steps. In contrast, in various embodiments of the present invention, the order of the steps may be adjusted according to process adjustments.

Aiming at the defects that the existing silicon bridge does not consider the integration of passive devices into the silicon bridge, and the passive devices are often required to be integrated in the form of discrete devices, so that the space occupation rate is high, the parasitic effect is large and the like, the invention provides the silicon bridge module for integrating the passive devices, which integrates the integrated passive devices into the silicon bridge in a three-dimensional stacking manner, so that the integration of the high-density interconnection silicon bridge and the silicon-based integrated passive devices is realized.

Specifically, the silicon bridge module of the integrated passive device comprises a substrate, a first insulating layer arranged on the first surface of the substrate pair, a capacitor arranged on the surface of the first insulating layer, a second insulating layer arranged on the surface of the capacitor and exposing at least part of electrodes of the capacitor, a first metal interconnection layer arranged on the surface of the second insulating layer and electrically connected with the capacitor, and an external bonding pad arranged on the outermost layer of the first metal interconnection layer and electrically connected with the first metal interconnection layer. In some embodiments of the invention, the silicon bridge module further comprises a through silicon via extending through the substrate in electrical connection with the first metal interconnect layer, and/or a second metal interconnect layer disposed on the second surface of the substrate in electrical connection with the through silicon via.

In an embodiment of the present invention, the capacitor may be a deep trench capacitor or a planar capacitor. The silicon bridge module may have different structures based on the difference in capacitance types and the presence or absence of through silicon vias.

Fig. 1 to 4 respectively show structures of different silicon bridge modules in various embodiments of the present invention. The silicon bridge module shown in fig. 1 adopts a deep trench capacitor and is not provided with a through silicon via; the silicon bridge module shown in fig. 2 adopts a deep trench capacitor and is provided with a through silicon via; the silicon bridge module shown in fig. 3 employs planar capacitors and does not have through silicon vias; and the silicon bridge module shown in fig. 4 adopts a planar capacitor and is provided with a through silicon via.

The structure and fabrication method of each of the silicon bridge modules are further described below with reference to the drawings of the various embodiments.

The silicon bridge module shown in fig. 1 includes a substrate 101, a first insulating layer 121, a second insulating layer 122, a deep trench capacitor 131, a first metal interconnect layer 141, an inductive device 107, and an external pad 105. The deep trench capacitor 131 is disposed in a deep silicon trench at the first surface of the substrate 101, and includes a first electrode layer 1311, a dielectric layer 1312, and a second electrode layer 1313. The deep trench capacitor 131 is isolated from the substrate 101 by a first insulating layer 121. In one embodiment of the present invention, the substrate 101 is made of silicon. In one embodiment of the present invention, the first metal interconnect layer 141 includes one or more layers of conductive traces and an insulating medium disposed between the conductive traces. The inductive device 107 is integrated in the first metal interconnect layer 141. In one embodiment of the invention, the inductive device comprises an inductor coil structure.

The silicon bridge module shown in fig. 2 is substantially identical to the silicon bridge module structure shown in fig. 1 except that it further includes through silicon vias 106. The through silicon via 106 penetrates through the substrate 101, and has a first end electrically connected to the first metal interconnection layer 141, and a second end exposed on the second surface of the substrate 101. A second end of which may be provided with an external bond pad, for example, to which it is electrically connected, or a second metal interconnect layer 142. Similarly, the second metal interconnect layer 142 includes one or more layers of conductive traces and an insulating medium disposed between the conductive traces.

The silicon bridge module shown in fig. 3 is different from the silicon bridge module shown in fig. 1 in that the capacitance type is different, and includes a substrate 101, a first insulating layer 121, a second insulating layer 122, an intermediate insulating layer 123, a planar capacitor 132, a first metal interconnection layer 141, an inductance device 107, and an external pad 105. The planar capacitor 132 is disposed on the surface of the first insulating layer 121, and includes a first electrode layer 1321, a dielectric layer 1322, and a second electrode layer 1323. As shown, the first electrode layer 1321 is disposed on the surface of the first insulating layer 121, but does not cover the entire first insulating layer 121, and the surface of the first insulating layer, on which the first electrode layer is not disposed, may form part of the lines of the first metal interconnection layer at the same time. The dielectric layer 1322 is disposed on the surface of the first electrode layer 1321, but does not cover the entire first electrode layer, so as to facilitate the extraction of the first electrode layer. The second electrode layer 1323 is disposed on a surface of the dielectric layer 1322, and has a size substantially identical to that of the dielectric layer 1322. Similarly, the periphery of the second electrode layer 1323 may also form part of the wiring of the first metal interconnection layer simultaneously.

The silicon bridge module shown in fig. 4 is substantially identical to the silicon bridge module structure shown in fig. 3, except that it further includes through silicon vias 106. The through silicon via 106 penetrates through the substrate 101, and has a first end electrically connected to the first metal interconnection layer 141, and a second end exposed on the second surface of the substrate 101. A second end of which may be provided with an external bond pad, for example, to which it is electrically connected, or a second metal interconnect layer 142.

The various silicon bridge modules described above can be applied to fan-out packages or FCBGAs employing embedded substrates. Fig. 5a to 5d respectively show schematic structural views of different package structures including silicon bridge modules according to different embodiments of the present invention. Fig. 5a and 5b illustrate the use of a silicon bridge module 001 without a through silicon via structure in a fan-out package, and FCBGA employing a buried substrate, respectively. As shown, the silicon bridge module may be electrically connected to the chip, circuit in the package structure, either directly or through a rerouting structure. Fig. 5c and 5d illustrate the use of a silicon bridge module 002 with through-silicon via structure in fan-out packages, respectively, FCBGAs employing a buried substrate. As shown in the figure, the silicon bridge module with the through silicon vias can further realize vertical connection of devices such as chips in the packaging structure.

Fig. 6 is a flow chart illustrating a method of manufacturing a silicon bridge module integrated with a passive device according to an embodiment of the present invention. As shown in fig. 6, the method for manufacturing the silicon bridge module includes:

first, in step 601, a first insulating layer is deposited. Depositing a first insulating layer on the surface of the silicon wafer;

next, at step 602, a capacitor is formed. Forming a capacitor on the surface of the first insulating layer, wherein the capacitor comprises a first electrode layer, a dielectric layer and a second electrode layer;

next, in step 603, a second insulating layer is deposited. Depositing a second insulating layer on the surface of the second electrode layer of the capacitor, and windowing to lead out a first electrode and a second electrode of the capacitor;

next, at step 604, a first metal interconnect layer is formed. Forming a first metal interconnection layer on the surface of the second insulating layer, wherein the first metal interconnection layer comprises an inductance coil structure;

next, at step 605, an external bond pad is prepared. Preparing an external bonding pad on the surface of the first metal interconnection layer; and

finally, at step 606, the wafer is diced. And thinning the back surface of the silicon wafer, and cutting to obtain a single silicon bridge.

In one embodiment of the present invention, the silicon bridge module has a through silicon via and/or a second metal interconnection layer, so that in the preparation process, processes such as etching, depositing an insulating layer, filling, flattening and the like of the through silicon via are further required to be performed in the silicon wafer, and finally, after the through silicon via is exposed, the second metal interconnection layer is formed on the second surface of the silicon wafer.

Fig. 7a to 7e show a process schematic of a method of manufacturing a silicon bridge module without through silicon vias using deep trench capacitors. As shown in the figure, the method for manufacturing the silicon bridge module without the through silicon vias by using the deep trench capacitor comprises the following steps:

first, as shown in fig. 7a, a deep silicon trench is etched on a first surface of a silicon wafer 101, and a first insulating layer 121 is deposited, and then, a first electrode layer 1311, a High K dielectric material 1312 and a second electrode layer 1313 are sequentially filled to form a deep trench capacitor 131;

next, as shown in fig. 7b, a second insulating layer 122 is deposited to cover the second electrode layer, and windows are opened on the second insulating layer to realize the extraction of the first electrode layer and the second electrode layer;

next, as shown in fig. 7c, a plurality of interconnection lines and dielectric layers are alternately prepared to form a first metal interconnection layer 141, wherein an inductance coil structure 107 can be introduced into the interconnection lines, and an external bonding pad 105 is prepared on the surface of the interconnection lines, so that subsequent connection with a chip is facilitated;

next, as shown in fig. 7d, the second surface of the silicon wafer is thinned; and

finally, as shown in fig. 7e, chip dicing is performed to prepare a single silicon bridge.

Fig. 8a to 8e show a process schematic of a method for manufacturing a silicon bridge module with through silicon vias using deep trench capacitors. As shown in the figure, the method for manufacturing a silicon bridge module with a through silicon via using a deep trench capacitor includes:

first, as shown in fig. 8a, a deep silicon trench is etched on a first surface of a silicon wafer 101, and a first insulating layer 121 is deposited, and then, a first electrode layer 1311, a High K dielectric material 1312 and a second electrode layer 1313 are sequentially filled to form a deep trench capacitor 131;

next, as shown in fig. 8b, the processes of etching, depositing the second insulating layer 122, filling, planarizing, etc. of the through-silicon via 106 are performed to form a through-silicon via;

next, as shown in fig. 8c, a window is opened on the second insulating layer, so as to lead out the first electrode layer and the second electrode layer, then, a plurality of layers of interconnection lines and dielectric layers are alternately prepared on the surface of the second insulating layer, so as to form a first metal interconnection layer 141, wherein an inductance coil structure 107 can be introduced into the interconnection lines, and an external bonding pad 105 is prepared on the surface of the interconnection lines, so that the subsequent connection with a chip is facilitated;

next, as shown in fig. 8d, a temporary bonding plate 003 is disposed on the surface of the first metal interconnection layer, and the second surface of the silicon wafer is thinned to achieve the outcrop of the through silicon via, and a second metal interconnection structure 142 is formed on the second surface of the silicon wafer or an external bonding pad is formed at the end surface of the through silicon via; and

finally, as shown in fig. 8e, the temporary bonding plate is removed, and chip dicing is performed to prepare a single silicon bridge.

Fig. 9a to 9e show a process schematic of a method of manufacturing a silicon bridge module without through silicon vias using planar capacitors. As shown in the figure, the method for manufacturing the silicon bridge module which adopts the planar capacitor and does not have the through silicon vias comprises the following steps:

first, as shown in fig. 9a, a first insulating layer 121 is deposited on a first surface of a silicon wafer 101, and a first electrode layer 1321 and a part of a circuit which is in the same stack as the first electrode layer are prepared;

next, as shown in fig. 9b, an intermediate insulating layer 123 and a High K dielectric material 1322 are deposited, wherein the High K dielectric material is embedded in the intermediate insulating layer, and then windows are formed on the intermediate insulating layer to realize the extraction and interlayer interconnection of the first electrode layer, and a second electrode layer 1323 is prepared to form a planar capacitor 132, and simultaneously, an interconnection line of the same stack as that of the second electrode layer is prepared;

next, as shown in fig. 9c, a second insulating layer 122 is deposited to cover the second electrode layer, and windows are opened on the second insulating layer to realize the extraction of the second electrode layer, and then a plurality of interconnection lines and dielectric layers are alternately prepared to form a first metal interconnection layer 141, wherein an inductance coil structure 107 can be introduced into the interconnection lines, and an external bonding pad 105 is prepared on the surface of the interconnection lines, so that the subsequent connection with a chip is facilitated;

next, as shown in fig. 9d, the second surface of the silicon wafer is thinned; and

finally, as shown in fig. 9e, chip dicing is performed to prepare individual silicon bridges.

Fig. 10a to 10e show a process schematic of a method for manufacturing a silicon bridge module with through silicon vias using planar capacitors. As shown in the figure, the method for manufacturing a silicon bridge module using a planar capacitor and having a through silicon via includes:

first, as shown in fig. 10a, etching, depositing a first insulating layer 121, filling, planarizing and the like of a through silicon via 106 are performed on a first surface of a silicon wafer 101 to form a through silicon via;

next, as shown in fig. 10b, a first electrode layer 1321 is prepared on the surface of the first insulating layer, and a part of the circuit is formed on the same layer stack as the first electrode layer, then an intermediate insulating layer 123 and a High K dielectric material 1322 are deposited, wherein the High K dielectric material is embedded in the intermediate insulating layer, then windows are formed on the intermediate insulating layer, the extraction and interlayer interconnection of the first electrode layer are realized, and a second electrode layer 1323 is prepared to form a planar capacitor 132, and meanwhile, the interconnection circuit of the second electrode layer is prepared on the same layer stack;

next, as shown in fig. 10c, a second insulating layer 122 is deposited to cover the second electrode layer, and windows are opened on the second insulating layer to realize the extraction of the second electrode layer, and then a plurality of interconnection lines and dielectric layers are alternately prepared to form a first metal interconnection layer 141, wherein an inductance coil structure 107 can be introduced into the interconnection lines, and an external bonding pad 105 is prepared on the surface of the interconnection lines, so that the subsequent connection with a chip is facilitated;

next, as shown in fig. 10d, a temporary bonding plate 003 is disposed on the surface of the first metal interconnection layer, and the second surface of the silicon wafer is thinned to achieve the outcrop of the through silicon via, and a second metal interconnection structure 142 is formed on the second surface of the silicon wafer or an external bonding pad is formed at the end surface of the through silicon via; and

finally, as shown in fig. 10e, the temporary bonding plate is removed, and chip dicing is performed to prepare a single silicon bridge.

The silicon bridge module of the integrated passive device provided by the invention has the advantages that the silicon bridge structure with the integrated passive device is prepared through the wafer-level process, the integrated integration of the inter-chip interconnection circuit and the passive device is realized, the high-speed signal transmission is realized, the processing function of a signal or power supply transmission network is integrated, the integration level of a system is improved, and the packaging volume is saved.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A silicon bridge module for integrating passive devices, comprising:

a substrate, the first surface of which is provided with a first insulating layer;

a capacitor disposed on the surface of the first insulating layer;

a second insulating layer disposed on a surface of the capacitor, but exposing at least a portion of the electrode of the capacitor;

the first metal interconnection layer is arranged on the surface of the second insulation layer and comprises one or more layers of conductive circuits and an insulation medium arranged between the conductive circuits, and the capacitor is electrically connected with the first metal interconnection layer;

an inductive device integrated in the metal interconnect layer; and

and the external bonding pad is arranged on the outermost layer of the first metal interconnection layer and is electrically connected with the first metal interconnection layer.

2. The silicon bridge module of claim 1, wherein the capacitor is a deep trench capacitor disposed within a deep trench of the substrate, and the deep trench capacitor comprises a first electrode layer, a dielectric layer, and a second electrode layer, wherein the first electrode layer, and the second electrode layer are electrically connected to the first metal interconnect layer.

3. The silicon bridge module of claim 1, wherein the capacitor is a planar capacitor disposed on the surface of the first insulating layer and comprising a first electrode layer, a dielectric layer, and a second electrode layer, wherein the first electrode layer, and the second electrode layer are electrically connected to the first metal interconnect layer.

4. The silicon bridge module of claim 1, further comprising a through silicon via extending through the substrate and having a first end electrically connected to the first metal interconnect layer and a second end exposing a second surface of the substrate opposite the first surface.

5. The silicon bridge module of claim 4, further comprising a second metal interconnect layer disposed on the second surface of the substrate, including one or more layers of conductive traces and an insulating medium disposed between the conductive traces, the second end of the through silicon via being electrically connected to the second metal interconnect layer.

6. A method of manufacturing a silicon bridge module as defined in any one of claims 1 to 5, comprising the steps of:

depositing a first insulating layer on the surface of a silicon wafer, and forming a capacitor, wherein the capacitor comprises a first electrode layer, a dielectric layer and a second electrode layer;

depositing a second insulating layer on the surface of the second electrode layer, and windowing to lead out the first electrode layer and the second electrode layer;

forming a first metal interconnection layer on the surface of the second insulating layer, wherein the first metal interconnection layer comprises an inductance coil structure;

preparing an external bonding pad on the surface of the first metal interconnection layer; and

and thinning the back surface of the silicon wafer, and cutting to obtain a single silicon bridge.

7. The method of manufacturing of claim 6, wherein depositing the first insulating layer and forming the capacitor comprises the steps of:

etching a deep silicon groove on the first surface of the silicon wafer;

depositing a first insulating layer on the first surface of the silicon wafer and the surface of the deep silicon groove; and

and sequentially filling the first electrode, the dielectric material and the second electrode in the deep silicon groove.

8. The method of manufacturing of claim 6, wherein depositing the first insulating layer and forming the capacitor comprises the steps of:

depositing a first insulating layer on the surface of the silicon wafer;

preparing a first electrode layer and a part of circuits of a first metal interconnection layer on the surface of the first insulating layer;

depositing an intermediate insulating layer on the first electrode layer and the circuit surface, but exposing at least part of the surface of the first electrode layer to deposit a dielectric material;

windowing is carried out on the middle insulating layer so as to lead out the first electrode layer and an external bonding pad of a circuit; and

and forming a second electrode layer and a part of circuits of the first metal interconnection layer on the intermediate insulating layer.

9. The method of manufacturing of claim 6, further comprising the step of:

forming a through silicon via on the silicon wafer, wherein a first end of the through silicon via is electrically connected with the first metal interconnection layer; and/or

And grinding and thinning the second surface of the silicon wafer to enable the through silicon hole to be exposed, forming a second metal interconnection layer on the second surface of the silicon wafer, and electrically connecting the second end of the through silicon hole with the second metal interconnection layer.

10. A package structure comprising a silicon bridge module as claimed in any one of claims 1 to 5.