CN114566490B

CN114566490B - Vertical layout MSM capacitor structure and manufacturing method thereof

Info

Publication number: CN114566490B
Application number: CN202210075871.4A
Authority: CN
Inventors: 祁冬; 张睿; 张先荣; 王志辉; 朱勇
Original assignee: CETC 10 Research Institute
Current assignee: CETC 10 Research Institute
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2023-06-27
Anticipated expiration: 2042-04-15
Also published as: CN114566490A

Abstract

The vertical layout MSM capacitor structure and the manufacturing method thereof can be applied to various semiconductor integrated/packaging structures with small capacitance and miniaturization requirements. The dielectric layer of the capacitor is formed by vertically arranging MSM capacitor structure dielectric partition walls on the upper surface and the lower surface of the semiconductor dielectric substrate; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, the two metal electrode plates extend to two ends of the dielectric partition wall S1 through metal layer microstrip connection lines etched on the surface of the semiconductor dielectric substrate to form an electrode structure led out from the MSM capacitor leading-out ends L1 and L2, and therefore an MSM capacitor equivalent circuit structure with vertical layout is formed.

Description

Vertical layout MSM capacitor structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of microwave technology and wireless communication, in particular to an embedded integrated three-dimensional flat capacitor structure, which is particularly a vertical capacitor structure representing metal-semiconductor-metal (MSM), namely MSM=metal-semiconductor-metal, in semiconductor integrated/packaging structures which can be applied to various small capacity values and miniaturization requirements, and also relates to a manufacturing method of the MSM capacitor.

Background

In the current 2D/2.5D/3D integrated circuit/package design, capacitors with different capacitance and packages are widely applied to decoupling, bypass, blocking, resonance, energy storage and other functional links. The existing capacitor forms mainly comprise: 1) Electrolytic capacitors, tantalum capacitors, monolithic capacitors, ceramic chip capacitors and the like which are conventionally arranged on the surface of a plate or a package body; 2) A small-capacitance chip capacitor which is arranged in the cavity and is convenient for interconnection or gold wire bonding; 3) Z-direction stacked MIM capacitor or wafer level integrated capacitor based on three-dimensional stacked/packaged structure, such as low-temperature co-fired ceramic LTCC, high-temperature co-fired ceramic HTCC, printed circuit boardPCB, silicon-based interposer/MEMS stack, glass-based interposer/MEMS stack, etc.; 4) A vertically arranged metal-insulator-metal MIM capacitor. The type 1) capacitor shape aims at the traditional board-level circuit requirement; the 2 nd), 3) and 4) types of capacitor forms are mainly aimed at the requirements of three-dimensional packaging/three-dimensional integrated miniaturization design, such as system-in-package (SiP), system-on-chip (SoC), package antenna AiP and the like. However, the main contradiction of chip or module miniaturization compared to Z-direction extension is still concentrated on XY plane layout. Compared with the type 1) capacitor form, the type 2) and the type 3) capacitor forms can reduce the occupied area of the planar layout to a certain extent in the application field of small and medium capacitance values, improve the miniaturization performance, but the flat capacitance calculation formula

The size of the parallel metal plates/layers is limited, resulting in the inevitable contradiction between capacity expansion and miniaturization. While the 4 th metal-insulator-metal (MIM) capacitor configuration solves the contradiction between capacity expansion and miniaturization, the preparation and formation of the insulator (I) layer in the MIM structure tends to introduce additional processes and risks for the integrated three-dimensional integration technology based on semiconductors. Therefore, on the premise of ensuring that no additional material, preparation process and risk are introduced, the size of the XY plane layout of the capacitor is effectively reduced, and further, the requirements of circuit miniaturization and integrated high-performance integrated design are met, so that the method is a key technology to be broken through in the current urgent need.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides a vertical layout metal-semiconductor-metal MSM capacitor structure with a simple structure, which can effectively reduce the layout of XY plane dimensions, and an intermediate semiconductor medium can keep the high-precision design requirement of a capacitor on the basis of being compatible with the prior integrated three-dimensional integration process. For this reason, the invention also relates to a preparation method of the metal-semiconductor-metal MSM capacitor structure as described below.

The above object of the present invention can be achieved by a vertical layout MSM capacitor structure comprising: the multi-layer semiconductor medium substrate stacking structure is tightly attached to the surface of the semiconductor medium substrate, and the metal layers G1, G2, G1 and G2 which are not communicated with the capacitor electrode plates can be metal surfaces with any shapes and can be communicated with each other or not. The method is characterized in that: two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor medium substrate and are separated by a medium partition wall S1 are formed in a specific position of the semiconductor medium substrate, and the medium partition wall S1 forms a medium layer of a capacitor; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, the two metal electrode plates P1 and P2 extend to two ends of the dielectric partition wall S1 through metal layer microstrip connection lines etched on the surface of the semiconductor dielectric substrate to form an electrode structure led out from the MSM capacitor leading-out ends L1 and L2, wherein the L1 and the L2 can be positioned on the same surface or different surfaces of the semiconductor dielectric layer, and therefore the MSM capacitor equivalent circuit structure with vertical layout is formed.

The preparation method for manufacturing the vertical layout MSM capacitor structure is characterized by comprising the following steps: manufacturing two flat metalized through grooves, blind grooves or buried grooves which are parallel to each other and vertically arranged on the semiconductor medium substrate, and forming a medium partition wall S1 of an MSM capacitor insulating layer; etching the lead-out microstrip transmission lines of the capacitor lead-out ends on the upper/lower metal layers of the dielectric partition wall S1 according to the interconnection relation of the MSM capacitor structure in a vertical layout to form MSM capacitor lead-out ends L1 and L2, depositing an adhesion layer on the side walls and the bottoms of the flat metalized through grooves, the blind grooves or the buried grooves, and depositing a diffusion barrier layer on the side walls and the bottoms of the flat metalized through grooves, the blind grooves or the buried grooves; depositing a seed layer on the diffusion barrier layers on the side walls and the bottom of the flat metalized through groove, the blind groove or the buried groove; and electroplating filling metal in the groove which is subjected to seed layer deposition, and if the groove is a sidewall metallized hollow groove, not performing the electroplating filling operation.

Compared with the prior art, the invention has the following beneficial effects:

the invention aims at the inherent form and characteristic of an actual circuit/packaging substrate, two flat metalized through grooves, blind grooves or buried grooves which are vertical to the surface of a semiconductor medium substrate and are separated by a medium partition wall S1 are manufactured at specific positions of the semiconductor medium substrate, and the medium partition wall S1 is utilized to form a medium layer of a capacitor; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, and the two metal electrode plates P1 and P2 are led out to extend to two ends of the dielectric partition wall S1 through metal layer microstrip connecting lines etched on the surface of the semiconductor dielectric substrate to form a vertical layout MSM capacitor structure. In the field of small capacitance requirement, the integrated integration of embedded capacitor can be truly realized. In particular, other materials and processes besides interconnect metal and semiconductor dielectric substrate materials may not be introduced, achieving the beneficial objectives of cost reduction and risk control. The capacitor integrated/packaged structure solves the problems that capacitors in the existing semiconductor integrated/packaged structure cannot be integrated into a whole in three dimensions and the layout size in the XY direction is effectively reduced.

Drawings

FIG. 1 is a front view of a vertical layout MSM capacitor structure of the present invention;

FIG. 2 is a top view of FIG. 1;

FIG. 3 is a schematic diagram of a vertically-laid capacitive structure for a blind-slot plate in accordance with the present invention;

FIG. 4 is a schematic diagram of a single capacitor series interconnect structure;

FIG. 5 is a schematic diagram of a single capacitor parallel interconnect structure;

FIG. 6 is a schematic diagram of a dual capacitance series interconnect structure;

FIG. 7 is a schematic diagram of a dual capacitance parallel interconnect structure;

fig. 8 is a schematic diagram of a multi-layer stack structure of MSM capacitor structure example 5 of the present invention.

The objects, technical solutions and advantages of the present invention will become more apparent hereinafter, and the present invention will be further described in detail hereinafter with reference to the accompanying drawings.

Detailed Description

See fig. 1 and 2. In the exemplary preferred embodiment described below, a vertical layout MSM capacitive structure includes: the multi-layer semiconductor medium substrate stacking structure is tightly attached to the surface of the semiconductor medium substrate, and the metal layers G1, G2, G1 and G2 which are not communicated with the capacitor electrode plates can be metal surfaces with any shapes and can be communicated with each other or not. Two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor medium substrate and are separated by a medium partition wall S1 are formed in a specific position of the semiconductor medium substrate, and the medium partition wall S1 forms a medium layer of a capacitor; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, the two metal electrode plates P1 and P2 extend to two ends of the dielectric partition wall S1 through metal layer microstrip connection lines etched on the surface of the semiconductor dielectric substrate to form an electrode structure led out from the MSM capacitor leading-out ends L1 and L2, wherein the L1 and the L2 can be positioned on the same surface or different surfaces of the semiconductor dielectric layer, and therefore the MSM capacitor equivalent circuit structure with vertical layout is formed.

In an alternative embodiment, embodiment 1:

the two flat metalized through grooves, blind grooves or buried grooves of the vertical MSM capacitor body structure are in parallel, and the side walls of the flat metalized through grooves, blind grooves or buried grooves can be metalized hollow structures or metal fully-filled solid structures. The dielectric partition wall S1 may be a semiconductor dielectric layer sandwiched between two flat metallized through grooves, blind grooves or buried grooves and adjacent to the side walls, where the semiconductor dielectric layer and the semiconductor dielectric substrate are made of the same material, and are integrally connected with the capacitor lead-out terminal. L1 and L2 may be in the form of microstrip lines, striplines, coplanar waveguides, etc. transmission lines. The metal layers G1 and G2 that are not in communication with the capacitor plates may be used as ground or it may be used.

Example 2:

see fig. 3. The difference between this embodiment and embodiment 1 is that the two parallel grooves are buried grooves, i.e. one end of the grooves does not extend to communicate with the metal layer. This embodiment differs from the process step of embodiment 1 in that the process step of performing buried trench to via conversion using a backside CMP process may be omitted.

Example 3:

fig. 4 and 5 are schematic front views of the vertical metal-semiconductor-metal MSM capacitor structure in series and parallel in an actual circuit, i.e. as a demonstration of the actual layout usage of the capacitor structure. The series connection mode is characterized in that, as shown in embodiment 1, two capacitor leading-out ends are respectively connected to two parallel metal plate grooves, the two leading-out ends can be positioned on the same metal layer or on different upper and lower metal layers, and the ground end is not communicated with the two parallel metal plate grooves. The parallel connection mode is characterized in that the two capacitor leading-out ends are connected with one of the parallel metal polar plate grooves, the two leading-out ends can be positioned on the same metal layer or on different upper and lower metal layers, and the other parallel metal polar plate groove is connected with the ground end. This embodiment exemplifies the layout of a single vertical metal-semiconductor-metal MSM capacitor that functions as a blocking, filtering, resonating, etc. in an actual circuit.

Example 4:

fig. 6 and 7 are schematic front views of the two vertical metal-semiconductor-metal MSM capacitor structures connected in series and schematic top views connected in parallel in an actual circuit, i.e. as a display of the actual layout usage of the capacitor structures. The series interconnection mode is characterized in that two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure playing a role in mutual communication can be positioned on a metal layer at the top of the groove polar plate or on a metal layer at the bottom of the groove polar plate; the two leading-out terminals are connected with the grooves of the respective residual parallel metal polar plates, and can be positioned on the same metal layer or on upper and lower different metal layers. The parallel interconnection mode is characterized in that two capacitors are respectively provided with a parallel metal polar plate groove and are mutually communicated through a transmission structure, and the transmission structure playing a role in mutual communication can be positioned on a metal layer at the top of the groove polar plate or on a metal layer at the bottom of the groove polar plate; the two leading-out ends are respectively connected with the parallel metal polar plate grooves which are mutually communicated, and the two leading-out ends can be positioned on the same metal layer or can be positioned on upper and lower different metal layers. This embodiment exemplifies the layout of two or more vertical metal-semiconductor-metal MSM capacitors functioning as multi-stage filtering, parallel resonance, etc. in an actual circuit.

Example 5:

fig. 8 is a schematic diagram of a layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual multi-layer semiconductor dielectric stack, i.e., as a demonstration of the actual layout usage of the capacitor structure. The capacitor structure in this embodiment may be any of the layout and extraction patterns of embodiments 1 to 4, or may be any combination of the capacitor structures of embodiments 1 to 4. The single-layer structures can be stacked in a direct bonding or indirect bonding mode, and the number of layers (N1 is more than or equal to 0 or N2 is more than or equal to 0 and is an integer) is stacked up and down, and the stacking method comprises bonding processes such as hot-press bonding, eutectic bonding, solid-liquid diffusion bonding and the like. This embodiment exemplifies the morphological layout of the vertical metal-semiconductor-metal MSM capacitor structure in an actual integrated package design.

The present invention has been described in detail in the foregoing description with reference to specific embodiments, but is not to be construed as limiting the invention. Any modifications, equivalent substitutions, variations and improvements in the present invention may occur to those skilled in the art without departing from the spirit and principles of the invention, and are intended to be included within the scope of the present invention.

Claims

1. A vertically-laid out MSM capacitor structure, comprising: the multilayer semiconductor medium substrate stacking structure clings to the surface of the semiconductor medium substrate, and the metal layers G1, G2, G1 and G2 which are not communicated with the capacitor electrode plates are metal surfaces with any shape which are communicated or not communicated with each other, and the multilayer semiconductor medium substrate stacking structure is characterized in that: two flat metallized through grooves, blind grooves or buried grooves which are vertical to the surface of the semiconductor medium substrate and are separated by a medium partition wall S1 are formed in a specific position of the semiconductor medium substrate, and the medium partition wall S1 forms a medium layer of a capacitor; the two parallel rectangular through grooves, blind grooves or buried grooves are embedded with metal electrode plates P1 and P2 forming homoepitaxy of the capacitor body, the two metal electrode plates P1 and P2 extend to two ends of the dielectric partition wall S1 through metal layer microstrip connection lines etched on the surface of the semiconductor dielectric substrate to form an electrode structure led out from the MSM capacitor leading-out ends L1 and L2, wherein the L1 and the L2 are located on the same surface or different surfaces of the semiconductor dielectric layer, and therefore the MSM capacitor equivalent circuit structure with vertical layout is formed.

2. The vertical layout MSM capacitor structure of claim 1 wherein: the two flat metalized through grooves, blind grooves or buried grooves of the vertical MSM capacitor body structure are in parallel, and the side walls of the flat metalized through grooves, blind grooves or buried grooves are of a metalized hollow structure or a metal fully-filled solid structure.

3. The vertical layout MSM capacitor structure of claim 1 wherein: the dielectric partition wall S1 is a semiconductor dielectric layer clamped between two flat metalized through grooves, blind grooves or buried grooves and adjacent to the side walls, and the semiconductor dielectric layer and the semiconductor dielectric substrate are made of the same material and are integrally communicated with the capacitor leading-out end.

4. The vertical layout MSM capacitor structure of claim 1 wherein: l1 and L2 are microstrip lines, strip lines, coplanar waveguide transmission lines, and metal layers G1 and G2, which are not in communication with the capacitor plates, serve as grounds.

5. The vertical layout MSM capacitor structure of claim 1 wherein: the two grooves which are parallel to each other are buried grooves, and one end of each groove is not extended to be communicated with the metal layer.

6. The vertical layout MSM capacitor structure of claim 1 wherein: the two capacitor leading-out ends are respectively connected to the two parallel metal polar plate grooves, the two leading-out ends are positioned on the same metal layer or on upper and lower different metal layers, and the ground end is not communicated with the two parallel metal polar plate grooves: the two capacitor lead-out terminals are connected with one parallel metal polar plate groove, and the other parallel metal polar plate groove is connected with the ground terminal.

7. The vertical layout MSM capacitor structure of claim 1 wherein: the two capacitors are respectively provided with a parallel metal polar plate groove, and are mutually communicated through a transmission structure, and the transmission structure playing a role of mutual communication is positioned on a metal layer at the top of the groove polar plate or a metal layer at the bottom of the groove polar plate; the two leading-out terminals are connected with the grooves of the respective residual parallel metal polar plates and are positioned on the same metal layer or on the upper and lower different metal layers.

8. The vertical layout MSM capacitor structure of claim 1 wherein: the two capacitors are respectively provided with a parallel metal polar plate groove, and are mutually communicated through a transmission structure, and the transmission structure playing a role of mutual communication is positioned on a metal layer at the top of the groove polar plate or a metal layer at the bottom of the groove polar plate; the two leading-out ends are respectively connected with the parallel metal polar plate grooves which are mutually communicated, and the two leading-out ends can be positioned on the same metal layer or on upper and lower different metal layers.

9. The vertical layout MSM capacitor structure of claim 1 wherein: the capacitor structure is stacked in any structural layout and extraction form or any mutual combination form of the capacitor structures, each single-layer structure is stacked in a direct bonding or indirect bonding mode, the number of layers N1 of the upper and lower stacking layers is more than or equal to 0 or N2 of the lower stacking layers is more than or equal to 0, and the whole number is taken, and the stacking method comprises hot-press bonding, eutectic bonding and solid-liquid diffusion bonding processes.

10. A method of making the vertical layout MSM capacitor structure of claim 1, comprising the steps of: manufacturing two flat metalized through grooves, blind grooves or buried grooves which are parallel to each other and vertically arranged on the semiconductor medium substrate, and forming a medium partition wall S1 of an MSM capacitor insulating layer; etching the lead-out microstrip transmission lines of the capacitor lead-out ends on the upper/lower metal layers of the dielectric partition wall S1 according to the interconnection relation of the MSM capacitor structure in a vertical layout to form MSM capacitor lead-out ends L1 and L2, depositing an adhesion layer on the side walls and the bottoms of the flat metalized through grooves, the blind grooves or the buried grooves, and depositing a diffusion barrier layer on the side walls and the bottoms of the flat metalized through grooves, the blind grooves or the buried grooves; depositing a seed layer on the diffusion barrier layers on the side walls and the bottom of the flat metalized through groove, the blind groove or the buried groove; and electroplating filling metal in the groove which is subjected to seed layer deposition, and if the groove is a sidewall metallized hollow groove, not performing the electroplating filling operation.