CN218939447U - 3D-silicon-based capacitor bank - Google Patents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
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Abstract
The utility model discloses a 3D-silicon-based capacitor bank, which comprises at least two capacitor bodies, wherein when the capacitor bank comprises two capacitor bodies, the two capacitor bodies are connected in series or in parallel through a conductive bonding layer to form the 3D-silicon-based capacitor bank; when the capacitor comprises more than two capacitor bodies, a plurality of capacitor bodies are connected in parallel through electrodes to form a 3D-silicon-based capacitor bank, and the capacitor bodies are connected through an insulating layer. The utility model has the beneficial effects that the capacitors are connected in parallel or in series to form a 3D-silicon-based capacitor structure through bonding layers or electrodes according to the structures of different capacitors and the specification number of different capacitors, so that the constructed 3D-silicon-based capacitor has large capacity and high voltage resistance.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a 3D-silicon-based capacitor bank.
Background
The 3D silicon-based capacitor is an ultra-stable and high-capacity density capacitor device prepared on a silicon-based substrate by applying a micro-nano technology. Etching a high depth-to-width ratio groove on a silicon substrate by adopting a deep silicon etching technology so as to increase the alignment area of an electrode of a device, thereby realizing high capacity density, and the silicon substrate is generally used as a bottom electrode of the silicon-based capacitor; the dielectric layer is grown by adopting LPCVD, ALD and other technologies, and the dielectric layer generally has the characteristics of excellent dielectric property, small dielectric loss, small leakage current and the like; the top electrode generally adopts LPCVD, ALD and other technologies to grow polysilicon, tiN, metal Pt, W and the like; the external electrode is generally prepared by adopting sputtering and electroplating technology, the internal electrode is led out, the external electrode is patterned, and proper external electrode arrangement is designed according to the functional requirement of the capacitor. Similar to the structure of a multilayer ceramic capacitor (MLCC), a LPCVD or ALD method is adopted to grow a multilayer medium and an inner electrode film, the inner electrode and the medium film are overlapped in a dislocation mode by utilizing a micro-assembly technology to form an intercalation structure, and the inner electrode is led out to form the 3D silicon-based capacitor with the multilayer structure.
Conventionally, in the process of manufacturing a capacitor, on the one hand, an LPCVD (low pressure chemical vapor deposition) or ALD (atomic layer deposition) method is generally adopted for growth, and in order to obtain a higher capacity area ratio, the smaller the line width of a deep silicon groove is, the better; on the other hand, according to the calculation formula of the capacitance, the smaller the thickness of the dielectric film, the larger the capacity, and in addition, the larger the capacity density of the silicon-based capacitor, the characteristic size is generally smaller, and the whole capacity is still smaller compared with the traditional MLCC. However, in the conventional 3D silicon-based capacitor, the dielectric layer has a relatively thin film, resulting in a relatively low withstand voltage level and capacity.
In view of this, the present application is specifically proposed.
Disclosure of Invention
The utility model aims to solve the technical problems that in the prior art, a dielectric layer film in a capacitor is thinner, so that the voltage-resistant level difference and the capacity are low, and the utility model aims to provide a 3D-silicon-based capacitor bank which can enable the capacity of the capacitor to be large and resist high voltage.
The utility model is realized by the following technical scheme:
the 3D-silicon-based capacitor bank comprises two capacitor bodies, wherein the two capacitor bodies are connected in series or in parallel through a conductive bonding layer (6) to form the 3D-silicon-based capacitor bank; or alternatively, the process may be performed,
the capacitor comprises at least three capacitor bodies, wherein a plurality of capacitor bodies are connected in parallel through electrodes to form a 3D-silicon-based capacitor bank, and the capacitor bodies are connected through an insulating layer.
In the conventional capacitor, on the one hand, the LPCVD or ALD method is generally adopted for growth, and in order to obtain higher capacity area ratio, the smaller the line width of the deep silicon groove is, the better; on the other hand, according to the calculation formula of the capacitance, the smaller the thickness of the dielectric film is, the larger the capacity is, in addition, the larger the capacity density of the silicon-based capacitor is, but the characteristic dimension is generally smaller, the whole capacity is still smaller compared with that of the traditional MLCC, but in the capacitor prepared by adopting the method, the voltage-resistant level difference and the capacity are low due to the fact that the dielectric layer is thinner, the 3D-silicon-based capacitor bank is provided, and according to the structures of different capacitors and the specification number of different capacitors, the capacitor is connected in parallel or in series with one 3D-silicon-based capacitor structure through the bonding layer or the electrode, so that the capacity of the constructed 3D-silicon-based capacitor is large and high voltage resistant.
Preferably, when the two capacitor bodies are connected in series through the conductive adhesive layer to form the 3D-silicon-based capacitor group, the capacitor bodies are capacitor bodies with a single-layer upper and lower electrode structure, and the lower electrodes of the two capacitor bodies are connected in series through the conductive adhesive layer.
Preferably, the capacitor body includes a lower electrode layer, a substrate layer, a dielectric layer, an inner electrode layer and an upper electrode layer, wherein the substrate layer, the dielectric layer, the inner electrode layer and the upper electrode layer are sequentially grown on the lower electrode layer, and the upper electrode layer is integrally covered on the inner electrode layer.
Preferably, when the two capacitor bodies are connected in parallel through the conductive adhesive layer to form a 3D-silicon-based capacitor group, the capacitor bodies are capacitor bodies with a multi-layer left-right electrode structure, and the corresponding left-right electrodes of the two capacitor bodies are connected in parallel through the conductive adhesive layer.
Preferably, when at least three capacitor bodies are connected in parallel through the upper electrode layer to form a 3D-silicon-based capacitor bank, the capacitor bodies are capacitor bodies with a multi-layer left-right electrode structure, the capacitor bodies are stacked, two capacitor bodies are connected through an insulating layer, and the left electrode and the right electrode of the plurality of capacitor bodies are respectively connected.
Preferably, the capacitor body comprises a lower electrode layer, a silicon substrate layer, an inner electrode layer, a dielectric layer and two upper electrode layers, wherein the silicon substrate layer grows on the lower electrode layer, the dielectric layer and the inner electrode layer are of multi-layer structures, the dielectric layer and the inner electrode layer are overlapped in a staggered manner, an intercalation structure is formed on the silicon substrate layer, and the two upper electrode layers grow at two ends of the inner electrode layer respectively.
Preferably, the insulating layer is an epoxy layer, a polyester layer, a fluoropolymer layer or a photoresist layer.
Preferably, the conductive adhesive layer is a conductive adhesive layer or a metal layer.
Preferably, the thickness of the conductive adhesive layer ranges from 1um to 100um.
Preferably, the metal layer material is Au or AuSn or Cu or Ti or Ni.
Compared with the prior art, the utility model has the following advantages and beneficial effects:
according to the 3D-silicon-based capacitor group provided by the embodiment of the utility model, the capacitors are connected in parallel or in series to form a 3D-silicon-based capacitor structure through the bonding layers or the electrodes according to the structures of different capacitors and the specification numbers of different capacitors, so that the constructed 3D-silicon-based capacitor has large capacity and high voltage resistance.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present utility model, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present utility model and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a series capacitor structure;
FIG. 2 is a schematic diagram of a parallel capacitor structure;
fig. 3 is a schematic diagram of a parallel capacitor structure.
Reference numerals:
1. an inner electrode layer; 2. an upper electrode layer; 3. a dielectric layer; 4. a substrate layer; 5. a lower electrode layer; 6. a conductive adhesive layer; 7. an insulating layer.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present utility model, the present utility model will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present utility model and the descriptions thereof are for illustrating the present utility model only and are not to be construed as limiting the present utility model.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the utility model. In other instances, well-known structures, circuits, materials, or methods have not been described in detail in order not to obscure the utility model.
Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the utility model. Thus, the appearances of the phrases "in one embodiment," "in an example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the description of the present utility model, the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present utility model and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the scope of the present utility model.
In the conventional capacitor, on the one hand, the LPCVD or ALD method is generally adopted for growth, and in order to obtain higher capacity area ratio, the smaller the line width of the deep silicon groove is, the better; on the other hand, according to the calculation formula of the capacitance, the smaller the thickness of the dielectric film, the larger the capacity, and in addition, the larger the capacity density of the silicon-based capacitor, the characteristic size is generally smaller, the whole capacity is still smaller compared with the traditional MLCC, but in the capacitor prepared by adopting the method, the dielectric layer 3 is thinner, so that the voltage-resistant level difference and the capacity are low,
the embodiment provides a 3D-silicon-based capacitor group, according to structures of different capacitors and specification numbers of different capacitors, the capacitors are connected in parallel or in series to form a 3D-silicon-based capacitor structure through bonding layers or electrodes, so that the capacity of the constructed 3D-silicon-based capacitor is large and high voltage resistance is achieved. The specific structure is shown in figures 1-3, and comprises two capacitor bodies, wherein the two capacitor bodies are connected in series or in parallel through a conductive bonding layer (6) to form a 3D-silicon-based capacitor bank; or alternatively, the process may be performed,
the capacitor comprises at least three capacitor bodies, wherein a plurality of capacitor bodies are connected in parallel through electrodes to form a 3D-silicon-based capacitor bank, and the capacitor bodies are connected through an insulating layer.
In this embodiment, thanks to the conventional multi-core capacitor manufacturing concept, it is considered to stack and connect the 3D silicon-based capacitor into a complete capacitor according to the multi-core capacitor stack. In the multi-core group capacitor, the outer electrodes of the chip capacitors are arranged at the left end and the right end of the chip, the left and the right outer electrodes of the chip capacitors are welded and integrated into an integral capacitor through the bracket, and the bracket is a wire for linking the chip capacitors, so that the structural stability of the capacitor group is ensured.
The external electrode of the 3D silicon-based capacitor is not arranged on the side surface of the chip, so that the 3D silicon-based capacitor cannot be integrated in a welding mode of the multi-core group chip capacitor, therefore, the bonding integration of the multi-layer 3D silicon-based capacitor through the wafer bonding process is referred to by combining the wafer bonding process and the TSV process, the parallel connection and series connection functions among different silicon-based capacitors are realized through the TSV process, and the capacity density and the compressive strength of the 3D silicon-based capacitor are improved.
When two capacitor bodies are connected in series through the conductive adhesive layer 6 to form a 3D-silicon-based capacitor bank, the capacitor bodies are capacitor bodies with a single-layer upper electrode structure and a single-layer lower electrode structure, and the lower electrodes of the two capacitor bodies are connected in series through the conductive adhesive layer 6, the specific structure is shown in figure 1, the capacitor bodies comprise a lower electrode layer 5, a substrate layer 4, a dielectric layer 3, an inner electrode layer 1 and an upper electrode layer 2, the substrate layer 4, the dielectric layer 3, the inner electrode layer 1 and the upper electrode layer 2 are sequentially grown on the lower electrode layer 5, and the upper electrode layer 2 is integrally covered on the inner electrode layer 1.
In the preparation process of the silicon-based capacitor, the high-conductivity silicon substrate layer 4 has the resistivity less than 0.01 omega cm, the substrate layer 4 needs to be polished on two sides, and the thickness of the substrate is 100-250 mu m; the deep silicon etching line width is 1-4 μm, the etching depth is 40-200 μm, and the dielectric can be ONO dielectric, aluminum oxide, hafnium oxide or any combination of the above.
The conductive bonding can be conductive adhesive, or a material which can be subjected to covalent welding such as Au, auSn, cu, ti, ni can be selected as an electrode when the bottom metal electrode is prepared; in the bonding process, the welding process can be finished by adopting modes of hot press bonding, eutectic bonding, self-propagating reaction welding of nano thin foil and the like.
In the embodiment, the adopted silicon substrate layer 4 has the resistivity of 0.0005 ohm cm, the double-sided polishing of the substrate and the thickness of 100 mu m, the surface of the silicon substrate layer 4 is processed by a silicon-based capacitor, the width of deep silicon etching lines on the upper electrode structure and the lower electrode structure is 2 mu m, the etching depth is 80 mu m, the medium adopts alumina, the product size is 2020, and the back surface is prepared by an AuSn electrode; reserving a subsequent alignment mark when the obtained capacitor body is prepared, photoetching the reserved alignment mark, and adopting a deep silicon etching technology to mark the position; and aligning the back surfaces of the two capacitor bodies, compacting, and ensuring that the alignment accuracy error is not more than 10 mu m. Then heating the substrate to 320+/-10 ℃ for 20s, cooling, and bonding the two substrate edges together; and cutting and sealing the bonded substrate. The final capacitor bank had a capacity of 5nF and a breakdown voltage of 100V.
The capacitor body comprises a lower electrode layer 5, a silicon substrate layer 4, an inner electrode layer 1, a dielectric layer 3 and two upper electrode layers 2, wherein the silicon substrate layer 4 is grown on the lower electrode layer 5, the dielectric layer 3 and the inner electrode layer 1 are of a multi-layer structure, the dielectric layer 3 and the inner electrode layer 1 are staggered and overlapped to form an intercalation structure, the intercalation structure is grown on the silicon substrate layer 4, and the two upper electrode layers 2 are respectively grown at two ends of the inner electrode layer 1. When the capacitor body is of a multilayer left-right electrode structure, two or more capacitors can be connected in parallel, and the specific structure of the parallel connection is as follows:
when two capacitor bodies are connected in parallel through the conductive adhesive layer 6 to form a 3D-silicon-based capacitor bank, the capacitor bodies are capacitor bodies with a multi-layer left-right electrode structure, and the corresponding left-right electrodes of the two capacitor bodies are connected in parallel through the conductive adhesive layer 6, as shown in fig. 2.
In the preparation process of the silicon-based capacitor, the high-conductivity silicon substrate, N type and P type can be adopted, the resistivity is less than 0.01 omega cm, the substrate needs to be polished on two sides, and the thickness of the substrate is 100-250 mu m; the deep silicon etching line width is 1-4 μm, the etching depth is 40-200 μm, and the dielectric can be ONO dielectric, aluminum oxide, hafnium oxide or any combination of the above.
The adhesive can be conductive adhesive, or a material which can be subjected to covalent welding such as Au, auSn, cu, ti, ni can be selected as an electrode when the bottom metal electrode is prepared; in the bonding process, the welding can be finished by adopting modes of hot press bonding, eutectic bonding, self-propagating reaction welding of nano thin foil and the like.
The silicon substrate adopted in the embodiment has resistivity of 0.0005 Ω cm, the substrate is polished on both sides, and the thickness of the substrate is 120 μm; the left electrode of the product is designed to be in communication with the substrate base. The width of the deep silicon etched line is 2 mu m, the etching depth is 80 mu m, the medium adopts hafnium oxide, and the product size is 2040. The final capacitor had a single capacity of 50nF and a breakdown voltage of 50V. AuSn is adopted for the left electrode and the right electrode of the silicon-based capacitor. Reserving a subsequent alignment mark when the silicon-based capacitor is prepared, photoetching the reserved alignment mark, and punching the mark position by adopting a deep silicon etching technology; the two substrates are aligned and pressed in the mode of figure 2, and the alignment precision error is not more than 5 mu m. Then heating the substrate to 320+/-10 ℃ for 20s, cooling, and bonding the two substrate edges together; and cutting and sealing the bonded substrate. The single product capacity of the final parallel capacitor bank was 100nF and the breakdown voltage was 50V.
When at least three capacitor bodies are connected in parallel through the upper electrode layer 2 to form a 3D-silicon-based capacitor bank, the capacitor bodies are of a multi-layer left-right electrode structure, the capacitor bodies are stacked, two capacitor bodies are connected through an insulating layer, and the left electrodes and the right electrodes of the capacitor bodies are connected.
Through the TSV technology, a plurality of capacitors can be welded together to form a plurality of capacitors with parallel structures, and the following diagram is a schematic diagram of 3 multi-layer 3D silicon-based capacitors after being connected in parallel. In this design, it should be noted that, first, in order to avoid short circuit caused by conduction of the silicon substrate, a high-resistance silicon wafer is selected, as shown in fig. 3;
two multi-layer chip capacitors are connected in parallel. When the parallel capacitor is manufactured, the two left and right electrodes are aligned by utilizing a chip alignment process in a TSV process, and the accuracy of electrode alignment is directly related to the final reliability of the capacitor. After the electrodes are aligned, the chips are welded together by using adhesive or solder, so that the two chips form a parallel structure.
The insulating layer is made of non-conductive materials such as epoxy resin, polyester, fluorine-containing polymer, photoresist, etc.; in the bonding process, hot pressing, baking and other processes can be adopted;
in the embodiment, the adopted silicon substrate layer 4 is an intrinsic monocrystalline silicon wafer, the resistivity is more than 104 omega cm, the substrate needs to be polished on two sides, and the thickness of the substrate is 100 mu m-250 mu m; the width of the deep silicon etching line is 1-4 mu m, the etching depth is 40-200 mu m, and the medium can be ONO medium, aluminum oxide, hafnium oxide or any combination of the above; in the bonding process, the welding can be finished by adopting modes such as hot-press bonding and the like.
And processing a silicon-based capacitor on the surface of the silicon wafer, wherein the structure of the silicon-based capacitor is of a left electrode structure and a right electrode structure. The width of the deep silicon etched line is 2 mu m, the etching depth is 80 mu m, the medium adopts hafnium oxide, and the product size is 2040. The single capacity of the final capacitor is 50nF, and the breakdown voltage is 50V; the deep silicon etching technology etches the substrate downwards at the edges of the left electrode and the right electrode of the capacitor and simultaneously reserves the subsequent alignment mark; aligning and bonding the 3 substrates, wherein the bonding agent adopts epoxy resin, and the bonding process is that the baking is carried out for 5min at 180 ℃; filling conductive material Cu into the through silicon via by adopting a TSV process, so that electrodes of the capacitor are interconnected and form a parallel structure; cutting and sealing. The individual capacity of the final capacitor bank was 150nF and the breakdown voltage was 50V.
The external electrode of the 3D silicon-based capacitor is not arranged on the side surface of the chip, so that the 3D silicon-based capacitor cannot be integrated in a welding mode of the multi-core group chip capacitor, therefore, the bonding integration of the multi-layer 3D silicon-based capacitor through the wafer bonding process is referred to by combining the wafer bonding process and the TSV process, the parallel connection and series connection functions among different silicon-based capacitors are realized through the TSV process, and the capacity density and the compressive strength of the 3D silicon-based capacitor are improved.
The embodiment provides a 3D-silicon-based capacitor group, according to structures of different capacitors and specification numbers of different capacitors, the capacitors are connected in parallel or in series to form a 3D-silicon-based capacitor structure through bonding layers or electrodes, so that the capacity of the constructed 3D-silicon-based capacitor is large, the 3D-silicon-based capacitor is high-voltage-resistant, the stability of the 3D-silicon-based capacitor in the use process is improved, and the defects of signal delay, large noise or large driving power and the like caused by connecting the capacitors in series or in parallel can be avoided; when a plurality of capacitors are connected in parallel or in series to form a capacitor bank, the installation area is reduced, the process for preparing the capacitor bank is stable, and the prepared product has higher consistency.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the utility model, and is not meant to limit the scope of the utility model, but to limit the utility model to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the utility model are intended to be included within the scope of the utility model.
Claims (10)
1. The 3D-silicon-based capacitor bank is characterized by comprising two capacitor bodies, wherein the two capacitor bodies are connected in series or in parallel through a conductive bonding layer (6) to form the 3D-silicon-based capacitor bank; or alternatively, the process may be performed,
the capacitor comprises at least three capacitor bodies, wherein a plurality of capacitor bodies are connected in parallel through electrodes to form a 3D-silicon-based capacitor bank, and the capacitor bodies are connected through an insulating layer.
2. A 3D-silicon based capacitor bank according to claim 1, characterized in that when two of the capacitor bodies are connected in series by means of an electrically conductive adhesive layer (6) to form a 3D-silicon based capacitor bank, the capacitor bodies are capacitor bodies of a single-layer upper and lower electrode structure, and the lower electrodes of the two capacitor bodies are connected in series by means of an electrically conductive adhesive layer (6).
3. A 3D-silicon based capacitor bank according to claim 2, characterized in that the capacitor body comprises a lower electrode layer (5), a substrate layer (4), a dielectric layer (3), an inner electrode layer (1) and an upper electrode layer (2), the substrate layer (4), the dielectric layer (3), the inner electrode layer (1) and the upper electrode layer (2) are grown on the lower electrode layer (5) in sequence, and the upper electrode layer (2) is entirely covered on the inner electrode layer (1).
4. A 3D-silicon based capacitor bank according to claim 1, characterized in that when two capacitor bodies are connected in parallel by means of a conductive adhesive layer (6) to form a 3D-silicon based capacitor bank, the capacitor bodies are capacitor bodies of a multilayer left-right electrode structure, and the corresponding left-right electrodes of the two capacitor bodies are connected in parallel by means of the conductive adhesive layer (6).
5. A 3D-silicon-based capacitor bank according to claim 1, wherein when at least three capacitor bodies are connected in parallel by an upper electrode layer (2) to form the 3D-silicon-based capacitor bank, the capacitor bodies are capacitor bodies of a multi-layer left-right electrode structure, and the capacitor bodies are stacked, two capacitor bodies are connected by an insulating layer, and left-right electrodes of a plurality of capacitor bodies are connected.
6. A 3D-silicon-based capacitor bank according to claim 4 or 5, characterized in that the capacitor body comprises a lower electrode layer (5), a silicon substrate layer (4), an inner electrode layer (1), a dielectric layer (3) and two upper electrode layers (2), wherein the silicon substrate layer (4) is grown on the lower electrode layer (5), the dielectric layer (3) and the inner electrode layer (1) are both in a multi-layer structure, the dielectric layer (3) and the inner electrode layer (1) are in staggered superposition to form an intercalation structure on the silicon substrate layer (4), and the two upper electrode layers (2) are respectively grown at two ends of the inner electrode layer (1).
7. A 3D-silicon based capacitor bank according to claim 6, wherein the insulating layer is an epoxy layer, a polyester layer, a fluoropolymer layer or a photoresist layer.
8. A 3D-silicon based capacitor bank according to claim 3, characterized in that the conductive adhesive layer (6) is a conductive glue layer or a metal layer.
9. A 3D-silicon based capacitor bank according to claim 8, characterized in that the thickness of the conductive adhesive layer (6) is in the range of 1um to 100um.
10. A 3D-silicon based capacitor bank according to claim 9, wherein the metal layer material is Au or AuSn or Cu or Ti or Ni.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222511565.9U CN218939447U (en) | 2022-09-22 | 2022-09-22 | 3D-silicon-based capacitor bank |
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| CN116666382A (en) * | 2023-07-26 | 2023-08-29 | 湖北三维半导体集成创新中心有限责任公司 | Semiconductor structure and preparation method thereof |
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