CN116666382A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN116666382A
CN116666382A CN202310928764.6A CN202310928764A CN116666382A CN 116666382 A CN116666382 A CN 116666382A CN 202310928764 A CN202310928764 A CN 202310928764A CN 116666382 A CN116666382 A CN 116666382A
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CN
China
Prior art keywords
layer
substrate
forming
capacitor structure
trench
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CN202310928764.6A
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Chinese (zh)
Inventor
曹瑞霞
胡杏
李琳瑜
程翠
陈闰鹏
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Hubei 3d Semiconductor Integrated Innovation Center Co ltd
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Hubei 3d Semiconductor Integrated Innovation Center Co ltd
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Priority to CN202310928764.6A priority Critical patent/CN116666382A/en
Publication of CN116666382A publication Critical patent/CN116666382A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology

Abstract

The application relates to the field of semiconductor integrated circuits, and in particular provides a semiconductor structure and a preparation method thereof, wherein the capacitance density of a deep trench capacitor cannot be effectively improved at present, and the semiconductor structure comprises: a substrate including a first surface and a second surface disposed opposite along a first direction; the first capacitor structure is arranged on the first surface and extends towards the inside of the substrate along the first direction; the second capacitor structure is arranged on the second surface and extends towards the inside of the substrate along the first direction; the first capacitor structure and the second capacitor structure are symmetrically arranged; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitance structures in the first direction. In this way, the capacitance density per unit area of the semiconductor structure can be increased, thereby enabling the semiconductor structure to be used in a variety of different scenarios.

Description

Semiconductor structure and preparation method thereof
Technical Field
The present application relates to the field of semiconductor integrated circuits, and more particularly, to a semiconductor structure and a method for manufacturing the same.
Background
With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is continuously improved and simultaneously, the semiconductor devices are also developed towards miniaturization and microminiaturization. Deep trench capacitors (Deep Trench Capacitor, DTCs) are important building blocks in integrated circuits, but the capacitance of deep trench capacitors currently cannot support the requirements of high performance computing chips. Moreover, the current methods for increasing the capacitance density of deep trench capacitors are limited in size and process capability. Therefore, it is highly desirable to increase the capacitance density per unit area of deep trench capacitors.
Disclosure of Invention
The application provides a semiconductor structure and a preparation method thereof.
The technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a semiconductor structure, including:
a substrate including a first surface and a second surface disposed opposite in a first direction;
the first capacitor structure is arranged on the first surface and extends towards the inside of the substrate along the first direction;
the second capacitor structure is arranged on the second surface and extends towards the inside of the substrate along the first direction;
the first capacitor structure and the second capacitor structure are symmetrically arranged, and the symmetry planes of the first capacitor structure and the second capacitor structure are perpendicular to the first direction; the first direction is the thickness direction of the substrate; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitive structures in the first direction.
In some embodiments, the semiconductor structure further comprises a first redistribution layer and a second redistribution layer;
the first rewiring layer is arranged on the first surface and is electrically connected with the first capacitor structure;
The second redistribution layer is disposed on the second surface and electrically connected to the second capacitor structure.
In some embodiments, the semiconductor structure further includes a through silicon via penetrating the substrate;
the through silicon via is electrically connected with the first and second redistribution layers.
In some embodiments, the first capacitive structure comprises:
at least one first groove arranged on the first surface and extending towards the inside of the substrate;
a first stacked layer covering an inner surface of the first trench; the first stacked layer comprises at least two first electrode layers and at least a first dielectric layer positioned between the first electrode layers;
a first sealing layer covering the surface of the first stacked layer and the top of the first trench; a first gap is formed between the first sealing layer and the first stacking layer in the first groove.
In some embodiments, the second capacitive structure comprises:
at least one second groove arranged on the second surface and extending towards the inside of the substrate;
a second stacked layer covering an inner surface of the second trench; the second stacked layer comprises at least two second electrode layers and at least a second dielectric layer positioned between the second electrode layers;
A second sealing layer covering the surface of the second stacked layer and the top of the second trench; a second gap is provided between the second sealing layer and the second stacking layer in the second trench.
In some embodiments, the aspect ratio of the first trench and the second trench is greater than or equal to 20:1.
In some embodiments, the semiconductor structure further comprises a first pad and a second pad;
the first bonding pad is arranged on the first surface and is electrically connected with the first rewiring layer;
the second bonding pad is arranged on the second surface and is electrically connected with the second rewiring layer.
In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, where the method includes:
providing a substrate comprising a first surface and a second surface disposed opposite along a first direction;
forming a first capacitor structure on the first surface extending along the first direction inside the substrate;
forming a second capacitor structure on the second surface extending along the first direction inside the substrate;
the first capacitor structure and the second capacitor structure are symmetrically arranged, and the symmetry planes of the first capacitor structure and the second capacitor structure are perpendicular to the first direction; the first direction is the thickness direction of the substrate; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitive structures in the first direction.
In some embodiments, after forming the first capacitance structure, the method further comprises:
and forming a first rewiring layer electrically connected with the first capacitor structure on the first surface.
In some embodiments, after forming the second capacitance structure, the method further comprises:
forming a second redistribution layer on the second surface electrically connected to the second capacitance structure;
forming a second pad electrically connected to the second redistribution layer on the second surface;
and forming a first bonding pad electrically connected with the first rewiring layer on the first surface.
In some embodiments, after forming the second capacitance structure and before forming the second redistribution layer, the method further comprises:
forming a through silicon via penetrating through the substrate; the through silicon via is electrically connected with the first and second redistribution layers.
In some embodiments, forming a first capacitive structure on the first surface extending inward of the substrate, comprising:
forming at least one first trench in the first surface;
forming a first stacked layer on the inner surface of the first groove; the first stacked layer comprises at least two first electrode layers and at least a first dielectric layer positioned between the first electrode layers;
Forming a first sealing layer at least on the surface of the first stacking layer and the top of the first groove; a first gap is formed between the first sealing layer and the first stacking layer in the first groove.
In some embodiments, forming a second capacitive structure on the second surface extending inward of the substrate, comprising:
forming at least one second groove on the second surface;
forming a second stacked layer on the inner surface of the second groove; the second stacked layer comprises at least two second electrode layers and at least a second dielectric layer positioned between the second electrode layers;
forming a second sealing layer at least on the surface of the second stacking layer and the top of the second groove; a second gap is provided between the second sealing layer and the second stacking layer in the second trench.
In some embodiments, the providing a substrate comprises:
providing an initial substrate; the initial substrate includes the first surface and the second surface disposed opposite along a first direction;
and after the first capacitor structure is formed, thinning the initial substrate along the second surface to form the substrate.
The embodiment of the application provides a semiconductor structure and a preparation method, wherein the semiconductor structure comprises the following steps: a substrate, a first capacitance structure and a second capacitance structure; the substrate includes a first surface and a second surface disposed opposite along a first direction; the first capacitor structure and the second capacitor structure are respectively arranged on the first surface and the second surface; the first capacitor structure and the second capacitor structure are symmetrically arranged; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitance structures in the first direction. Because the semiconductor structure comprises the second capacitance structure which is arranged opposite to the first capacitance structure, the capacitance density in the unit area of the semiconductor structure can be improved, and the semiconductor structure can be applied to a plurality of different scenes.
Drawings
FIG. 1 is a schematic diagram of a semiconductor package structure;
fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 3 is a schematic diagram of a semiconductor structure according to an embodiment of the present application in a manufacturing process;
fig. 4 is a schematic diagram of a second structure in the process of manufacturing a semiconductor structure according to an embodiment of the present application;
Fig. 5 is a schematic diagram III of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 6 is a schematic diagram of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 7 is a schematic diagram of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 8 is a schematic diagram of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 9 is a schematic diagram seventh in the process of manufacturing a semiconductor structure according to an embodiment of the present application;
fig. 10 is a schematic structural diagram eight in a semiconductor structure manufacturing process according to an embodiment of the present application;
fig. 11 is a schematic diagram of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 12 is a schematic diagram of a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 13 is a schematic diagram eleven in a semiconductor structure manufacturing process according to an embodiment of the present application;
fig. 14 is a schematic diagram showing a semiconductor structure in a manufacturing process according to an embodiment of the present application;
fig. 15 is a schematic diagram of thirteenth structure in a semiconductor structure manufacturing process according to an embodiment of the present application;
Fig. 16 is a schematic diagram fourteen structures in a semiconductor structure manufacturing process according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
It should be noted that the term "first/second/third" in relation to embodiments of the present application is merely used to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if allowed, to enable embodiments of the present application described herein to be implemented in an order other than that illustrated or described herein.
Currently, with the continuous progress of semiconductor integrated circuit manufacturing technology, the performance of semiconductor devices is continuously improved, and along with the miniaturization and miniaturization of semiconductor devices, there is a demand for disposing as many semiconductor devices as possible in a certain area.
The capacitor is used as an important component unit in an integrated circuit and is widely applied to chips such as memories, microwaves, radio frequencies, smart cards, high voltage and filtering. With the reduction of chip size and the demand for large capacitance in performance, how to obtain high density capacitance in a limited area is a very attractive issue.
In order to obtain higher capacitance density per unit area, three methods are generally adopted, but have certain limitations, one of the methods is to adopt a dielectric material with higher dielectric constant to improve the capacitance density, the currently available dielectric material in the method is limited, and the method can be combined with the existing technology, namely, the method for changing the high dielectric constant material has limited lifting space; secondly, the thickness of the dielectric layer is reduced, but the breakdown voltage is reduced when the thickness of the dielectric layer is reduced, so that the application range of the method is limited; and thirdly, the capacitance is improved by increasing the area, for example, the area of a capacitance polar plate in a unit area is increased by using the undulating shape, but the mismatch parameter is reduced by the process, so that the electrical performance of the single-layer capacitor is reduced.
Fig. 1 is a schematic view of a semiconductor package structure, the package structure 100 comprising: a substrate (substrate) 101, an interposer (interposer) 102, a System on a Chip (SOC) 103, a silicon capacitor 104a, a silicon capacitor 104b, a silicon capacitor 104c, a silicon capacitor 104d, a silicon capacitor 104e, and a solder ball 105. As can be seen from fig. 1, the substrate 101 and the interposer 102 are connected by solder balls 105, the interposer 102 and the system-in-chip 103 are also connected by solder balls 105, and a plurality of silicon capacitors are distributed on the surfaces of the substrate 101 and the interposer 102 for the system-in-chip 103 to use. As process nodes continue to shrink, such semiconductor packages 100 have exhibited limitations such as package volume limitations encountered due to process and device limitations.
Currently, deep trench capacitors are often used to achieve the goal of increasing capacitance density. The deep trench capacitor is formed on the front surface of the substrate, and generally includes a deep trench and a stacked layer, which are formed by sequentially alternately depositing an electrode layer and a dielectric layer on the inner surface of the deep trench. However, to obtain higher density capacitance per unit area, it is necessary to increase the aspect ratio of the trench etch. However, current etching techniques, the process capability of thin film deposition, and substrate size limitations cannot further increase the capacitance density of deep trench capacitors.
Based on this, the embodiment of the application provides a semiconductor structure and a preparation method, wherein the semiconductor structure comprises: a substrate, a first capacitance structure and a second capacitance structure; the substrate includes a first surface and a second surface disposed opposite along a first direction; the first capacitor structure and the second capacitor structure are respectively arranged on the first surface and the second surface; the first capacitor structure and the second capacitor structure are symmetrically arranged; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitance structures in the first direction. Because the semiconductor structure comprises the second capacitance structure which is arranged opposite to the first capacitance structure, the capacitance density in the unit area of the semiconductor structure can be improved, and the semiconductor structure can be applied to a plurality of different scenes.
The following describes a semiconductor structure in an embodiment of the present application in detail with reference to the accompanying drawings.
Before describing embodiments of the present application, a description of the direction of a semiconductor structure that may be used in the following embodiments is defined. The substrate may include a top surface at the front side and a bottom surface at the back side opposite the front side; the direction intersecting (e.g., perpendicular to) the top and bottom surfaces of the substrate is defined as a first direction, ignoring the flatness of the top and bottom surfaces. In the embodiment of the present application, for example, the first direction may be defined as the X-axis direction.
Fig. 2 is a schematic flow chart of a semiconductor structure manufacturing method according to an embodiment of the present application, fig. 3 to fig. 16 are schematic structural diagrams during a semiconductor structure manufacturing process according to an embodiment of the present application, and the semiconductor structure manufacturing process according to an embodiment of the present application is described in detail below with reference to fig. 2 to fig. 16.
As shown in fig. 2, the method for manufacturing the semiconductor structure includes the following steps S201 to S203:
first, referring to fig. 2 and 3, step S201 is performed to provide a substrate including a first surface 301 and a second surface 302 disposed opposite to each other in a first direction.
In some embodiments, step S201 may include the steps of:
providing an initial substrate 30; the initial substrate 30 includes a first surface 301 and a second surface 302 disposed opposite in the X-axis direction.
Here, the initial substrate 30 may be a semiconductor substrate including a semiconductor material, or may be a wafer. The material of the semiconductor substrate may be silicon (Si); the semiconductor substrate may also include other semiconductor elements, such as: germanium (Ge), or include semiconductor compounds such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys such as: silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide, or combinations thereof. In other embodiments, the initial substrate 30 may also be a substrate after ion doping, such as a P-doped substrate or an N-doped substrate.
In the embodiment of the present application, the initial substrate 30 is taken as an example of a wafer. The first surface 301 may be a front side of the wafer and the second surface 302 may be a back side of the wafer.
Next, referring to fig. 2, 4 and 5, step S202 is performed to form a first capacitor structure 41 extending toward the inside of the substrate along the first direction on the first surface 301.
In some embodiments, step S202 may include the steps of:
step 1: at least one first trench 411 as shown in fig. 4 is formed in the first surface 301.
Note that, in the cross-sectional view shown in fig. 4, only a limited number (4) of the first trenches 411 are shown, and in fact, when the first capacitor structure 41 is formed, a plurality of first trenches 411 are formed on the first surface 301, and the plurality of first trenches 411 may be connected in parallel.
Here, the first trench 411 may be obtained by etching the initial substrate 30. The etching process may employ dry etching. The gas used for dry etching may be a fluoride gas, such as sulfur hexafluoride (SF) 6 ) Carbon tetrafluoride (CF) 4 ) Nitrogen trifluoride (NF) 3 ) Hexafluoroethane (C) 2 F 6 ) Octafluoropropane (C) 3 F 8 ) And trifluoromethane (CHF) 3 ) One or more of the following.
It should be noted that, assuming that the depth of the first trench 411 is B and the thickness of the initial substrate 30 is a, a is greater than or equal to 2B, it is ensured that the subsequent etching of the second trench on the second surface 302 does not etch through the initial substrate 30.
It is noted that the aspect ratio of the first trench 411 is greater than or equal to 20:1, for example, 25:1, 30:1, 35:1, or 40:1.
after forming the at least one first trench 411, a first insulating layer 415 as shown in fig. 5 is formed on the inner surface of the at least one first trench 411, and the first surface 301.
It should be appreciated that the first insulating layer 415 covers the inner surface of the first trench 411 for insulating an initial substrate (e.g., si) and an electrode layer (e.g., tiN) subsequently formed in the first trench 411. The material of the first insulating layer 415 may be silicon dioxide. In an embodiment of the present application, the first insulating layer 415 may be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition (Physical Vapor Deposition, PVD) process, an atomic layer deposition (Atomic Layer Deposition, ALD) process, a spin coating process, a furnace tube process, or the like.
Step 2: forming a first stacked layer 412 as shown in fig. 5 on a surface of the first insulating layer 415; the first stacked layer 412 includes at least two first electrode layers, and at least a first dielectric layer between the first electrode layers.
In practice, the first conductive material and the first dielectric material are sequentially deposited on the surface of the first insulating layer 415 by a suitable deposition process, so as to sequentially form the first electrode layer 11, the first dielectric layer (not shown), the second first electrode layer 12, the second first dielectric layer (not shown), the third first electrode layer 13, the third first dielectric layer (not shown) and the fourth first electrode layer 14 as shown in fig. 5, so as to form the first stacked layer 412. The first electrode layer 11 is connected with the third electrode layer 13, and the second electrode layer 12 is connected with the fourth electrode layer 14, so as to form three capacitors connected in parallel.
Here, the first conductive material may be a conductive metal nitride, an elemental metal, an intermetallic alloy, or a combination thereof; the conductive metal nitride may be, for example, titanium nitride.
In some embodiments, the first dielectric layer may be a single layer of material, such as a high-K (HK) material layer, which may be lanthanum oxide (La 2 O 3 ) Alumina (Al) 2 O 3 ) Hafnium oxide (HfO) 2 ) Hafnium oxynitride (HfON), hafnium silicate (HfSiO) x ) Or zirconia (ZrO 2 ) One or any combination of the above. In other embodiments, the first dielectric layer may also be formed by stacking multiple layers of materials, such as an oxide-nitride-oxide (ONO) structure.
In fig. 5, 4 first electrode layers and 3 first dielectric layers are shown, and in fact, when the first capacitor structure 41 is manufactured, more first electrode layers and first dielectric layers may be formed, so that more parallel capacitors may be formed, which may increase the capacity of the first capacitor structure.
It is to be understood that the same metal material may be used for the first electrode layer 11, the second electrode layer 12, the third electrode layer 13, and the fourth electrode layer 14, or different metal materials may be used. Similarly, the first dielectric layer, the second dielectric layer and the third dielectric layer may be made of the same dielectric material or different dielectric materials.
It should also be noted that each of the at least one first trenches 411 may be elongated laterally with a uniform width. A major portion of each first trench 411 (such as more than 50% of the entire area) may have a width perpendicular to the extension portion sufficient to accommodate all of the first electrode layers and all of the first dielectric layers that are subsequently formed. For example, a major portion of each first trench 411 may have a width perpendicular to the extension portion sufficient to accommodate at least four first electrode layers and at least three first dielectric layers.
Step 3: forming a first sealing layer 413 as shown in fig. 5 at least on the surface of the first stack layer 412 and on the top of the first trench 411; the first sealing layer 413 and the first stacked layer 412 in the first trench 411 have a first void 414 therebetween.
Note that the first sealing layer 413 may include the same dielectric material as the first dielectric layer, or may include a different material from the first dielectric layer. The first sealing layer 413 and the first stacked layer 412 in the first trench 411 have a first gap 414 therebetween, so that an air gap isolation structure having a specific aspect ratio can be formed.
The first stacked layer 412 and the first sealing layer 413 form the first capacitor structure 41.
In some embodiments, after forming the first capacitance structure 41, the method further comprises:
a first redistribution layer 51 as shown in fig. 6 is formed on the first surface 301 in electrical connection with the first capacitor structure 41.
In implementation, first, etching the fourth layer first electrode layer 14, the third layer first electrode layer 13, the second layer first electrode layer 12 and the first layer first electrode layer 11 on the surface of the first surface 301 to remove part of the fourth layer first electrode layer 14, part of the third layer first electrode layer 13, part of the second layer first electrode layer 12 and part of the first layer first electrode layer 11, and exposing part of the fourth layer first electrode layer 14, part of the third layer first electrode layer 13, part of the second layer first electrode layer 12 and part of the first layer first electrode layer 11 for subsequent extraction of an electrical signal; next, forming a dielectric layer 60 and a plurality of first contact holes 53 in the dielectric layer 60 on the surfaces of the etched fourth first electrode layer 14, third first electrode layer 13, second first electrode layer 12 and first electrode layer 11, wherein each first contact hole 53 is filled with a conductive material, and each first contact hole 53 is electrically connected with the first electrode layer 11, the second first electrode layer 12, the third first electrode layer 13 and the fourth first electrode layer 14 respectively; again, a second insulating layer 416 is formed over the first contact holes 53, and a first contact pad 450 contacting each of the first contact holes 53 is formed over the second insulating layer 416; finally, a third insulating layer 418 is formed on the surface of the first contact pad 450, wherein a medium 60 is also formed between the third insulating layer 418 and the second insulating layer 416. The first contact hole 53, the first contact pad 450, the dielectric layer 60, the second insulating layer 416, and the third insulating layer 418 constitute a first re-wiring layer 51.
Here, the conductive material filled in the first contact hole 53 may be a metal material, for example, copper. The material of the second insulating layer 416 may be, for example, silicon oxide or silicon nitride, and the material of the third insulating layer 418 may be, for example, silicon nitride. The material of the dielectric layer may be silicon oxide.
In some embodiments, after forming the first capacitance structure 41, the initial substrate 30 is thinned along the second surface 302 to form the substrate 30a.
In practice, the first surface 301 of the initial substrate 30 is bonded (e.g., temporarily bonded) to the first carrier wafer 303 to form the structure shown in fig. 7, and then the initial substrate 30 is etched or chemically mechanically polished (Chemical Mechanical Polishing, CMP) along the second surface 302 to achieve the thinning of the initial substrate 30 to form the substrate 30a. In the embodiment of the present application, since the thickness of the thinned substrate 30a is only tens of micrometers, the first carrier wafer 303 is required to be used as a supporting structure for supporting the subsequent process steps, such as the step of forming the second capacitor structure.
It should be noted that, in the thinning process of the second surface 302 of the initial substrate 30, the thickness of the thinning process needs to be controlled such that the thickness of the substrate 30a after the initial substrate 30 is thinned is greater than 2 times the depth of the first trench 411. In this way, the bottoms of the trenches of the first and second capacitor structures 41 and 42 are not in contact with each other, and short-circuiting of the first and second capacitor structures 41 and 42 can be avoided.
Finally, referring to fig. 2 and 8 to 14, step S203 is performed to form a second capacitor structure 42 extending toward the inside of the substrate 30a along the first direction on the second surface 302; the first capacitor structure 41 and the second capacitor structure 42 are symmetrically arranged, and the symmetry plane of the first capacitor structure 41 and the second capacitor structure 42 is perpendicular to the first direction; the first direction is the thickness direction of the substrate 30 a; the thickness of the substrate 30a is greater than the sum of the dimensions of the first and second capacitance structures 41 and 42 in the first direction.
Since the first and second grooves 411 and 421 (as shown in fig. 8) are symmetrically disposed, the first and second grooves 411 and 421 have the same depth. That is, the thickness C (as shown in fig. 9) of the substrate 30a after the thinning is greater than the sum 2B of the depth of the first trench 411 and the depth of the second trench 421 (see fig. 4). For example, the thickness of the initial substrate is 100 micrometers, and the depth of the first trench 411 or the second trench 421 is 20 micrometers, so that the thickness of the substrate 30a should be greater than 40 micrometers after the thinning process; that is, the reduced thickness is less than 60 microns to meet the design requirements.
It should be noted that fig. 8 is an enlarged schematic view of the second capacitor structure 42, and the specific forming process of the second capacitor structure 42 can be understood with reference to fig. 8.
In some embodiments, step S203 may include the steps of:
step 1: at least one second groove 421 as shown in fig. 8 is formed in the second surface 302.
Note that, in the cross-sectional view shown in fig. 8, only a limited number (4) of the second grooves 421 are shown, and in fact, when the second capacitor structure 42 is formed, a plurality of the second grooves 421 are formed on the second surface 302, and the plurality of the second grooves 421 may be connected in parallel.
It should be noted that, the method of forming the second trench 421 is similar to that of forming the first trench 411, and it is understood that the description is omitted here.
In some embodiments, the aspect ratio of the second trench 421 is greater than or equal to 20:1, for example, 25:1, 30:1, 35:1, or 40:1.
In some embodiments, after forming the at least one second trench 421, a fourth insulating layer 425 is formed on the inner surface of the at least one second trench 421, and on the second surface 302.
It is understood that the fourth insulating layer 425 covers the inner surface of the second trench 421 for insulating a substrate (e.g., si) and an electrode layer (e.g., tiN) subsequently formed in the second trench 421. The material of the fourth insulating layer 425 may be silicon dioxide. In the embodiment of the present application, the fourth insulating layer 425 may be formed by using CVD, PVD, ALD, spin coating, or furnace process.
Step 2: forming a second stacked layer 422 as shown in fig. 8 on the surface of the fourth insulating layer 425; the second stacked layer 422 includes at least two second electrode layers, and at least a second dielectric layer between the second electrode layers.
In practice, the second conductive material and the second dielectric material are sequentially deposited on the surface of the fourth insulating layer 425 in a cyclic manner by using a suitable deposition process, so as to sequentially form the first second electrode layer 21, the first second dielectric layer (not shown), the second electrode layer 22, the second dielectric layer (not shown), the third second electrode layer 23, the third second dielectric layer (not shown) and the fourth second electrode layer 24, so as to form the second stacked layer 422. The first second electrode layer 21 is connected with the third second electrode layer 23, and the second electrode layer 22 is connected with the fourth second electrode layer 24, so that three capacitors connected in parallel are formed.
Here, the second conductive material may be a conductive metal nitride, an elemental metal, an intermetallic alloy, or a combination thereof; the conductive metal nitride may be, for example, titanium nitride. The second dielectric layer may be a single layer of material, such as a layer of HK material. In other embodiments, the second dielectric layer may be formed by stacking multiple layers of materials, such as an ONO structure.
It should be noted that, in fig. 8, 4 second electrode layers and 3 second dielectric layers are shown, in fact, when the second capacitor structure 42 is fabricated, more second electrode layers and second dielectric layers may be formed, so that more parallel capacitors may be formed, which may increase the capacity of the fabricated second capacitor structure.
It is to be understood that the same metal material may be used for the first second electrode layer 21, the second electrode layer 22, the third second electrode layer 23, and the fourth second electrode layer 24, or different metal materials may be used. Similarly, the first second dielectric layer, the second dielectric layer and the third second dielectric layer may be made of the same dielectric material or different dielectric materials.
Step 3: forming a second sealing layer 423 at least on the surface of the second stacked layer 422 and on top of the second groove 421; the second sealing layer 423 and the second stacked layer 422 in the second trench 421 have a second void 424 therebetween.
The second sealing layer 423 may be made of the same material as the first sealing layer 413 or may be made of a different material from the first sealing layer 413. The second gap 424 between the second sealing layer 423 and the second stacked layer 422 in the second trench 421 can form an air gap isolation structure with a specific aspect ratio.
The second stacked layer 422 and the second sealing layer 423 form the second capacitor structure 42.
In the embodiment of the present application, the first capacitor structure 41 shown in fig. 9 is formed on the first surface 301 of the substrate 30a, and the second capacitor structure 42 shown in fig. 9 is formed on the second surface 302 of the substrate 30a, so that the capacitance density per unit area of the substrate 30a can be improved, and the capacitance value required by the high-power chip can be satisfied.
In some embodiments, referring to fig. 10 to 14, after forming the second capacitor structure 42, the method of manufacturing the semiconductor structure further includes the following steps 11 to 17:
step 11: forming a through silicon via 33 penetrating the substrate 30a as shown in fig. 10 or 11;
the through-silicon via 33 penetrates the substrate 30a in the thickness direction of the substrate 30a. The through silicon vias 33 may be connected to the first redistribution layer 51 on the first surface 301 (as shown in fig. 10), thereby enabling the first redistribution layer 51 to be routed out of the second surface 302 (i.e., the back side) of the substrate 30a.
The electrical connection between the through-silicon via 33 and the first redistribution layer 51 means that the through-silicon via 33 is connected to the first contact pad 450 in the first redistribution layer 51.
Step 12: a second redistribution layer 52 as shown in fig. 11 is formed on the second surface 302.
In practice, etching the fourth second electrode layer 24, the third second electrode layer 23, the second electrode layer 22 and the first second electrode layer 21 on the second surface 302 to remove part of the fourth second electrode layer 24, part of the third second electrode layer 23, part of the second electrode layer 22 and part of the first second electrode layer 21 and expose part of the fourth second electrode layer 24, part of the third second electrode layer 23, part of the second electrode layer 22 and part of the first second electrode layer 21 for subsequent extraction of electrical signals; next, forming a dielectric layer 60 and a plurality of second contact holes 54 in the dielectric layer 60 on the surfaces of the etched fourth second electrode layer 24, third second electrode layer 23, second electrode layer 22 and first second electrode layer 21, wherein each second contact hole 54 is filled with a conductive material, and each second contact hole 54 is electrically connected with the first second electrode layer 21, second electrode layer 22, third second electrode layer 23 and fourth second electrode layer 24 respectively; again, a fifth insulating layer 426 is formed over the second contact hole 54, and a second contact pad 451 is formed over the fifth insulating layer 426, and finally, a sixth insulating layer 428 is formed on the surface of the second contact pad 451, wherein a medium 60 is also formed between the sixth insulating layer 428 and the fifth insulating layer 426. The second contact hole 54, the second contact pad 451, the dielectric layer 60, the fifth insulating layer 426, and the sixth insulating layer 428 constitute a second redistribution layer 52.
Here, the conductive material filled in the second contact hole 54 may be a metal material, for example, copper. The material of the fifth insulating layer 426 may be, for example, silicon oxide or silicon nitride, and the material of the sixth insulating layer 428 may be, for example, silicon nitride. The material of the dielectric layer may be silicon oxide.
The through-silicon via 33 is electrically connected to the second redistribution layer 52. Specifically, the through silicon via 33 is connected to the second contact pad 451 in the second redistribution layer 52.
Step 13: a second pad 62 as shown in fig. 12 is formed on the second surface 302 in electrical connection with the second redistribution layer 52.
The second pad 62 is used to draw out the electrical signal of the second capacitance structure 42. The number of the second pads 62 may be plural, and the material of the second pads 62 is generally a metal material, for example, copper, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), etc., and the material of the second pads 62 in the embodiment of the present application is metallic aluminum, but is not limited thereto.
Step 14: the second bonding pad 62 is temporarily bonded to the second carrier wafer 304 to form a structure as shown in fig. 13, so as to fix the substrate 30a on which the second capacitor structure 42 is formed, so that the first bonding pad 61 is formed on the surface of the substrate 30 a.
Step 15: the first carrier wafer 303 is removed.
In the embodiment of the present application, the first carrier wafer 303 may be cleaned and removed by etching, polishing, and planarization processes.
In other embodiments, when there is a temporary bond between the first surface 301 and the first carrier wafer 303, the first carrier wafer 303 may be removed by de-bonding.
Step 16: a first pad 61 as shown in fig. 14 electrically connected to the first re-wiring layer 51 is formed on the first surface 301.
The first pad 61 may lead out the electrical signals of the first capacitor structure 41, or the first capacitor structure 41 and the second capacitor structure 42. The number of the first pads 61 may be plural, and the first pads 61 may be made of the same metal material as the second pads 62, or may be made of a different metal material from the second pads 62.
Step 17: the second carrier wafer 304 is removed.
It should be noted that, in the embodiment of the present application, the second carrier wafer 304 may be removed by means of debonding the second bonding pad 62 from the second carrier wafer, or the second carrier wafer 304 may be removed by etching, polishing, and planarization processes.
The formation of the semiconductor structure 200 shown in fig. 14 on the substrate 30a can be achieved through the above steps. The semiconductor structure 200 may form a single sided capacitance or a double sided capacitance. When the semiconductor structure 200 is a single-sided capacitor, the capacitance density is doubled compared with that of the capacitor structure in the related art; when the semiconductor structure 200 is a double-sided capacitor, the capacitance density is doubled compared to that of the related art capacitor structure, but the first capacitor structure 41 and the second capacitor structure 42 located on the first surface 301 and the second surface 302 cannot be used by both upper and lower devices (e.g., chips and intermediaries in 2.5D packages).
In summary, the semiconductor structure provided by the embodiment of the application can increase the capacitance density in a unit area, so that the semiconductor structure can be applied to various different scenes.
In some embodiments, referring to fig. 15 and 16, after forming the second capacitor structure 42 (i.e., based on the structure shown in fig. 9), the method of manufacturing the semiconductor structure may further include the following steps 21 to 26:
step 21: the second redistribution layer 52 shown in fig. 15 is formed on the second surface 302.
Step 22: a second pad 62 (shown in fig. 16) is formed on the second surface 302 in electrical connection with the second redistribution layer 52.
Step 23: the second bonding pad 62 is temporarily bonded to the second carrier wafer 304 to fix the substrate 30a on which the second capacitor structure 42 is formed, so that the first bonding pad 61 is formed on the surface of the substrate 30 a.
Step 24: the first carrier wafer 303 is removed.
Step 25: a first pad 61 (shown in fig. 16) electrically connected to the first re-wiring layer 51 is formed on the first surface 301.
Step 26: the second carrier wafer 304 is removed.
It should be noted that, in the embodiment of the present application, the forming process of the second redistribution layer 52, the second pad 62, and the first pad 61 in the steps S21 to 26 is similar to the forming process of the second redistribution layer 52, the second pad 62, and the first pad 61 in the steps S12 to 17 of the above embodiment, and will not be repeated here.
It should be further noted that the semiconductor structure shown in fig. 16 according to the embodiment of the present application may form a double-sided capacitor structure, and the first capacitor structure 41 and the second capacitor structure 42 may be used for both upper and lower devices (or, for example, a chip and an interposer in a 2.5D package). Therefore, the capacitance capacity can be doubled under the same size, and the size can be reduced by half under the same capacitance capacity, so that the application range is wide.
An embodiment of the present application provides a semiconductor structure 200, as shown in fig. 14 and 16, the semiconductor structure 200 includes:
a substrate 30a, the substrate 30a including a first surface 301 and a second surface 302 disposed opposite to each other in the X-axis direction;
the first capacitor structure 41 is disposed on the first surface 301 and extends toward the inside of the substrate 30a along the X-axis direction;
the second capacitor structure 42 is disposed on the second surface 302 and extends toward the inside of the substrate 30a along the X-axis direction;
the first capacitor structure 41 and the second capacitor structure 42 are symmetrically arranged, and the symmetry plane of the first capacitor structure 41 and the second capacitor structure 42 is perpendicular to the X-axis direction, that is, the symmetry plane of the first capacitor structure 41 and the second capacitor structure 42 is the plane where the substrate 30a is located; the thickness of the substrate 30a is greater than the sum of the dimensions of the first and second capacitance structures 41 and 42 in the X-axis direction.
The first capacitor structure 41 and the second capacitor structure 42 are symmetrically arranged about the X-axis direction, so that the first capacitor structure 41 and the second capacitor structure 42 can be ensured to be in a unit area of a wafer, and the increase of the capacitance density in the unit area can be realized.
In some embodiments, referring to fig. 5 and 8, the first capacitor structure 41 and the second capacitor structure 42 may be trench capacitors, and the trench depths of the first capacitor structure 41 and the second capacitor structure 42 may be the same, and the thickness of the substrate 30a is greater than 2 times the trench depth. In this way it is ensured that the trench bottom of the first capacitance structure 41 and the trench bottom of the second capacitance structure 42 are not in contact, i.e. the first capacitance structure 41 and the second capacitance structure 42 do not affect each other.
In some embodiments, with continued reference to fig. 14 and 16, the semiconductor structure 200 further includes a first redistribution layer 51 and a second redistribution layer 52;
the first redistribution layer 51 is disposed on the first surface 301 and electrically connected to the first capacitor structure 41;
the second redistribution layer 52 is disposed on the second surface 302 and electrically connected to the second capacitor structure 42.
It should be noted that the semiconductor structure illustrated in fig. 16 may be a double-sided capacitor structure, and the first capacitor structure 41 and the second capacitor structure 42 may be used for both upper and lower devices (e.g., a chip and an interposer in a 2.5D package). Therefore, the capacitance capacity can be doubled under the same size, and the size can be reduced by half under the same capacitance capacity, so that the application range is wide.
In some embodiments, with continued reference to fig. 14, semiconductor structure 200 further includes a through silicon via 33 extending through substrate 30a, the through silicon via 33 being electrically connected to first and second redistribution layers 51 and 52.
It should be noted that the semiconductor structure 200 shown in fig. 14 may be a single-sided capacitor or a double-sided capacitor. When the semiconductor structure 200 is a single-sided capacitor, the capacitance density is doubled compared with that of the capacitor structure in the related art; when the semiconductor structure 200 is a double-sided capacitor, the capacitance density is doubled compared to that of the related art capacitor structure, but the first capacitor structure 41 and the second capacitor structure 42 located on the first surface 301 and the second surface 302 cannot be used by both upper and lower devices (e.g., chips and intermediaries in 2.5D packages).
In some embodiments, referring to fig. 5, the first capacitor structure 41 includes:
at least one first trench 411 disposed on the first surface 301 and extending toward the inside of the substrate 30 a;
a first stack layer 412 covering an inner surface of the first trench 411; the first stacked layer 412 includes at least four first electrode layers (first layer 11, second layer 12, third layer 13, fourth layer 14), and a first dielectric layer (not shown) located at least between the first electrode layers;
A first sealing layer 413 covering the surface of the first stacked layer 412 and the top of the first trench 411; the first sealing layer 413 and the first stacked layer 412 in the first trench 411 have a first void 414 therebetween.
In some embodiments, with continued reference to fig. 8, the second capacitance structure 42 includes:
at least one second groove 421 disposed on the second surface 302 and extending toward the inside of the substrate 30 a;
a second stacked layer 422 covering an inner surface of the second groove 421; the second stacked layer 422 includes at least two second electrode layers (a first layer of the second electrode layer 21, a second layer of the second electrode layer 22, a third layer of the second electrode layer 23, a fourth layer of the second electrode layer 24), and a second dielectric layer (not shown) at least between the second electrode layers;
a second sealing layer 423 covering the surface of the second stacked layer 422 and the top of the second trench 421; the second sealing layer 423 and the second stacked layer 422 in the second trench 421 have a second void 424 therebetween.
In some embodiments, the aspect ratio of the first trench 411 is greater than or equal to 20:1, and the aspect ratio of the second trench 421 is greater than or equal to 20:1.
In some embodiments, with continued reference to fig. 14 and 16, the semiconductor structure 200 further includes a first pad 61 and a second pad 62;
A first pad 61 disposed on the first surface 301 and electrically connected to the first redistribution layer 51; specifically, the first pad 61 is connected to the first contact pad 450 in the first redistribution layer 51, and the first pad 61 is used to draw out an electrical signal of the first capacitance structure 41.
A second pad 62 disposed on the second surface 302 and electrically connected to the second redistribution layer 52; specifically, the second pad 62 is connected to the second contact pad 451 in the second redistribution layer 52, and the second pad 62 is used to draw out the electrical signal of the second capacitance structure 42.
It should be noted that, the semiconductor structure in the embodiment of the present application is similar to the semiconductor structure prepared by the method for preparing a semiconductor structure in the above embodiment, and for technical features that are not disclosed in detail in the embodiment of the present application, please refer to the above embodiment for understanding, and no further description is given here.
In summary, embodiments of the present application provide a semiconductor structure and a method of manufacturing the same, the semiconductor structure including a substrate including a first surface and a second surface disposed opposite to each other along a first direction; the first capacitor structure is arranged on the first surface and extends towards the inside of the substrate along the first direction; the second capacitor structure is arranged on the second surface and extends towards the inside of the substrate along the first direction; the first capacitor structure and the second capacitor structure are symmetrically arranged, and the symmetrical planes of the first capacitor structure and the second capacitor structure are perpendicular to the first direction; the first direction is the thickness direction of the substrate; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitance structures in the first direction. In this way, the capacitance density per unit area of the semiconductor structure 200 can be increased, thereby enabling the semiconductor structure 200 to meet a variety of different packaging requirements.
The above is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.
It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The methods disclosed in the method embodiments provided by the application can be arbitrarily combined under the condition of no conflict to obtain a new method embodiment.
The features disclosed in the several product embodiments provided by the application can be combined arbitrarily under the condition of no conflict to obtain new product embodiments.
The features disclosed in the embodiments of the method or the apparatus provided by the application can be arbitrarily combined without conflict to obtain new embodiments of the method or the apparatus.
The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered.

Claims (14)

1. A semiconductor structure, comprising:
a substrate including a first surface and a second surface disposed opposite in a first direction;
the first capacitor structure is arranged on the first surface and extends towards the inside of the substrate along the first direction;
the second capacitor structure is arranged on the second surface and extends towards the inside of the substrate along the first direction;
the first capacitor structure and the second capacitor structure are symmetrically arranged, and the symmetry planes of the first capacitor structure and the second capacitor structure are perpendicular to the first direction; the first direction is the thickness direction of the substrate; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitive structures in the first direction.
2. The semiconductor structure of claim 1, further comprising a first redistribution layer and a second redistribution layer;
The first rewiring layer is arranged on the first surface and is electrically connected with the first capacitor structure;
the second redistribution layer is disposed on the second surface and electrically connected to the second capacitor structure.
3. The semiconductor structure of claim 2, wherein the semiconductor structure further comprises: through silicon vias penetrating the substrate;
the through silicon via is electrically connected with the first and second redistribution layers.
4. A semiconductor structure according to any one of claims 1 to 3, wherein the first capacitance structure comprises:
at least one first groove arranged on the first surface and extending towards the inside of the substrate;
a first stacked layer covering an inner surface of the first trench; the first stacked layer comprises at least two first electrode layers and at least a first dielectric layer positioned between the first electrode layers;
a first sealing layer covering the surface of the first stacked layer and the top of the first trench; a first gap is formed between the first sealing layer and the first stacking layer in the first groove.
5. The semiconductor structure of claim 4, wherein the second capacitance structure comprises:
At least one second groove arranged on the second surface and extending towards the inside of the substrate;
a second stacked layer covering an inner surface of the second trench; the second stacked layer comprises at least two second electrode layers and at least a second dielectric layer positioned between the second electrode layers;
a second sealing layer covering the surface of the second stacked layer and the top of the second trench; a second gap is provided between the second sealing layer and the second stacking layer in the second trench.
6. The semiconductor structure of claim 5, wherein an aspect ratio of the first trench and the second trench is greater than or equal to 20:1.
7. The semiconductor structure of claim 2, further comprising a first pad and a second pad;
the first bonding pad is arranged on the first surface and is electrically connected with the first rewiring layer;
the second bonding pad is arranged on the second surface and is electrically connected with the second rewiring layer.
8. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate comprising a first surface and a second surface disposed opposite along a first direction;
Forming a first capacitor structure on the first surface extending along the first direction inside the substrate;
forming a second capacitor structure on the second surface extending along the first direction inside the substrate;
the first capacitor structure and the second capacitor structure are symmetrically arranged, and the symmetry planes of the first capacitor structure and the second capacitor structure are perpendicular to the first direction; the first direction is the thickness direction of the substrate; the thickness of the substrate is greater than the sum of the dimensions of the first and second capacitive structures in the first direction.
9. The method of claim 8, wherein after forming the first capacitance structure, the method further comprises:
and forming a first rewiring layer electrically connected with the first capacitor structure on the first surface.
10. The method of claim 9, wherein after forming the second capacitance structure, the method further comprises:
forming a second redistribution layer on the second surface electrically connected to the second capacitance structure;
forming a second pad electrically connected to the second redistribution layer on the second surface;
And forming a first bonding pad electrically connected with the first rewiring layer on the first surface.
11. The method of claim 10, wherein after forming the second capacitance structure and before forming the second redistribution layer, the method further comprises:
forming a through silicon via penetrating through the substrate; the through silicon via is electrically connected with the first and second redistribution layers.
12. The method of any one of claims 8 to 11, wherein forming a first capacitance structure on the first surface extending inward of the substrate comprises:
forming at least one first trench in the first surface;
forming a first stacked layer on the inner surface of the first groove; the first stacked layer comprises at least two first electrode layers and at least a first dielectric layer positioned between the first electrode layers;
forming a first sealing layer at least on the surface of the first stacking layer and the top of the first groove; a first gap is formed between the first sealing layer and the first stacking layer in the first groove.
13. The method of any one of claims 8 to 11, wherein forming a second capacitance structure on the second surface extending inward of the substrate comprises:
Forming at least one second groove on the second surface;
forming a second stacked layer on the inner surface of the second groove; the second stacked layer comprises at least two second electrode layers and at least a second dielectric layer positioned between the second electrode layers;
forming a second sealing layer at least on the surface of the second stacking layer and the top of the second groove; a second gap is provided between the second sealing layer and the second stacking layer in the second trench.
14. The method of claim 8, wherein the providing a substrate comprises:
providing an initial substrate; the initial substrate includes the first surface and the second surface disposed opposite along a first direction;
and after the first capacitor structure is formed, thinning the initial substrate along the second surface to form the substrate.
CN202310928764.6A 2023-07-26 2023-07-26 Semiconductor structure and preparation method thereof Pending CN116666382A (en)

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