WO2011090440A1

WO2011090440A1 - Capacitor arrangement and a method of forming the same

Info

Publication number: WO2011090440A1
Application number: PCT/SG2011/000032
Authority: WO
Inventors: Navab Singh; Vaidyanathan Kripesh; Ying Ying Lim; Mohanraj Soundarapandian; Ajay Agarwal; Ranganathan Nagarajan; Jinglin Shi
Original assignee: Agency For Science, Technology And Research
Priority date: 2010-01-25
Filing date: 2011-01-25
Publication date: 2011-07-28

Abstract

According to embodiments of the present invention, a capacitor arrangement is provided. The capacitor arrangement includes: a substrate; a first contact disposed over the substrate; a second contact disposed over the substrate; and a stack of layers, comprising: a plurality of first conductive layers; a plurality of second conductive layers; and a plurality of capacitive isolation layers; wherein the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers; and wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact.

Description

CAPACITOR ARRANGEMENT AND A METHOD OF FORMING THE SAME

Cross-Reference To Related Application [0001] This application claims the benefit of priority of Singapore application No. 201000519-7, filed 25 January 2010, the content of it being hereby incorporated by reference in its entirety for all purposes.

Technical Field

[0002] Various embodiments relate to a capacitor arrangement and a method of forming a capacitor arrangement.

Background

[0003] Miniaturization and the reduction of on board passive components is an increasing challenge in the packaging industry. In this regard, silicon-based platform has emerged as an attractive packaging option for system-in package (SiP) technologies, as it allows high levels of passive integration on silicon, which can be integrated with other CMOS, MEMS and GaAs technologies in one compact SiP package. In addition, three- dimensional (3D) die stacking is also a flexible option using such technology.

[0004] High density capacitors are required for RF supply line, phase-locked loop filtering and DRAM memories. For DRAM applications, the capacity of the capacitor required is in fF/μιη². High-density capacitors fabricated in semiconductor substrates, especially in silicon are generally known. Different parameters can be considered in attempting to increase the capacity of the capacitor. Making trench or pillar structures in the 3D dimension is an option. In addition, implantable microsystems offering long lifetimes require significant energy storage density and a stable shelf- life.

[0005] However, conventional high density capacitors may not be able to meet the various requirements, such as the capacitive storage density, the shelf-life and the breakdown voltage, for various applications. Table 1 shows examples of high density capacitors known in the art.

Table 1 : High density capacitors

Reference Capacitor Breakdown Leakage

Lifetime density voltage current

(years) (nF/rnm²) (V) (nA/mm )

[1] 20-30 30 <1 10

[1] 400 30 <1 10

[2] 300 10 NIL 10

[3] 200 NIL NIL NIL

[4] Cap loss~70%

156000 1.2 < 10000

Over 10 years

Reference [1] - Roozeboom F., Kemmeren A.L.A.M., Verhoeven J.F.C., F.C. van den

Heuvel, Klootwijk J., Kretschman H., Fric T., E.C.E. van Grunsven, Bardy S., Bunel C, Chevrie D., LeComec F., Ledain S., Murray F. and Philippe P., "Passive and heterogeneous integration towards a Si-based System-in-Package concept", Thin Solid Films 504, 391 - 396 (2006).

Reference [2] - Sun W. and Chen X., "Fabrication and tests of a novel three dimensional micro supercapacitor", Microelectronic Engineering 86, 1307-1310 (2009).

Reference [3] - Dang B., Wright S.L., Andry P., Sprogis E., Ketkar S., Tsang C,

Polastre R. and Knickerbocker J., "3D Chip Stack with Integrated Decoupling Capacitors", Proc. ECTC, pp. 1-5, 2009

Reference [4] - Mars P. and Greene C, "CAP-XX & Powercast - RF Energy Harvesting",

Darell NanoPower Forum, 2009.

(http://www.cap-xx.com/resources/docs) Summary

[0006] According to an embodiment, a capacitor arrangement is provided. The capacitor arrangement may include: a substrate; a first contact disposed over the substrate; a second contact disposed over the substrate; and a stack of layers, comprising: a plurality of first conductive layers; a plurality of second conductive layers; and a plurality of capacitive isolation layers; wherein the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers; and wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact.

[0007] According to an embodiment, a method of forming a capacitor arrangement is provided. The method of forming the capacitor arrangement may include: forming a first contact over a substrate; forming a second contact over the substrate; and forming a stack of layers over the substrate, wherein forming the stack of layer includes: forming a plurality of first conductive layers; forming a plurality of second conductive layers; and forming a plurality of capacitive isolation layers; wherein the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers; and wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact. Brief Description of the Drawings

[0008] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0009] FIGS. 1A and IB show schematic block diagrams of a capacitor arrangement, according to various embodiments.

[0010] FIGS. 2A and 2B show schematic cross-sectional views of a capacitor arrangement, according to various embodiments.

[0011] FIG. 2C shows a partially exploded view of the capacitor arrangement of the embodiment of FIG. 2B.

[0012] FIG. 3 shows a flow chart illustrating a method of forming a capacitor arrangement, according to various embodiments.

[0013] FIGS. 4A and 4B show schematic cross-sectional views of substrates, according to various embodiments.

[0014] FIGS. 4C to 4H show schematic cross-sectional views of a fabrication process to manufacture a capacitor arrangement, according to various embodiments.

[0015] FIGS. 5A to 5D show schematic cross-sectional views of a fabrication process to manufacture a capacitor arrangement, according to various embodiments.

Detailed Description [0016] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0017] Various embodiments provide a capacitor arrangement that may provide a high capacitive storage density and a method of forming the capacitor arrangement, without or with reduced at least some of the associated disadvantages of conventional capacitors.

[0018] Various embodiments may provide a capacitor arrangement including a plurality of conductive layers and a plurality of capacitive isolation layers. The plurality of conductive layers may include a plurality of first conductive layers and a plurality of second conductive layers. In various embodiments, the capacitor arrangement may be configured such that the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers.

[0019] Various embodiments may provide a capacitor arrangement including a multilayer arrangement (for example a stack of layers) including a plurality of conductive layers and a plurality of capacitive isolation layers in a metal-insulator-metal (MIM) arrangement, in a planar or high aspect-ratio (for example including a trench) configuration and a method of forming such a capacitor arrangement. In various embodiments, the capacitive storage density may depend on the multilayer arrangement. As an example, the capacitive storage density of a metal-insulator-metal (MIM) trench capacitor design may be increased over 21 times by significantly increasing the MIM surface area for a given silicon area, for example, by employing a 10-layer structure and a high-aspect-ratio via process. This high density 3D trench capacitor may be achieved while minimizing the footprint required. A 10-layer structure may mean a structure having 10 layers of metals (eg. 5 layers of a first metal and 5 layers of a second metal, arranged alternately), with a layer of dielectric in between two successive metal layers.

[0020] In various embodiments, the plurality of conductive layers and the plurality of capacitive isolation layers of the stack of layers are arranged alternately. In various embodiments, the conductive layers may be metal layers and the capacitive isolation layers may be dielectric layers, such that multiple layers of dielectric and metals are formed over a substrate and/or at least partially in a trench formed in a substrate, in a ' metal-insulator-metal ' (MIM) configuration.

[0021] In various embodiments, the plurality of conductive layers may include a plurality of first conductive layers and a plurality of second conductive layers, such that the plurality of conductive layers may include a plurality of first conductive layers of a first material and a plurality of second conductive layers of a second material, where the first and second materials are different materials. As an example, the first material and the second material may be respectively a first metal and a second metal. In various embodiments, the plurality of the capacitive isolation layers may include a dielectric material with a high dielectric constant, κ, (ie. a high κ dielectric material, i.e. eg. a material having a dielectric constant greater than the dielectric constant of silicon dioxide, e.g. a dielectric constant greater than 3.9). As examples and not limitations, one layer of dielectric and two layers of metals in a MIM configuration, or two layers of dielectric and three layers of metals in a MIMIM configuration, or three layers of dielectric and four layers of metals in a MIMIMIM configuration may be provided, such as over the substrate and/or at least partially in the trench formed, for example, in the substrate. It should be appreciated that any number of layers of metals and the corresponding number of layers of dielectric, where a layer of dielectric is arranged in between two layers of metals, may be provided. The number of layers of metals and dielectric provided may depend on the capacitance to be achieved for the different applications.

[0022] In various embodiments, the plurality of first conductive layers (for example layers of a first metal) and a plurality of second conductive layers (for example layers of a second metal) may be arranged alternately, with a layer of capacitive isolation layer (for example a dielectric layer) in between. For example, a ' metal i-insulator-metal₂' (Mrl- M₂) or a ' metal _!-insulator-meta^-insulator-metali-insulator-meta^' (M₁-I-M₂-I-Mj-I-M₂) configuration, where Mi≠ M₂, may be provided over a substrate and/or at least partially in a trench formed, for example in a substrate. In various embodiments, the number of the layers of the different metals may be the same or different. For example, the number of layers of the different metals is the same in the configurations of Mi-I-M₂ or Mi-I-M₂-I- Mi-I-M₂ but is different in the configuration of M₁-I-M₂-I-M₁. In various embodiments, the substrate may be used as an electrode, for example in embodiments where the number of layers of the different metals is different.

[0023] In the context of various embodiments, the term 'MIM layers' may refer to a stack of layers or a multi-layer arrangement having a plurality of conductive layers and a plurality of capacitive isolation layers. The term 'MIM layers' may be used to refer to a stack of layers having any number of layers of conductive layers (eg. metals or other conductive materials) with a capacitive isolation layer (eg. dielectric or insulator layer) in between, and should be understood as not being limited to three layers. The plurality of conductive layers may include a plurality of first conductive layers and a plurality of second conductive layers. The plurality of first conductive layers and the plurality of second conductive layers are alternated with each other with a capacitive isolation layer in between. The plurality of first conductive layers and the plurality of second conductive layers, are of different materials. Therefore, the term 'MIM layers' may include a stack of layers having the configuration of Mj-I-M₂, Mi-I-M₂-I-Mi, Mi-I-M₂-I-M₁-I-M₂, or any other number of layers, where Mi≠ M₂.

[0024] Various embodiments of a capacitor arrangement and a method of forming a capacitor arrangement may provide a compact, ultra high density integrated capacitor through the use of a high aspect ratio trench. Various embodiments may enable the use of a single contact for all the metal layers of the same material, which therefore enables a compact footprint, and which may be implemented on Si-based platform which may allow for high levels of passive integration on silicon that may be integrated with other CMOS, MEMS and GaAs technologies in one compact systein-in package (SiP) package. For example, a contact is provided for all layers of a first metal (eg. a plurality of first conductive layers) and another contact is provided for all layers of a second metal (eg. a plurality of second conductive layers), such that at least two contacts are provided.

[0025] Various embodiments may provide high density integrated three-dimensional (3D) trench capacitors. Various embodiments may provide a trench capacitor or a capacitor arrangement including a high aspect ratio trench which may allow multiple layers or a stack of layers of conductive layers and capacitive isolation layers to be formed at least partially in the trench. Therefore, a high aspect ratio capacitor may be provided. In various embodiments, the stack of layers may have a substantially U-like shape.

[0026] Various . embodiments may provide high density capacitors, for example high density trench capacitors, and a method to realize or form the high density capacitors. The high density capacitors may be used for implantable medical applications, and as miniaturized storage for medical and mobile applications. Various embodiments of the high density capacitors may be compatible with silicon (Si) complementary metal oxide semiconductor (CMOS) process.

[0027] Various embodiments of the high density capacitors may have a long term stability of approximately 10 years or more. Various embodiments of the high density capacitors may provide capacitance density or capacitive storage density of approximately 140 nF/mm (140 nanofarad per millimeter square) or more (ie.≥140 nF/mm ). In various embodiments, the high density capacitors may provide capacitance density in the range of approximately 140 nF/mm² to 1200 nF/mm², for example a range of approximately 140 nF/mm² to 800 nF/mm², a range of approximately 140 nF/mm² to 500 nF/mm², or a range of approximately 300 nF/mm² to 1200 nF/mm², such that a capacitance density of approximately 200 nF/mm², or 300 nF/mm², or 500 nF/mm 2 , or 800 nF/mm 2 , or 1000 nF/mm 2 , or 1200 nF/mm 2 may be provided.

[0028] Various embodiments may provide a design and a method of fabricating a capacitor arrangement using localized selective recessing of conductive layers or metal layers. The method may include forming a stack of layers. The process of forming the stack of layers include forming a plurality of first conductive layers, forming a plurality of second conductive layers and forming a plurality of capacitive isolation layers, such that the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers. In various embodiments, the stack of layers may be formed layer-by-layer sequentially. One layer may be formed at one time and a subsequent layer formed thereon and the process is repeated until the required number of layers is formed in the stack of layers. [0029] Subsequently, a portion is removed from an end of each of the plurality of the first conductive layers, thereby creating a plurality of first recesses within the stack of layers. In addition, a portion is removed from an end of each of the plurality of the second conductive layers, thereby creating a plurality of second recesses within the stack of layers. In various embodiments, the ends of the plurality of the first conductive layers and the ends of the plurality of the second conductive layers where portions are removed, are arranged on opposite sides. In various embodiments, removal of the portions from the ends of the first conductive layers and the ends of the second conductive layers may be carried out using a selective etching process.

[0030] In various embodiments, the plurality of first recesses corresponding to the removed portions from the ends of the first conductive layers may be partly filled with a capacitive isolation material or any other dielectric material. In various embodiments, the plurality of second recesses corresponding to the removed portions from the ends of the second conductive layers may be partly filled with a further or second capacitive isolation material or any other dielectric material. In various embodiments, the capacitive isolation material and the further capacitive isolation material may be of the same or different materials. In various embodiments, the capacitive isolation material and the further capacitive isolation material may be of the same or different materials from the material of the capacitive isolation layers.

[0031] Various embodiments may provide a capacitor arrangement and a method of forming a capacitor arrangement where one set of contacts or contact pads, for example a first contact and a second contact, is used to contact the plurality of conductive layers, thereby enabling a small footprint. In various embodiments, the capacitor arrangement may include a trench capacitor, a high aspect ratio capacitor or a planar capacitor.

[0032] As examples and not limitations, in various embodiments, an end of each of the first conductive layers are electrically connected or in electrical communication, either directly or indirectly, with the first contact, and the opposite end of each of the first conductive layers are electrically isolated from the second contact, for example by the capacitive isolation layers. In addition, an end of each of the second conductive layers are electrically connected or in electrical communication, either directly or indirectly, with the second contact, and the opposite end of each of the second conductive layers are electrically isolated from the first contact, for example by the capacitive isolation layers. Providing a common contact (ie. a single contact) for the plurality of like conductive layers provides , a much smaller footprint and much less process steps and hence may provide higher density of capacitance at low cost.

[0033] Various embodiments may provide a method of forming a capacitor arrangement, which includes conformal deposition of a stack of layers including a plurality of first conductive layers (eg. metal layers), a plurality of second conductive layers (eg. metal layers) and a plurality of capacitive isolation layers (eg. dielectric layers). Some of the processes that may be used to deposit these layers may include, but not limited to physical vapor deposition (PVD) and atomic layer deposition (ALD). Subsequently, a localized selective etching or recessing of the plurality of layers of the first conductive layers and the second conductive layers may be carried out. After the selective local recess process, planarization of the capacitor arrangement may be carried out and contacts, such as contact pads, may be formed, for example through metallization of the contacts.

[0034] Such a method advantageously allows flexibility in the thickness of the MIM layers as the thickness is not limited by lithography resolution and overlay. Therefore, very thin layers of the metal and dielectric layers may be provided or deposited. This enables multiple layers of alternating dielectric layers to be formed in between the metal layers, such that high density MIM capacitors may be provided. In addition, by employing a selective local recess process step, a single contact may be provided for all the metal layers of the same material, which enables a compact footprint.

[0035] In various embodiments, in order to increase the capacity density further, wafers with the multi-layer MIM capacitors may be stacked together to increase the number of layers of the metal layers (ie. conductive layers) and the dielectric layers (ie. capacitive isolation layers) in the capacitor arrangement. The plurality of the metal layers (ie. conductive layers), including a plurality of first metal layers (ie. first conductive layers) and a plurality of second metal layers (ie. second conductive layers), may then be wire- bonded or bonded using through silicon via (TSV) technology to a common pair of contacts or contact pads, such that the plurality of first metal layers may be bonded to a first common contact and the plurality of second metal layers may be bonded to a second common contact in the wafer stack.

[0036] Various embodiments may provide a capacitor arrangement with a substrate. The substrate may be silicon. The substrate (eg. silicon) may be doped to form an electrode. In addition or alternatively, a metal may be provided on the substrate to form an electrode or a further electrode. A plurality of layers of two different metals may be sequentially deposited with a dielectric layer in between, on or over the substrate, for example on or over a planar surface of the substrate in a planar configuration.

[0037] Various embodiments may include a process for etching of a trench in the substrate, using typical CMOS processes. A plurality of layers of two different metals may then be sequentially deposited with a dielectric layer in between, on or over the substrate and/or in the trench. Therefore, the trench may be completely filled with the plurality of layers of the different metals and the dielectric.

[0038] In various embodiments, the multi-layer or the plurality of the layers of different metals with the dielectric layer in between, deposited on the substrate in a planar configuration or in a trench, forms MIM capacitors.

[0039] In various embodiments, a contact may be provided for electrical communication or to be electrically connected to the plurality of like layers of one metal and another contact may be provided for electrical communication or to be electrically connected to the plurality of like layers of the other metal such that the capacitor arrangement may act or function as a single capacitor having a capacitive storage density dependent on the number of the plurality of the layers of the different metals and the dielectric (ie. the maximum possible capacity). Such a capacitor arrangement functioning as a single capacitor may be equivalent to a parallel connection of all the MIM layers in the capacitor arrangement.

[0040] In various embodiments, in order to achieve parallel connection of the MIM layers, the ends of the plurality of layers of the two different metals are exposed. In a planar configuration, the plurality of the different metals with a dielectric layer in between are deposited on a planar surface of a substrate and the ends of the plurality of the different metals may be exposed through a respective window or opening formed in or through the plurality of layers. In the case of a trench capacitor arrangement, the plurality of the different metals are exposed through a window or an opening of the trench, for example by polishing the deposited plurality of layers of different metals with a dielectric layer in between, from the top, to create ends of the plurality of layers of different metals in the trench.

[0041] Subsequently, in various embodiments, the plurality of layers of different metals are etched selective to each other. For example, an end of the plurality of layers of one metal positioned on one side of the trench, may be selectively etched, while an end of the plurality of layers of the other metal positioned on the opposite side of the trench, may be selectively etched. A sequence of dielectric layer deposition, polishing and etch back may then be carried out to isolate the etched plurality of layers of the different metals. Contacts or contact pads, for example metal wires, are then connected to the ends of the plurality of layers of the different metals which are not etched and isolated, and therefore exposed, using subtractive or additive metallization process. Therefore, the MIM layers may be connected in parallel as on one side of the trench, the plurality of layers of one metal is electrically connected with each other to a contact (eg. a first wire) and on the opposite side of the trench, the plurality of layers of the other metal is electrically connected with each other to another contact (eg. a second wire).

[0042] Various embodiments may provide a capacitor arrangement including a plurality of conductive layers to increase the surface area of the capacitor arrangement, and therefore the capacitance. Various embodiments may provide a common contact for a plurality of conductive layers (eg. metal layers) of the same material, irrespective of the structure or configurations (eg. a trench) where the plurality of conductive layers are provided in or on. Advantageously, the various embodiments may not require the formation of other structures, for example pillars, recessed in the trench. Various embodiments may provide a capacitor arrangement which may include one or more trenches and the overlaying of dielectric layers and electrically conducting layers in the one or more trenches to form a multi-layer high density capacitor. In various embodiments, an alternating sequence of dielectric layers and electrically conducting layers may be provided. As an example and not limitations, two dielectric layers and more than two (eg. three) electrically conductive layers may be provided. [0043] Various embodiments may provide a capacitor arrangement formed on or over a substrate. In the context of various embodiments, the substrate may include, but not limited to a material such as silicon, poly silicon, silicon germanium, silicon carbide, sapphire and glass. However, it should be appreciated that the substrate may be of any material. In various embodiments, the substrate may be doped with n-type dopants, for example phosphorus or arsenic, or p-type dopants, for example boron.

[0044] In various embodiments, the substrate may be flat. A flat substrate may mean a substrate having at least one planar surface. The stack of layers may be arranged over the substrate. In various embodiments, a first dielectric layer may be provided on the substrate, prior to deposition of the stack of layers including the MIM layers on or over the substrate. In various embodiments, a second dielectric layer may be provided over the deposited stack of layers. The first dielectric layer and the second dielectric layer may be silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide or other high-K dielectrics. In various embodiments, the first dielectric layer includes substantially the same material or of a different material to the material of the second dielectric layer. In various embodiments, each of the first dielectric layer and the second dielectric layer includes substantially the same material or of a different material to the material of the capacitive isolation layers. For example, the second dielectric layer may be silicon dioxide while the first dielectric layer and/or the capacitive isolation layers, may be silicon dioxide or another high-κ dielectric material.

[0045] In various embodiments, the substrate may include one or more trenches, . for example formed or etched in the substrate. In various embodiments, a dielectric layer, may be provided on the substrate and in the one or more trenches, prior to deposition of the stack of layers including the MIM layers. In various embodiments, a second dielectric layer may be provided over the deposited stack of layers. The first dielectric layer and the second dielectric layer may be silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide or other high-κ dielectrics. In various embodiments, the first dielectric layer includes substantially the same material or of a different material to the material of the second dielectric layer. In various embodiments, each of the first dielectric layer and the second dielectric layer includes substantially the same material or of a different material to the material of the capacitive isolation layers. For example, the second dielectric layer may be silicon dioxide while the first dielectric layer and/or the capacitive isolation layers, may be silicon dioxide or another high-κ dielectric material.

[0046] In various embodiments, the first dielectric layer and the second dielectric layer may be part of the stack of layers including the ΜΪΜ layers.

[0047] In various embodiments, one or more films (eg. thick or thin films) may be deposited on the substrate such that the one or more films are disposed on or over the substrate, for example, in between the substrate and the stack of layers. The one or more films may be conducting films and/or non-conducting films (eg. silicon dioxide or silicon nitride). In various embodiments, the conducting films may have substantially the same material as that of the first conductive layers or the second conductive layers. Nonconducting dielectric films may have substantially the same material as that of the capacitive isolation layers. In various embodiments, one or more trenches may then be formed or etched into the one or more films deposited on the substrate. The one or more trenches may be formed completely or partially through the one or more films. In various embodiments, the one or more trenches may be etched partially into the substrate. In various embodiments, the stack of layers may be partly arranged in the trench.

[0048] In various embodiments, a mask including a structure configured for forming a trench may be provided, for example over the substrate or the one or more films disposed on the substrate. The mask may be provided to cover completely or partially a top surface of the substrate or the one or more films.

[0049] In the context of various embodiments, the term 'trench' may mean a depression such that a trench formed, for example, in a substrate may mean a depression formed in the substrate. The term 'trench' may also be used interchangeably with the same meaning as the terms "hole" or "well" and the likes. In various embodiments, the trench may have a larger dimension in terms of its depth compared to its width. Accordingly, the trench may be a trench with a high aspect ratio (ie. aspect ratio = depth:width). In various embodiments, the trench may have an aspect ratio in the range of approximately 1 : 1 to 100: 1, for example in the range of approximately 1: 1 to 80: 1, approximately 1:1 to 60: 1, approximately 1: 1 to 50: 1, approximately 1: 1 to 20:1, approximately 1: 1 to 10: 1, approximately 5: 1 to 100: 1, approximately 5: 1 to 50:1, approximately 5: 1 to 20: 1 or approximately 20: 1 to 100: 1, such that the trench may have an aspect ratio of approximately 1 : 1, approximately 5: 1, approximately 10: 1, approximately 15: 1, approximately 20: 1, approximately 30: 1, approximately 50: 1, approximately 80: 1 or approximately 100: 1.

[0050] In various embodiments, the width of the trench may decrease with increasing trench depth, or the width of the trench may remain constant or at least substantially constant with increasing trench depth. In various embodiments, the bottom surface of the trench may be at least substantially flat or U shaped.

[0051] In the context of various embodiments, the term "contact" may mean a contact region where electrical signals, for example a voltage or a current, may be provided. Accordingly, the term "contact" may include electrical contacts, contact pads and the likes. In various embodiments, the contact or contacts may be in the form of a wire.

[0052] In various embodiments, one or more contacts may be provided in electrical communication with the plurality of conductive layers or the plurality of metal layers. In various embodiments, a set of contacts having two contacts may be provided, such that a first contact is in electrical communication with a plurality of first conductive layers (eg. first metal layers) and a second contact is in electrical communication with a plurality of second conductive layers (eg. second metal layers). In various embodiments, the first contact and the second contact may be contact pads, respectively.

[0053] In various embodiments, the first contact may include, but not limited to a material such as doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer. In various embodiments, the metal may include, but not limited to titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr) and copper (Cu). In various embodiments, the metal nitride may include, but not limited to titanium nitride (TiN), tantalum nitride (TaN) and hafnium nitride (HfN). In various embodiments, the metal silicide may include, but not limited to nickel silicide (NiSi) and titanium silicide (TiSi).

[0054] In various embodiments, the second contact may include, but not limited to a material such as doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer. In various embodiments, the metal may include, but not limited to titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr) and copper (Cu). In various embodiments, the metal nitride may include, but not limited to titanium nitride (TiN), tantalum nitride (TaN) and hafnium nitride (HfN). In various embodiments, the metal silicide may include, but not limited to nickel silicide (NiSi) and titanium silicide (TiSi).

[0055] In various embodiments, the first contact may include a material that is substantially the same material as that for the second contact or a different material than the material of the second contact. In various embodiments, deposition of the first contact and the second contact may be carried out simultaneously. In embodiments where deposition of the first contact and the second contact is cariied out simultaneously, the material of the first contact and the second contact may be the same.

[0056] In various embodiments where the stack of layers is formed over the substrate, the first contact and the second contact may be respectively positioned on a same or different vertical position as the vertical position of a surface of the substrate. In various embodiments where one or more films are disposed between the substrate and the stack of layers, the first contact and the second contact may be respectively positioned on a same or different vertical position as the vertical position of a surface of the one or more films (ie. a top surface of the one or more films).

[0057] In the context of various embodiments, the term 'conductive layer' may mean a layer of conductive material or a layer having a material having the property of conductivity. Therefore, charged particles, for example electrons, may at least substantially travel through the conductive layer. In various embodiments, a plurality of conductive layers may be provided. The plurality of conductive layers may include a plurality of first conductive layers and a plurality of second conductive layers.

[0058] In various embodiments, each of the first conductive layers may include, but not limited to a material such as doped silicon, doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer. In various embodiments, the metal may include, but not limited to titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr) and copper (Cu). In various embodiments, the metal nitride may include, but not limited to titanium nitride (TiN), tantalum nitride (TaN), and hafnium nitride (HfN). In various embodiments, the metal silicide may include, but not limited to nickel silicide (NiSi) and titanium silicide (TiSi). [0059] In various embodiments, each of the second conductive layers may include, but not limited to a material such as doped silicon, doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer. In various embodiments, the metal may include, but not limited to titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr) and copper (Cu). In various embodiments, the metal nitride may include, but not limited to titanium nitride (TiN), tantalum nitride (TaN) and hafnium nitride (HfN). In various embodiments, the metal silicide may include, but not limited to nickel silicide (NiSi) and titanium silicide (TiSi).

[0060] In various embodiments, each of the first conductive layers includes a different material from the material of each of the second conductive layers. This enables the first conductive layers and the second conductive layers to be selectively etched with respect to each other. In other words, the first conductive layers may be etched selective to the second conductive layers (ie. the first conductive layers is etched while the second conductive layers is not etched) and the second conductive layers may be etched selective to the first conductive layers (ie. the first conductive layers is not etched while the second conductive layers is etched). In various embodiments, etching may be carried out using dry or wet processes.

[0061] In the context of various embodiments, the term 'capacitive isolation layer' may include an insulator layer, a dielectric layer or the likes. The term 'capacitive isolation layer' may mean a layer having a capacitive isolation material or a dielectric material or an insulating material, such that charged particles, for example electrons, may not substantially travel through the capacitive isolation layer. In various embodiments, a plurality of capacitive isolation layers may be provided. In various embodiments, a capacitive isolation layer is placed in between two neighbouring conductive layers to provide electrical isolation between the two neighbouring conductive layers. Such an arrangement may be equivalent to a capacitor.

[0062] In various embodiments, each of the capacitive isolation layers may include, but not limited to a material such as silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide or other high-κ dielectrics or ultra high-κ dielectrics.

[0063] In the context of various embodiments, after the deposition of the stack of layers, a planarization process may be performed. In various embodiments where a trench is formed in the substrate or the one or more films disposed on a substrate, a planarization process may be carried out such that a top surface of the parts of the substrate or the one or more films surrounding the trench are exposed. In various embodiments where a mask is provided for forming the trench, the planarization process may be carried out such that the mask surrounding the trench is exposed.

[0064] In order that the invention may be readily understood and put into practical effect, particular embodiments will now be described by way of examples and not limitations, and with reference to the figures. It should be appreciated that while the embodiments illustrated in the figures show that a stack of layers are formed over the substrate such that the stack of layers is in contact with the substrate, one or more films of conducting films and/or non-conducting films may be disposed between the substrate and the stack of layers. Accordingly, descriptions with respect to the figures may be similarly applicable to various embodiments including the one or more films, for example descriptions relating to the configuration of the trenches.

[0065] In various embodiments, the capacitor arrangement of various embodiments may be fabricated in a backend process or a post back end process on a wafer, where the wafer may include a dielectric layer on the wafer and a number of metal lines embedded in the dielectric layer in electrical communication with circuits which may be provided underneath the dielectric layer on the wafer.

[0066] FIG. 1A shows a schematic block diagram of a capacitor arrangement 100, according to one embodiment. The capacitor arrangement 100 may include a substrate 102, a first contact 104 disposed over the substrate 102, a second contact 106 disposed over the substrate 102 and a stack of layers 108. The stack of layers 108 may include a plurality of first conductive layers 110, a plurality of second conductive layers 1 12 and a plurality of capacitive isolation layers 1 14. In various embodiments, the first contact 104 and the second contact 106 may be respectively positioned on a same or different vertical position as the vertical position of a surface of the substrate 102.

[0067] In various embodiments, the capacitor arrangement 100 may be configured such that the first conductive layers 110, the second conductive layers 112 and the capacitive isolation layers 114 alternate with each other such that, between two neighboring first conductive layers 110, one second conductive layer is disposed, and wherein the first conductive layers 110 and the second conductive layers 112 are isolated from each other by the capacitive isolation layers 114.

[0068] In various embodiments, the capacitor arrangement 100 may be further configured such that the first conductive layers 110 are electrically connected with the first contact 104 and electrically isolated from the second contact 106 and the second conductive layers 112 are electrically connected with the second contact 106 and electrically isolated from the first contact 104.

[0069] In various embodiments, the stack of layers 108 may be arranged over the substrate 102. In various embodiments, the substrate 102 may be a flat substrate or a substantially flat substrate.

[0070] In various embodiments, the substrate 102 may have any shapes, for example a square or a rectangular configuration. In various embodiments, the substrate 102 may have a trench or a plurality of trenches, for example two trenches, three trenches, four trenches or any number of trenches.

[0071] FIG. IB shows a schematic block diagram of a capacitor arrangement 130, according to one embodiment. The capacitor arrangement 130 may include some of the same features as that of the capacitor arrangement 100 as illustrated in the embodiment of FIG. 1A. Therefore, the descriptions of the arrangement, configuration and various embodiments of the capacitor arrangement 100 of FIG. 1A may be similarly applicable here for the capacitor arrangement 130 for like features present in the capacitor arrangement 100 of FIG. 1A and the capacitor arrangement 130 of FIG. IB, and hence descriptions will not be presented here for the like features for the capacitor arrangement 130 of FIG. IB.

[0072] In various embodiments of the capacitor arrangement 130, the substrate 102 may include a trench 1 16. In various embodiments, the capacitor arrangement 130 may be configured such that the stack of layers 108 may be partly arranged in the trench 1 16.

[0073] In various embodiments, the trench 116 of the substrate 102 may include a trench opening 118. In various embodiments, the trench opening 118 may include a first trench opening area 120 and a second trench opening area 122. The second trench opening area 122 is different from the first trench opening area 120. [0074] In various embodiments, the first contact 104 may be arranged over the first trench opening area 120 and the second contact 106 may be arranged over the second trench opening area 122.

[0075] In various embodiments, the width of the trench 116 may remain at least substantially constant with increasing trench depth. In other words, the width of the trench 116 remain at least substantially the same in the direction of the depth of the trench 116.

[0076] In alternate embodiments, the width of the trench 1 16 may decrease with increasing trench depth. In other words, the width of the trench 116 decreases or tapers in the direction of the depth of the trench 116. Accordingly, the walls of the trench 116 are inclined planes and may form a wedge shape.

[0077] FIG. 2A shows a schematic side view of a capacitor arrangement 200, according to one embodiment. The capacitor arrangement 200 includes a substrate 202, with a top surface 203, and a trench 204 formed in the substrate 202. The capacitor arrangement 200 includes a stack of layers 205. The stack of layers 205 may include a plurality of first conductive layers 208a, 208b, 208c, a plurality of capacitive isolation layers 209a, 209b, 209c, 209d, 209e, and a plurality of second conductive layers 210a, 210b, 210c. The capacitor arrangement 200 may include a first dielectric layer 206 and a second dielectric layer 21 1. In alternate embodiments, the first dielectric layer 206 and the second dielectric layer 211 may form part of the stack of layers^:205.

[0078] In various embodiments, the stack of layers 205 may have a substantially U-like shape. In various embodiments, the stack of layers 205 may at least substantially completely fill the trench 204. In various embodiments, the surface of the stack of layers 205, including the ends of the plurality of first conductive layers 208a, 208b, 208c, the plurality of capacitive isolation layers 209a, 209b, 209c, 209d, 209e, and the plurality of second conductive layers 210a, 210b, 210c, may be at least substantially flushed with or level or at the same plane as the surface 203 of the substrate 202.

[0079] In various embodiments, the stack of layers 205 is provided or deposited in the trench 204 via conformal depositions. After deposition of the first dielectric layer 206, the stack of layers 205 is deposited layer-by-layer sequentially, such that the first conductive layer 208a is deposited, followed by the capacitive isolation layer 209a, the second conductive layer 210a, until the second conductive layer 210c is deposited to complete the deposition of the stack of layers 205. Subsequently, the second dielectric layer 211 is deposited. In various embodiments, the first dielectric layer 206 and the second dielectric layer 211 may be of the at least substantially same material or of a different material to the material of the capacitive isolation layers 209a, 209b, 209c, 209d, 209e. For example, the second dielectric layer 211 may be silicon dioxide while the capacitive isolation layers 209a, 209b, 209c, 209d, 209e, may be silicon dioxide or another high-k dielectric material.

[0080] Subsequently, a localized selective recessing of the plurality of first conductive layers 208a, 208b, 208c, and the plurality of second conductive layers 210a, 210b, 210c is carried out. After the selective local recess process, planarization of the capacitor arrangement 200 is carried out and contacts, such as contact pads, may be formed, for example through metallization of contacts. The capacitor arrangement 212 illustrated in FIG. 2B shows the completed structure, including a first contact 214a and a second contact 214b. In the embodiment of FIG. 2B, the first contact 214a and the second contact 214b are respectively positioned on the same vertical position as the vertical position of the surface 203 of the substrate 202. In other words, the bottom surfaces 215a, 215b respectively of the first contact 214a and the second contact 214b are respectively positioned on at least substantially the same plane as the surface 203 of the substrate 202.

[0081] As can be seen in FIG. 2B, the plurality of first conductive layers 208a, 208b, 208c, have been selectively etched to remove a portion from one end of each of the plurality of first conductive layers 208a, 208b, 208c. The plurality of second conductive layers 210a, 210b, 210c, have also been selectively etched to remove a portion from one end of each of the plurality of second conductive layers 210a, 210b, 210c. In various embodiments, after the plurality of first conductive layers 208a, 208b, 208c, and the plurality of second conductive layers 210a, 210b, 210c, have been selectively etched, recesses are formed in the etched or removed portions. The recesses may then be at least partly filled with a capacitive isolation material which may be of a same or different material from the capacitive isolation layers 209a, 209b, 209c, 209d, 209e. [0082] In various embodiments, the first contact 214a is electrically connected with the plurality of first conductive layers 208a, 208b, 208c, and the second contact 214b is electrically connected with the plurality of second conductive layers 210a, 210b, 210c.

[0083] FIG. 2C shows a partially exploded view of the capacitor arrangement 212 of the embodiment of FIG. 2B. For ease of illustration and for clarity purposes, in FIG. 2C, the first dielectric layer 206, the second dielectric layer 211 and the plurality of capacitive isolation layers 209a, 209b, 209c, 209d, 209e are collectively represented as 209, the plurality of first conductive layers 208a, 208b, 208c are collectively represented as 208, and the plurality of second conductive layers 210a, 210b, 210c are collectively represented as 210.

[0084] In various embodiments, each of the first conductive layers 208 includes a first end 216a and a second end 216b, where the second end 216b is arranged opposite to the first end 216a. In FIG. 2C, the second ends 216b of the first conductive layers 208 have been selectively etched and each etched portion at least partly filled with a layer of a capacitive isolation material. In various embodiments, each of the second conductive layers 210 includes an end (termed as a third end hereinafter) 218a and another end (termed as a fourth end hereinafter) 218b, where the fourth end 218b is arranged opposite to the third end 218a. In FIG. 2C, the fourth ends 218b of the second conductive layers 210 have been selectively etched and each etched portion at least partly filled with a layer of a capacitive isolation material.

[0085] In various embodiments, the first ends 216a of the first conductive layers 208 are respectively in electrical communication or electrically connected with the first contact 214a, and the second ends 216b of the first conductive layers 208 are respectively electrically isolated from the second contact 214b. In various embodiments, the second ends 216b of the first conductive layers 208 may be respectively electrically isolated from the second contact 214b by the capacitive isolation layers 209.

[0086] In various embodiments, the third ends 218a of the second conductive layers 210 are respectively in electrical communication or electrically connected with the second contact 214b, and the fourth ends 218b of the second conductive layers 210 are respectively electrically isolated from the first contact 214a. In various embodiments, the fourth ends 218b of the second conductive layers 210 may be respectively electrically isolated from the first contact 214a by the capacitive isolation layers 209.

[0087] As illustrated in FIG. 2C, the trench 204 may include a trench opening 220. The trench opening 220 may include a first trench opening area, as represented by the dotted box 222a, and a second trench opening area, as represented by the dotted box 222b, where the second trench opening area 222b is different from the first trench opening area 222a. While each of the first trench opening area 222a and the second trench opening area 222b is illustrated having the particular size, shape and position as shown in the embodiment of FIG. 2C, it should be appreciated that each of the first trench opening area 222a and the second trench opening area 222b may cover an area of any shape and/or size and/or may be at a different position.

[0088] In various embodiments, the stack of layers 205 having an U-like shape may be configured or arranged with the first ends 216a of the first conductive layers 208 ending within the first trench opening area 222a, and the third ends 218a of the second conductive layers 210 ending within the second trench opening area 222b.

[0089] In various embodiments, the second ends 216b of the first conductive layers 208 may end within the second trench opening area 222b and the fourth ends 218b of the second conductive layers 210 may end within the first trench opening area 222a.

[0090] In various embodiments, the first contact 214a may be arranged over the first trench opening area 222a, and the second contact 214b may be arranged over the second trench opening area 222b.

[0091] In the embodiments illustrated in FIGS. 2A to 2C, only three layers of the first conductive layers and three layers of the second conductive layer, with a capacitive isolation layer in between two neighbouring conductive layers, are shown for ease of illustration and clarity purposes. It should be appreciated that any number of the layers of the first conductive layers and the second conductive layers may be provided. For example, five layers of the first conductive layer and five layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, or ten layers of the first conductive layer and ten layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, may be provided. In various embodiments, increasing the number of layers of the first conductive layer and the second conductive layer may increase the capacitance of the capacitor arrangement.

[0092] FIG. 3 shows a flow chart 300 illustrating a method of forming a capacitor arrangement, according to various embodiments.

[0093] At 302, a first contact is formed over a substrate.

[0094] At 304, a second contact is formed over the substrate.

[0095] At 306, a stack of layers is formed over the substrate. In various embodiments, in order to form the stack of layers, a plurality of first conductive layers is formed, a plurality of second conductive layers is formed and a plurality of capacitive isolation layers is formed, wherein the first conductive layers, the second conductive layers and the capacitive isolation layers are alternated with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers, and wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact.

[0096] FIG. 4A shows a schematic cross-sectional view of a substrate 400, according to various embodiments. The substrate 400 may be used for the manufacturing of a capacitor arrangement of various embodiments.

[0097] In various embodiments, the substrate 400 has a top surface 402 and two trenches 404a, 404b, formed in the substrate 400. In various embodiments, etching may be performed on the substrate 400 to form the two trenches 404a, 404b (ie. trench etch). While two trenches 404a, 404b, are illustrated in FIG. 4A, it should be appreciated that the substrate 400 may have any number of trenches formed in the substrate 400.

[0098] Using trench 404a as an example, the etched trench 404a includes a trench opening 406, a bottom surface 410, a first side wall 408a and a second side wall 408b, which are at least substantially parallel to each other and on opposite sides of the trench 404a. The trench opening 406 includes a first trench opening area 407a and a second trench opening area 407b, being different from the first trench opening area 407a (ie. first trench opening area 407a and a second trench opening area 407b are different trench opening areas). The trench 404a may have a width, w, and a depth, d. In various embodiments, the width, w, of the trench 404a remains at least substantially constant with increasing trench depth, d.

[0099] In various embodiments, the width, w, may be in approximately 0.2 μπι to 100 μπι, for example approximately 0.2 μπι to 50 μπι, approximately 0.2 μπι to 20 μηι, approximately 10 μπι to 100 μπι or approximately 10 μπι to 50 μπι, such that the width, w, may be approximately 0.2 μπι, approximately 1 μπι, approximately 5 μιη, approximately 10 μπι, approximately 20 μηι, approximately 50 μπι or approximately 100 μπι. In various embodiments, the width, w, may be more than 100 μπι (ie. > 100 μm). In various embodiments, the depth, d, may be in approximately 0.5 μιη to 100 um, for example approximately 0.5 μm to 50 μπι, approximately 0.5 μm to 20 μπι, approximately 10 m to 100 μιη or approximately 10 μιη to 50 μηι, such that the depth, d, may be approximately 0.5 μπι, approximately 1 μπι, approximately 5 μm, approximately 10 μπι, approximately 20 μηι, approximately 50 μιη or approximately 100 μηι. In various embodiments, the depth, d, may be more than 100 μπι (ie. > 100 μπι).

[0100] It should be appreciated that the descriptions and explanation with respect to trench 404a may be similarly applicable to trench 404b.

[0101] While each of the first trench opening area 407a and the second trench opening area 407b is illustrated having the particular size, shape and position as shown in the embodiment of FIG. 4A, it should be appreciated that each of the first trench opening area 407a and the second trench opening area 407b may cover an area of any shape and/or or size and/or may be at a different position.

[0102] FIG. 4B shows a schematic cross-sectional view of a substrate 420, according to various embodiments. The substrate 420 may be used for the manufacturing of a capacitor arrangement of various embodiments.

[0103] In various embodiments, the substrate 420 has a top surface 422 and two trenches 424a, 424b, formed in the substrate 420. In various embodiments, etching may be performed on the substrate 420 to form the two trenches 424a, 424b (ie. trench etch). While two trenches 424a, 424b, are illustrated in FIG. 4B, it should be appreciated that the substrate 420 may have any number of trenches formed in the substrate 420. [0104] Using trench 424a as an example, the etched trench 424a includes a trench opening 426, a bottom surface 430, a first side wall 428a and a second side wall 428b, which are on substantially opposite sides of the trench 424a. The trench opening 426 includes a first trench opening area 427a and a second trench opening area 427b, being different from the first trench opening area 427a (ie. first trench opening area 427a and a second trench opening area 427b are different trench opening areas). The trench 424a may have a depth, d, the trench opening 426 may have a width, wl, and the bottom surface 430 may have a width, w2, where w2 is less than wl (ie. w2 < wl). Therefore, the width of the trench 424a decreases with increasing trench depth, d. In other words, the width of the trench 424a decreases or tapers in the direction of the depth, d, of the trench 424a. Accordingly, the first side wall 428a and the second side wall 428b, of the trench 424a are inclined planes and may form a wedge shape.

[0105] In various embodiments, the widths, wl and w2, or a ratio of the widths, wl and w2, may be provided such that the first side wall 428a and the second side wall 428b may be inclined to the bottom surface 430 at an angle approximately 45° to 90° (where wl = w2 for the angle of 90°), for example, approximately 45° to 80°, approximately 45° to 60° or approximately 60° to 90°, such that the sngle may be approximately 45°, approximately 60° or approximately 80°. In various embodiments, the depth, d, may be in approximately 0.5 μπι to 100 μπι, for example approximately 0.5 μηι to 50 μπι, approximately 0.5 μπι to 20 μπι, approximately 10 μιη to 100 μιη or approximately 10 μπι to 50 μιη, such that the depth, d, may be approximately 0.5 μπι, approximately 1 μπι, approximately 5 μπι, approximately 10 μπι, approximately 20 μπι, approximately 50 μπι or approximately 100 μιη. In various embodiments, the depth, d, may be more than 100

[0106] It should be appreciated that the descriptions and explanation with respect to trench 424a may be similarly applicable to trench 424b.

[0107] While each of the first trench opening area 427a and the second trench opening area 427b is illustrated having the particular size, shape and position as shown in the embodiment of FIG. 4B, it should be appreciated that each of the first trench opening area 427a and the second trench opening area 427b may cover an area of any shape and/or size and/or may be at a different position.

[0108] In various embodiments, tapered trenches may be used to facilitate the filling of MIM layers in the trenches.

[0109] FIGS. 4C to 4H show cross-sectional views of a fabrication process to manufacture a capacitor arrangement, according to various embodiments.

[0110] As an example and not limitations, the substrate 400 of FIG. 4A is used for illustration of the fabrication process of FIGS. 4C to 4H. The substrate 400 may be silicon. In various embodiments, the substrate 400 may be coated with a first dielectric layer 442.

[0111] In various embodiments, a multiple deposition process is then carried out to deposit a stack of layers 440 having MIM layers, on or over the substrate 400 and partly arranged in the trenches 404a, 404b. Therefore, the stack of layers 440 is also deposited into the trenches 404a, 404b. In various embodiments, the stack of layers 440 having MIM layers includes a plurality of first conductive layers 444a, 444b, a plurality of capacitive isolation layers 446a, 446b, 446c, and a plurality of second conductive layers 448a, 448b. The stack of layers 440 has a substantially U-like shape in the the trenches 404a, 404b, and may at least substantially fill the trenches 404a, 404b. The material of the plurality of first conductive layers 444a, 444b, differs from the material of the plurality of second conductive layers 448a, 448b.

[0112] In various embodiments, the stack of layers 440 may be provided or deposited via conformal depositions. The stack of layers 440 is deposited layer-by-layer sequentially, such that the first conductive layer 444a is deposited, followed by the capacitive isolation layer 446a, the second conductive layer 448a, until the second conductive layer 448b is deposited to complete the deposition of the stack of layers 440. Subsequently, the second dielectric layer 450 is deposited. The first dielectric layer 442 and the second dielectric layer 450 may be of the substantially same material or of a different material to the material of the capacitive isolation layers 446a, 446b, 446c. FIG. 4C shows the structure 452 that is formed. In alternate embodiments, the first dielectric layer 442 and the second dielectric layer 450 may form part of the stack of layers 440. [0113] Subsequently, chemical-mechanical polishing (CMP), etching or a planarization process is carried out from the top of the structure 452 (FIG. 4C) to remove the layers of the plurality of first conductive layers 444a, 444b, the plurality of capacitive isolation layers 446a, 446b, 446c, the plurality of second conductive layers 448a, 448b, and the second dielectric layer 450 down to the first dielectric layer 442. Alternatively, the planarization process may be performed such that the top surface 402 of the parts of the substrate 400 surrounding the trenches 404a, 404b, are exposed, similar to the embodiment of FIG. 2A. FIG. 4D shows the structure 456 that is formed.

[0114] For ease of illustration and for clarity purposes, in FIGS. 4D to 4H, the plurality of capacitive isolation layers 446a, 446b, 446c are collectively represented as 446, the plurality of first conductive layers 444a, 444b are collectively represented as 444, and the plurality of second conductive layers 448a, 448b are collectively represented as 448.

[0115] As shown in FIG. 4D, after the planarization process, the ends of the plurality of first conductive layers 444, the plurality of capacitive isolation layers 446, and the plurality of second conductive layers 448, are exposed and are on the substantially same level as the surface 457 of the first dielectric layer 442. As shown in the embodiment of FIG. 4D, the first conductive layers 444 are formed such that each of the first conductive layers 444 includes a first end 458a and a second end 458b, where the second end 458b is arranged opposite to the first end 458a. In addition, the second conductive layers 448 are formed such that each of the second conductive layers 448 includes an end (termed as a third end hereinafter) 460a and another end (termed as a fourth end hereinafter) 460b, where the fourth end 460b is arranged opposite to the third end 460a.

[0116] As illustrated in FIG. 4D, the stack of layers 440 are formed such that the stack of layers 440 has an U-like shape within the trenches 404a, 404b, with the stack of layers 440 configured or arranged with the first ends 458a of the first conductive layers 444 ending within the first trench opening area 407a, the second ends 458b of the first conductive layers 444 ending within the second trench opening area 407b, the third ends 460a of the second conductive layers 448 ending within the second trench opening area 407b, and the fourth ends 460b of the second conductive layers 448 ending within the first trench opening area 407a. [0117] It should be appreciated that the descriptions, explanation and illustrations with respect to trench 404a may be similarly applicable to trench 404b.

[0118] Subsequently, in forming the stack of layers 440, a selective etching process is performed to remove a plurality of first portions from the second ends 458b of the first conductive layers 444, thereby creating a plurality of first recesses 464 within the stack of layers 440. Accordingly, the second ends 458b of the first conductive layers 444 are below the level of the surface 457 of the first dielectric layer 442 and ending within the second trench opening area 407b. FIG. 4E shows the structure 466 that is formed.

[0119] Subsequently, in forming the stack of layers 440, a selective etching process is performed to remove a plurality of second portions from the fourth ends 460b of the second conductive layers 448, thereby creating a plurality of second recesses 470 within the stack of layers 440. Accordingly, fourth ends 460b of the second conductive layers 448 are below the level of the surface 457 of the first dielectric layer 442 and ending within the first trench opening area 407a. FIG. 4F shows the structure 472 that is formed.

[0120] In various embodiments, the selective etching process to etch the second ends 458b of the first conductive layers 444 to create a plurality of first recesses 464 and to etch the fourth ends 460b of the second conductive layers 448 to create a plurality of second recesses 470, may be performed sequentially, or sequentially in reverse order, or simultaneously.

[0121] Subsequently, in forming the stack of layers 440, dielectric deposition is carried out to at least partly fill the first recesses 464 with a capacitive isolation material and the second recesses 470 with a further capacitive isolation material, followed by chemical- mechanical polishing (CMP), an etch back process or a planarization process to remove any excess capacitive isolation material and/or the further capacitive isolation material such that a substantially planar surface is formed on the substantially same level as the surface 457 of the first dielectric layer 442. FIG. 4G shows the structure 476 that is formed. In various embodiments, the capacitive isolation material and the further capacitive isolation material may be of a same or different material from the capacitive isolation layers 446.

[0122] Subsequently, contacts are formed and FIG, 4H shows the structure 480 that is formed. The structure 480 represents the capacitor arrangement of various embodiments. The structure 480 includes a first contact 482a and a second contact 482b formed for each of the stack of layers 440 formed in each of the trenches 404a, 404b, where the first contact 482a is arranged over the first trench opening area 407a, and the second contact 482b is arranged over the second trench opening area 407b. The first contact 482a and the second contact 482b may be, for example, metal or doped poly silicon or metal nitrides.

[0123] In the embodiment of FIG. 4H, the first contact 482a and the second contact 482b are respectively positioned on a different vertical position as the vertical position of the surface 402 of the substrate 400. In other words, the bottom surfaces 484a, 484b respectively of the first contact 482a and the second contact 482b are respectively positioned on a different plane as the surface 402 of the substrate 400. In the embodiment of FIG. 4H, the bottom surfaces 484a, 484b respectively of the first contact 482a and the second contact 482b are respectively positioned on at least substantially the same plane as the surface 457 of the first dielectric layer 442.

[0124] As shown in the embodiment of FIG. 4H, the first contact 482a is formed over the substrate 400 such that the first contact 482a is in electrical communication with or electrically connected to the first ends 458a of the first conductive layers 444 while the second contact 482b is formed over the substrate 400 such that the second contact 482b is in electrical communication with or electrically connected to the third ends 460a of the second conductive layers 448. In addition, the second ends 458b of the first conductive layers 444 are respectively electrically isolated from the second contact 482b and the fourth ends 460b of the second conductive layers 448 are respectively electrically isolated from the first contact 482a.

[0125] In various embodiments, after the formation of the structure 452 (FIG. 4C), a respective portion, as represented by the dotted boxes 453a, 453b, of the stack of layers 440 on opposite ends, may be etched away to produce recesses in the stack of layers 440. Accordingly, the stack of layers 440 includes a first opening, corresponding to the etched portion at the position represented by the dotted box 453a, and a second opening different from the first opening, where the second opening corresponds to the etched portion at the position represented by the dotted box 453b. A selective etching process may then be performed on respective ends of the plurality of first conductive layers 444a, 444b, and the plurality of second conductive layers 448a, 448b, to create a plurality of recesses which are then filled with a capacitive isolation material.

[0126] In alternate embodiments, the selective etching process may be carried out first on the stack of layers 440 on opposite ends to create recesses and the recesses filled with a capacitive isolation material, prior to etching the stack of layers 440 on respective portions, as represented by the dotted boxes 453a, 453b, to create the first opening and the second opening.

[0127] Subsequently, contacts (eg. metals) may be formed in the respective openings, with a contact formed in the first opening, and another contact formed in the second opening. It should be appreciated that the first opening and the second opening may be of any shape and/or size and/or may be at a different position.

[0128] In the embodiments illustrated in FIGS. 4C to 4H, two layers of the first conductive layers and two layers of the second conductive layer, with a capacitive isolation layer in between two neighbouring conductive layers, are shown for ease of illustration and clarity purposes. It should be appreciated that any number of the layers of the first conductive layers and the second conductive layers may be provided. For example, five layers of the first conductive layer and five layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, or ten layers of the first conductive layer and ten layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, may be provided. In various embodiments, increasing the number of layers of the first conductive layer and the second conductive layer may increase the capacitance of the capacitor arrangement.

[0129] In various embodiments relating to the embodiments of FIGS. 2A to 2C and 4A to 4H, one or more films (eg. conducting films and/or non-conducting films) may be disposed between the substrate and the stack of layers, and one or more trenches may be formed or etched in the one or more films. The one or more trenches may also be formed partially in the substrate. The stack of layers may be partly arranged in the one or more trenches. In various embodiments, each trench may include a trench opening, the trench opening comprising a first trench opening area and a second trench opening area being different from the first trench opening area. In various embodiments, the stack of layers may be formed by depositing the stack of layers over the one or more layers such that the stack of layers is also deposited into the trench, and carrying out a planarization process such that a top surface of the parts of the one or more films surrounding the trench are exposed.

[0130] In various embodiments relating to the embodiments of FIGS. 2A to 2C and 4A to 4H, an etching process configured to etch the stack of layers in the trench may be carried out, such that a first side wall and a second side wall of the trench may be partially exposed. Subsequently, the first contact and the second contact may be formed such that the first contact is arranged in contact with a side wall of the trench, and the second contact is arranged in contact with another side wall of the trench, the two side walls being opposite side walls. Using FIGS. 4A to 4H as an example, the first contact 482a may be arranged in contact with the first side wall 408a of the trench 404a and the second contact 482b may be arranged in contact with the second side wall 408b of the trench 404a.

[0131] FIGS. 5A to 5D show cross-sectional views of a fabrication process to manufacture a capacitor arrangement including a stack of layers on a planar wafer or substrate 500, according to various embodiments.

[0132] As shown in FIG. 5A, the substrate 500, used for the manufacture of a capacitor arrangement, is flat, with a stack of layers 502 deposited or arranged over the substrate 500. The substrate 500 has a top surface 504. The substrate 500 may be silicon. The substrate 500 may be coated with a first dielectric layer 506.

[0133] A multiple deposition process is then carried out to deposit the stack of layers 502 having MIM layers, on or over the substrate 500. In various embodiments, the stack of layers 502 having MIM layers includes a plurality of first conductive layers 508a, 508b, a plurality of capacitive isolation layers 510a, 510b, 510c, and a plurality of second conductive layers 512a, 512b. The material of the plurality of first conductive layers 508a, 508b, differs from the material of the plurality of second conductive layers 512a, 512b.

[0134] In various embodiments, the stack of layers 502 may be provided or deposited via conformal depositions. The stack of layers 502 is deposited layer-by-layer sequentially, such that the first conductive layer 508a is deposited, followed by the capacitive isolation layer 510a, the second conductive layer 512a, until the second conductive layer 512b is deposited to complete the deposition of the stack of layers 502. Subsequently, the second dielectric layer 514 is deposited. The first dielectric layer 506 and the second dielectric layer 514 may, be of the substantially same material or of a different material to the material of the capacitive isolation layers 510a, 510b, 510c. FIG. 5 A shows the structure 516 that is formed. In alternate embodiments, the first dielectric layer 506 and the second dielectric layer 514 may form part of the stack of layers 502.

[0135] As shown in the embodiment of FIG. 5 A, the first conductive layers 508a, 508b, are formed such that each of the first conductive layers 508a, 508b includes a first end 518a and a second end 518b, where the second end 518b is arranged opposite to the first end 518a. In addition, the second conductive layers 512a, 512b, are formed such that each of the second conductive layers 512a, 512b includes an end (termed as a third end hereinafter) 520a and another end (termed as a fourth end hereinafter) 520b, where the fourth end 520b is arranged opposite to the third end 520a. The first end 518a of the first conductive layers 508a, 508b are on the at least substantially same vertical plane as the fourth end 520b of the second conductive layers 512a, 512b, while the second end 518b of the first conductive layers 508a, 508b are on the at least substantially same vertical plane as the third end 520a of the second conductive layers 512a, 512b.

[0136] For ease of illustration and for clarity purposes, in FIGS. 5B to 5D, the plurality of capacitive isolation layers 510a, 510b, 510c are collectively represented as 510, the plurality of first conductive layers 508a, 508b are collectively represented as 508, and the plurality of second conductive layers 512a, 512b are collectively represented as 512.

[0137] As shown in the embodiment of FIG. 5B, in forming the stack of layers 502, a selective etching process is then performed to remove a plurality of first portions from the second ends 518b of the first conductive layers 508, thereby creating a plurality of first recesses 522 within the stack of layers 502. Accordingly, the second ends 518b of the first conductive layers 508 are on a different vertical plane to the third end 520a of the second conductive layers 512.

[0138] Subsequently, in forming the stack of layers 502, a selective etching process is performed to remove a plurality of second portions from the fourth ends 520b of the second conductive layers 512, thereby creating a plurality of second recesses 524 within the stack of layers 502. Accordingly, the fourth ends 520b of the second conductive layers 512 are on a different vertical plane to the first end 518a of the first conductive layers 508. FIG. 5B shows the structure 526 that is formed.

[0139] In various embodiments, the selective etching process to etch the second ends 518b of the first conductive layers 508 to create a plurality of first recesses 522 and to etch the fourth ends 520b of the second conductive layers 512 to create a plurality of second recesses 524, may be performed sequentially, or sequentially in reverse order, or simultaneously.

[0140] In alternate embodiments, instead of depositing the stack of layers 502 on the substrate 500 similar to the embodiment of FIG. 5A, and then selectively etching the second ends 518b of the first conductive layers 508 to create a plurality of first recesses 522 and etching the fourth ends 520b of the second conductive layers 512 to create a plurality of second recesses 524 to produce a structure similar to structure 526 of FIG. 5B, the stack of layers 502 may be deposited on the substrate 500 such that the plurality of first recesses 522 and the plurality of second recesses 524 are created as the stack of layers 502 is deposited layer-by- layer sequentially, with the first conductive layers 508 and the second conductive layers 512 having reduced lengths, to produce a structure similar to structure 526 of FIG. 5B. Accordingly, the selective etching process may not be necessary.

[0141] Subsequently, in forming the stack of layers 502, dielectric deposition is carried out on the structure 526 of FIG. 5B to at least partly fill the first recesses 522 with a capacitive isolation material and the second recesses 524 with a further capacitive isolation material, followed by chemical-mechanical polishing (CMP), an etch back process or a planarization process to remove any excess capacitive isolation material and/or the further capacitive isolation material such the filled recesses corresponding to the first recesses 522 are on the at least substantially same vertical plane as the third ends 520a of the second conductive layers 512, and the filled recesses corresponding to the second recesses 524 are on the at least substantially same vertical plane as the first ends 518a of the first conductive layers 508. In various embodiments, the capacitive isolation material and the further capacitive isolation material may be of a same or different material from the capacitive isolation layers 510. FIG. 5C shows the structure 528 that is formed. [0142] Subsequently, contacts are formed on opposite ends of the structure 528. In various embodiments, a respective portion, as represented by the dotted boxes 529a, 529b, of the stack of layers 502 on opposite ends, may be etched away to produce recesses in the stack of layers 502. Accordingly, the stack of layers 502 includes a first opening, corresponding to the etched portion at the position represented by the dotted box 529a, and a second opening different from the first opening, where the second opening corresponds to the etched portion at the position represented by the dotted box 529b. Accordingly, the ends of the plurality of first conductive layers 508, and the ends of the plurality of second conductive layers 512, are exposed. Subsequently, contacts (eg. metals) may be formed in the respective recesses to form the first contact 532a and the second contact 532b. FIG. 5D shows the structure 530 that is formed, where the first contact 532a is arranged in the first opening, and the second contact 532b is arranged in the second opening. It should be appreciated that the first opening and the second opening may be of any shape and/or size and/or may be at a different position.

[0143] The structure 530 represents the capacitor arrangement of various embodiments. The structure 530 includes a first contact 532a and a second contact 532b. The first contact 532a and the second contact 532b may be, for example interconnects or contact pads having a material such as, for example, metal or doped poly silicon. In the embodiment of FIG. 5D, the first contact 532a and the second contact 532b are respectively positioned on a different vertical position as the vertical position of the surface 504 of the substrate 500. In other words, the bottom surfaces 534a, 534b respectively of the first contact 532a and the second contact 532b are respectively positioned on a different plane as the surface 504 of the substrate 500.

[0144] In various embodiments, the bottom surface 534a of the first contact 532a and the bottom surface 534b of the second contact 532b may be on a same or different vertical position or plane. As an example, in the embodiment of FIG. 5D, the bottom surface 534a of the first contact 532a and the bottom surface 534b Of the second contact 532b are on different vertical positions (ie. different planes).

[0145] As shown in the embodiment of FIG. 5D, the first contact 532a is formed over the substrate 500 such that the first contact 532a is in electrical communication with or electrically connected to the first ends 518a of the first conductive layers 508 while the second contact 532b is formed over the substrate 500 such that the second contact 532b is in electrical communication with or electrically connected to the third ends 520a of the second conductive layers 512. In addition, the second ends 518b of the first conductive layers 508 are respectively electrically isolated from the second contact 532b and the fourth ends 520b of the second conductive layers 512 are respectively electrically isolated from the first contact 532a.

[0146] In the embodiments illustrated in FIGS. 5A to 5D, two layers of the first conductive layers and two layers of the second conductive layer, with a capacitive isolation layer in between two neighbouring conductive layers, are shown for ease of illustration and clarity purposes. It should be appreciated that any number of the layers of the first conductive layers and the second conductive layers may be provided. For example, five layers of the first conductive layer and five layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, or ten layers of the first conductive layer and ten layers of the second conductive layer, with the corresponding number of the capacitive isolation layers, may be provided. In various embodiments, increasing the number of layers of the first conductive layer and the second conductive layer may increase the capacitance of the capacitor arrangement.

[0147] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A capacitor arrangement comprising:

a substrate;

a first contact disposed over the substrate;

a second contact disposed over the substrate; and

a stack of layers , comprising:

a plurality of first conductive layers;

a plurality of second conductive layers; and

a plurality of capacitive isolation layers;

wherein the first conductive layers, the second conductive layers and the capacitive isolation layers alternate with each other such that, between two neighboring first conductive layers, one second conductive layer is disposed, and wherein the first conductive layers and the second conductive layers are isolated from each other by the capacitive isolation layers; and

wherein the first conductive layers are electrically connected with the first contact and electrically isolated from the second contact and the second conductive layers are electrically connected with the second contact and electrically isolated from the first contact.

2. The capacitor arrangement of claim 1, wherein each of the first conductive layers comprises a first end and a second end, the second end arranged opposite to the first end.

3. The capacitor arrangement of claim 2, wherein the first ends of the first conductive layers are respectively electrically connected with the first contact, and the second ends of the first conductive layers are respectively electrically isolated from the second contact.

4. The capacitor arrangement of claim 3, wherein the second ends of the first conductive layers are respectively electrically isolated from the second contact by the capacitive isolation layers.

5. The capacitor arrangement of any one of claims 1 to 4, wherein each of the second conductive layers comprises a third end and a fourth end, the fourth end arranged opposite to the third end.

6. The capacitor arrangement of claim 5, wherein the third ends of the second conductive layers are respectively electrically connected with the second contact, and the fourth ends of the second conductive layers are respectively electrically isolated from the first contact.

7. The capacitor arrangement of claim 6, wherein the fourth ends of the second conductive layers are respectively electrically isolated from the first contact by the capacitive isolation layers.

8. The capacitor arrangement of any one of claims 1 to 7, wherein the substrate is flat, and wherein the stack of layers is arranged over the substrate.

9. The capacitor arrangement of any one of claims 1 to 8, wherein the substrate comprises a trench, and wherein the stack of layers is partly arranged in the trench.

10. The capacitor arrangement of any one of claims 1 to 8, wherein the capacitor arrangement further comprises one or more films disposed between the substrate and the stack of layers, wherein the one or more films comprise a trench, and wherein the stack of layers is partly arranged in the trench.

11. The capacitor arrangement of claim 10, wherein the one or more films comprise conducting films and/or non-conducting films.

12. The capacitor arrangement of any one of claims 9 to 11, wherein the width of the trench decreases with increasing trench depth, or wherein the width of the trench remains at least substantially constant with increasing trench depth.

13. The capacitor arrangement of any one of claims 9 to 12, wherein the trench comprises a trench opening, the trench opening comprising a first trench opening area and a second trench opening area being different from the first trench opening area.

14. The capacitor arrangement of claim 13, wherein the stack of layers has an U-like shape, the first ends of the first conductive layers ending within the first trench opening area, and the third ends of the second conductive layers ending within the second trench opening area.

15. The capacitor arrangement of claim 13 or 14, wherein the first contact is arranged over the first trench opening area, and the second contact is arranged over the second trench opening area.

16. The capacitor arrangement of any one of claims 1 to 9 or 12 to 14, wherein the first contact and the second contact are respectively positioned on a same or different vertical position as the vertical position of a surface of the substrate.

17. The capacitor arrangement of claim 10 or 11, wherein the first contact and the second contact are respectively positioned on a same or different vertical position as the vertical position of a surface of the one or more films.

18. The capacitor arrangement of any one of claims 1 to 17, wherein the substrate comprises a material selected from a group consisting of silicon, poly silicon, silicon germanium, silicon carbide, sapphire, and glass.

19. The capacitor arrangement of any one of claims 1 to 18, wherein each of the capacitive isolation layers comprises a material selected from a group consisting of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and magnesium oxide.

20. The capacitor arrangement of any one of claims 1 to 19, wherein each of the first conductive layers comprises a material selected from a group consisting of doped silicon, doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer.

21. The capacitor arrangement of any one of claims 1 to 20, wherein each of the second conductive layers comprises a material selected from a group consisting of doped silicon, doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer.

22. The capacitor arrangement of any one of claims 1 to 21, wherein each of the first conductive layers is a different material as the material of each of the second conductive layers.

23. The capacitor arrangement of any one of claims 1 to 19, wherein the first contact comprises a material selected from a group consisting of doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer.

24. The capacitor arrangement of any one of claims 1 to 20, wherein the second contact comprises a material selected from a group consisting of doped poly silicon, silicon germanium, metal, metal nitride, metal silicide, and conducting polymer.

25. The capacitor arrangement of any one of claims 1 to 24, wherein the first contact and the second contact are contact pads, respectively.

26. The capacitor arrangement of claim 20, 21, 23 or 24, wherein the metal is selected from a group consisting of titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), chromium (Cr) and copper (Cu).

27. The capacitor arrangement of claim 20, 21, 23 or 24, wherein the metal nitride comprises titanium nitride (TiN) or tantalum nitride (TaN) or hafnium nitride (HfN).

28. The capacitor arrangement of claim 20, 21, 23 or 24, wherein the metal silicide comprises nickel silicide (NiSi) or titanium silicide (TiSi).

29. A method of forming a capacitor arrangement, the method comprising:

forming a first contact over a substrate;

forming a second contact over the substrate; and

forming a stack of layers over the substrate, wherein forming the stack of layer comprises:

forming a plurality of first conductive layers;

forming a plurality of second conductive layers; and

forming a plurality of capacitive isolation layers;

30. The method of claim 29, wherein the first conductive layers are formed such that each of the first conductive layers comprises a first end and a second end, the second end arranged opposite to the first end.

31. The method of claim 30, wherein the second conductive layers are formed such that each of the second conductive layers comprises a third end and a fourth end, the fourth end arranged opposite to the third end.

32. The method of claim 31 , wherein forming the stack of layers further comprises: removing a plurality of first portions from the second ends of the first conductive layers, thereby creating a plurality of first recesses within the stack of layers; and

at least partly filling the first recesses with a capacitive isolation material.

33. The method of claim 32, wherein forming the stack of layers further comprises: removing a plurality of second portions from the fourth ends of the second conductive layers, thereby creating a plurality of second recesses within the stack of layers; and

at least partly filling the second recesses with a further capacitive isolation material.

34. The method of claim 33, wherein the removal of the first portions from the second ends of the first conductive layers and the removal of the second portions from the fourth ends of the second conductive layers are respectively carried out using a selective etching process.

35. The method of claim 33 or 34, wherein the capacitive isolation material and the further capacitive isolation material are of a same or different material from the capacitive isolation layers.

36. The method of any one of claims 31 to 35, wherein the first contact is formed over the substrate such that the first contact is electrically connected to the first ends of the first conductive layers.

37. The method of any one of claims 31 to 36, wherein the second contact is formed over the substrate such that the second contact is electrically connected to the third ends of the second conductive layers.

38. The method of any one of claims 29 to 37, wherein the material of the first conductive layers differs from the material of the second conductive layers.

39. The method of any one of claims 31 to 38, wherein forming the stack of layers comprises:

forming a trench in the substrate such that, the trench comprises a trench opening, the trench opening comprising a first trench opening area and a second trench opening area being different from the first trench opening area.

40. The method of claim 39, further comprising providing a mask over the substrate, wherein the mask comprises a structure configured for forming the trench.

41. The method of claim 40, wherein forming the stack of layers further comprises: depositing the stack of layers over the substrate such that the stack of layers is also deposited into the trench; and

carrying out a planarization process such that a top surface of the parts of the substrate or the mask surrounding the trench is exposed.

42. The method of any one of claims 31 to 38, further comprising forming one or more films between the substrate and the stack of layers, and wherein forming the stack of layers comprises forming a trench in the one or more films such that, the trench comprises a trench opening, the trench opening comprising a first trench opening area and a second trench opening area being different from the first trench opening area.

43. The method of claim 42, wherein forming the stack of layers further comprises forming the trench partially in the substrate.

44. The method of claim 42 or 43, further comprising providing a mask over the one or more films, wherein the mask comprises a structure configured for forming the trench.

45. The method of claim 44, wherein forming the stack of layers further comprises: depositing the stack of layers over the one or more films such that the stack of layers is also deposited into the trench; and carrying out a planarization process such that a top surface of the parts of the one or more films or the mask surrounding the trench is exposed.

46. The method of claim 41 or 45, wherein the stack of layers are formed such that the stack of layers has an U-like shape within the trench, the first ends of the first conductive layers ending within the first trench opening area, and the third ends of the second conductive layers ending within the second trench opening area.

47. The method of claim 46, wherein the first contact and the second contact are formed such that the first contact is arranged over the first trench opening area, and the second contact is arranged over the second trench opening area.

48. The method of claim 41 or 45, further comprising an etching process configured to etch the stack of layers in the trench such that a first side wall and a second side wall of the trench are partially exposed.

49. The method of claim 48, wherein the first contact and the second contact are formed such that the first contact is arranged in contact with the first side wall of the trench, and the second contact is arranged in contact with the second side wall of the trench.

50. The method of any one of claims 29 to 38, wherein the stack of layers comprises a first opening and a second opening different from the first opening.

51. The method of claim 50, wherein the first contact and the second contact are formed such that the first contact is arranged in the first opening, and the second contact is arranged in the second opening.