CN114256240A - Capacitor and preparation method thereof - Google Patents

Capacitor and preparation method thereof Download PDF

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Publication number
CN114256240A
CN114256240A CN202011019867.3A CN202011019867A CN114256240A CN 114256240 A CN114256240 A CN 114256240A CN 202011019867 A CN202011019867 A CN 202011019867A CN 114256240 A CN114256240 A CN 114256240A
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China
Prior art keywords
capacitor
sub
layer
electrode
capacitors
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CN202011019867.3A
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Chinese (zh)
Inventor
崔锺武
金成基
李俊杰
周娜
李琳
王佳
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202011019867.3A priority Critical patent/CN114256240A/en
Publication of CN114256240A publication Critical patent/CN114256240A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application relates to the technical field of semiconductors, in particular to a capacitor and a preparation method thereof, wherein the capacitor comprises: a substrate; forming a first sub-capacitor on the substrate; second to nth sub-capacitors sequentially stacked above the first sub-capacitor along a vertical direction; each sub-capacitor comprises a cylindrical lower electrode, and a conductive medium cylinder is filled in the cylindrical lower electrode; the lower electrodes of the second to Nth sub-capacitors are respectively connected with the conductive medium cylinders of the sub-capacitors below the lower electrodes; n is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel. This application sets up multilayer electrode plate subassembly, fills the cylinder at the inner wall of bottom electrode, uses the outer wall of bottom electrode as the electrode contact, has increased the area of plate electrode to the electric capacity of condenser has been improved.

Description

Capacitor and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a capacitor and a preparation method thereof.
Background
In the DRAM, data is stored using a capacitor, and as the leakage current is smaller and the capacitor capacity is larger, the characteristics of data storage and refresh characteristics are better.
Increasing the area of the Capacitor has become difficult with the high integration of semiconductor devices and the reduction of Design sizes (Design Rule), i.e., the height of the pillar Capacitor has reached the limit of the etching process, and the use of the inner and outer walls to increase the area of the Capacitor has reached the limit due to the reduction of the Design size.
Disclosure of Invention
The present application addresses, at least to some extent, the above-mentioned technical problems in the related art. Therefore, the application provides a capacitor and a preparation method thereof to solve the problem of electric leakage of the existing capacitor.
In order to achieve the above object, a first aspect of the present application provides a capacitor comprising:
a substrate;
forming a first sub-capacitor on the substrate;
second to nth sub-capacitors sequentially stacked above the first sub-capacitor along a vertical direction;
each sub-capacitor comprises a cylindrical lower electrode, and a conductive medium cylinder is filled in the cylindrical lower electrode;
the lower electrodes of the second to Nth sub-capacitors are respectively connected with the conductive medium cylinders of the sub-capacitors below the lower electrodes;
n is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel.
In a second aspect, the present application provides a method for manufacturing a capacitor, comprising the steps of:
providing a substrate;
forming a first sub-capacitor on the substrate;
sequentially stacking the first sub-capacitor above the second sub-capacitor along the vertical direction to form second to Nth sub-capacitors;
the step of forming each sub-capacitor comprises:
forming a cylindrical lower electrode, wherein a conductive medium cylinder is filled in the cylindrical lower electrode;
the lower electrodes of the second to Nth sub-capacitors are respectively connected with the conductive medium cylinders of the sub-capacitors below the lower electrodes;
n is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic structural diagram illustrating an interlayer dielectric layer, a first molding layer, and a first sub-capacitor trench formed on a semiconductor substrate;
FIG. 2 is a schematic diagram illustrating the structure of FIG. 1 after a first lower electrode is formed thereon;
FIG. 3 shows a schematic view of the structure shown in FIG. 2 after filling the first column;
FIG. 4 shows a schematic view of the structure shown in FIG. 3 after the first molding layer has been removed;
FIG. 5 shows a schematic view of the structure after a first dielectric layer has been formed over the structure shown in FIG. 4;
fig. 6 is a schematic view showing a structure after a first upper electrode is formed on the structure shown in fig. 5;
FIG. 7 shows a schematic view of the structure after a second molding layer is formed on the structure shown in FIG. 6;
fig. 8 is a schematic view illustrating a structure after forming a second sub-capacitor trench on the structure illustrated in fig. 7;
FIG. 9 is a schematic view showing a structure after removing a top surface of the first upper electrode from the structure shown in FIG. 8;
FIG. 10 is a schematic diagram of the structure of FIG. 9 after removing a portion of the top surface of the first dielectric layer and a portion of the top surface of the first pillars;
fig. 11 is a schematic view showing a structure after forming a second lower electrode on the structure shown in fig. 10, filling a second pillar, and removing a second molding layer;
fig. 12 is a schematic structural view after a second dielectric layer and a second upper electrode are formed on the structure shown in fig. 11.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Referring to fig. 12, a first aspect of the present application provides a cylindrical capacitor 100, where the capacitor 100 includes:
the semiconductor substrate 10 may be, for example, a bulk silicon semiconductor substrate, a silicon-on-insulator (SOI) semiconductor substrate, a germanium-on-insulator (GOI) semiconductor substrate, a silicon germanium semiconductor substrate, a III-V group compound semiconductor substrate, or an epitaxial thin film semiconductor substrate obtained by performing Selective Epitaxial Growth (SEG).
When the semiconductor substrate 10 is a silicon-based semiconductor substrate, the semiconductor substrate 10 may include, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor may be stabilized by a hydrogen annealing process by which hydrogen atoms are bonded to dangling-bonded silicon atoms of the semiconductor substrate 10. In this case, the hydrogen atom may be easily separated from the silicon atom, but boron may increase the binding energy between the silicon atom and the hydrogen atom. Thus, the variable retention time or charge retention time of a memory cell (e.g., capacitor CP) in a semiconductor structure may be improved.
An interlayer dielectric layer 20 formed on the upper surface of the semiconductor substrate 10, a storage node contact region (not numbered) formed in the semiconductor substrate 10, and a portion of the interlayer dielectric layer 20 corresponding to the storage node contact region is removed to form a contact hole exposing a portion of the semiconductor substrate 10. The contact hole is filled with polysilicon to form the storage node contact plug 12. In this embodiment, the material of the interlayer dielectric layer 20 may be SiO, and the material of the storage node contact plug 12 may be W.
And a first insulating layer 11 formed on an upper surface of the interlayer dielectric layer 20. In this embodiment, the material of the first insulating layer 11 may be SiN or SiBN.
The first sub-capacitor 13 specifically includes: a cylindrical first lower electrode 130, a first conductive dielectric cylinder (pellet) 131 filled in the first lower electrode 130; a first dielectric layer 132 covering the outer sidewall of the first lower electrode, the top surface of the first lower electrode and the top surface of the first pillar, a first upper electrode 133 covering the outer wall of the first dielectric layer 132, a bottom end of the first dielectric layer 132 extending in the horizontal direction to form a second extension 134, and a first insulating layer 11 located between the second extension 134 and the interlayer dielectric layer 20.
It should be noted that the material of the first lower electrode 130 and the first upper electrode 133 may be selected from one of TiN, TaN, W/WN, Pt, Ru, and AlN or a stack of two or more selected from the group consisting of the above materials, or the first lower electrode 130 and the first upper electrode 133 may be formed of: the film is made of the above-mentioned material (i.e., TiN, TaN, WN, Pt, Ru, or AlN) combined with Si, C, Al, Ge, etc., and the first lower electrode 130 and the first upper electrode 133 are preferably TiN films.
The first dielectric layer 132 is a high-k dielectric layer to increase the capacitance per unit area of the capacitor, and the first dielectric layer 132 may be made of a material having a high dielectric constant, such as Al2O3、ZrO2、HfO2、Ta2O5、TiO2STO, BST, PZT, or the like, or formed of a multilayer film.
The material of the first conductive dielectric pillar 131 may be selected from boron doped polysilicon, tantalum nitride, or titanium nitride.
The second sub-capacitor 14 and the nth sub-capacitor are stacked on the first sub-capacitor 13 along the vertical direction, where N is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel. It should be noted that, in the present embodiment, only N is equal to zero, that is, the cylindrical capacitor 100 includes two sub-capacitors stacked in the vertical direction for description, but the present embodiment is not limited thereto, and N may be equal to 1, 2, 3, 4, 5, and so on.
The second sub-capacitance 14 includes: the second lower electrode 140 has an electrode body 141 and an electrode contact 142, the electrode body 141 is cylindrical, the electrode contact 142 is formed by protruding from the bottom of the cylindrical shape, the electrode contact 142 penetrates through the first upper electrode 133 and the first dielectric layer 132 to contact the first conductive dielectric cylinder 131, the second conductive dielectric cylinder 143 is filled in the electrode body 141, the second dielectric layer 144 covers the outer sidewall of the electrode body 141, the top surface of the electrode body 141 and the top surface of the second conductive dielectric cylinder 143, and the second upper electrode 145 covers the outer sidewall of the second dielectric layer 144.
It should be noted that the materials of the second bottom electrode 140, the second top electrode 145, the second dielectric layer 144 and the second conductive dielectric pillar 143 may be the same as or different from the materials of the first bottom electrode 130, the first top electrode 133, the first dielectric layer 132 and the first conductive dielectric pillar 131. The present embodiment is not limited herein.
And a third insulating layer 15 disposed between the second lower electrode 140 of the second sub-capacitor 14 and the first upper electrode 133 of the first sub-capacitor 13, specifically, a through hole is formed on the top surface of the first upper electrode 130, and the third insulating layer 15 is embedded in the through hole and contacts with two sides of the electrode contact 142. In this embodiment, the material of the third insulating layer 15 may be SiN or SiO.
The second insulating layer 16 is disposed between the second dielectric layer 144 of the second sub-capacitor 14 and the first upper electrode 133 of the first sub-capacitor 13, specifically, the bottom end of the second dielectric layer 144 extends toward the horizontal direction to form a first extending portion 146, and the second insulating layer 16 is disposed between the first extending portion 146 and the first upper electrode 133. In this embodiment, the second insulating layer 16 may be made of SiN or SiBN.
It should be noted that, in order to prevent the first sub-capacitor 13 and the second sub-capacitor 14 from collapsing, the pillar capacitor 100 of the present embodiment may further include a top Support layer (Support) and a bottom Support layer (not shown), and the top Support layer and the bottom Support layer are spaced apart from each other. The top supporting layer and the bottom supporting layer are respectively located at the peripheries of the first upper electrode 133 and the second upper electrode 145, and are perpendicular to the extending direction of the U-shaped sidewalls of the first upper electrode 133 and the second upper electrode 145. Specifically, the material of the top supporting layer and the bottom supporting layer may be selected from SiN or SiCN.
In addition, an electrode connection layer (not shown) is further disposed on the top surface of the second upper electrode 145, and the electrode connection layer is used to connect the electrode plate assembly of the capacitor with the metal wire.
A method of manufacturing the cylindrical capacitor 100 in the embodiment of the present application is described below.
Specifically, the method for manufacturing the cylindrical capacitor 100 includes the steps of:
as shown in fig. 1, a semiconductor substrate 10 is provided, an interlayer dielectric layer 20 is formed on the semiconductor substrate 10, and then a predetermined portion of the interlayer dielectric layer 20 corresponding to a storage node contact region (not numbered) is etched to form a contact hole exposing a portion of the semiconductor substrate 10. The contact hole is filled with polysilicon to form the storage node contact plug 12. At this time, a series of predetermined processes related to the manufacture of the semiconductor device may be performed before the formation of the interlayer dielectric layer 20. For example, an isolation layer, a word line, and a bit line may be sequentially formed, or a source/drain of a transistor may be formed in the semiconductor substrate 10.
Next, with continued reference to fig. 1, a first insulating layer 11 and a first molding layer 17 are formed on the surface of the interlayer dielectric layer 20 by bottom-to-top deposition, the first molding layer 17 is made of an insulating material, and specifically, the material of the first molding layer 17 may be BPSG.
Next, with continued reference to fig. 1, the first molding layer 17 is patterned to form a first sub-capacitance trench 170 communicating with the storage node contact plug, and specifically, a portion of the first molding layer 17 and the first insulating layer 11 are etched away.
Next, as shown in fig. 2, a first lower electrode 130 is deposited on the inner sidewall of the first sub-capacitor trench 170 and the top surface of the storage node contact plug 12, the first lower electrode 130 covers the inner sidewall of the first sub-capacitor trench 170 and the top surface of the storage node contact plug 12, and the first lower electrode 130 is cylindrical.
Next, as shown in fig. 3, the first lower electrode 130 is filled with a first conductive dielectric pillar 131, and specifically, the first conductive dielectric pillar 131 may be formed in the first lower electrode 130 by a deposition process.
Next, as shown in fig. 4, the first molding layer 17 is removed using an etching process.
Next, as shown in fig. 5, a first dielectric layer 132 covering the outer sidewalls of the first lower electrode 130, the top surface of the first lower electrode 130, and the top surface of the first conductive dielectric pillar 131 may be formed by CMP or ALD.
Next, as shown in fig. 6, a first upper electrode 133 is formed to cover the outer wall of the first dielectric layer 132 by a deposition process.
It should be noted that the first lower electrode 130, the first conductive dielectric cylinder 131, the first dielectric layer 132, and the first upper electrode 133 form the first sub-capacitor 13 of the cylindrical capacitor 100.
Next, second sub-capacitances are sequentially stacked above the first sub-capacitance 13 in the vertical direction. The step of forming the second sub-capacitor comprises:
next, as shown in fig. 7, a second insulating layer 16 covering the top surface of the first upper electrode 133 is deposited; a second molding layer 18 is deposited on the second insulating layer 16, and the material of the second molding layer 18 is the same as that of the first molding layer 17, and is BPSG.
Next, patterning the second molding layer 18 to form the second sub-capacitor trench 180 specifically includes the following steps:
as shown in fig. 8, a portion of the second molding layer 18 is removed through an etching process to expose the first upper electrode 133 of the first sub-capacitor 13.
Next, as shown in fig. 9, the top surface of the first upper electrode 133 is etched away to expose the first dielectric layer 132.
Next, as shown in fig. 10, a third insulating layer 15 is deposited on the first dielectric layer 132, and a portion of the third insulating layer 15 and the first dielectric layer 132 is etched until the top surface of the adjacent first conductive dielectric pillar 131 is exposed.
Next, as shown in fig. 11, a second lower electrode 140 is deposited on the inner sidewall of the second sub-capacitor trench 180, the second lower electrode 140 is cylindrical, and then the second lower electrode 140 is filled with a second conductive dielectric cylinder 143, and the second molding layer 18 is removed by etching.
Next, as shown in fig. 12, a second dielectric layer 144 is deposited to cover the outer sidewall of the second bottom electrode 140, the top surface of the second bottom electrode 140, and the top surface of the second conductive dielectric pillar 143, and then a second top electrode 145 is deposited to cover the outer wall of the second dielectric layer 144.
It should be noted that the second bottom electrode 140, the second conductive dielectric cylinder 143, the second dielectric layer 144 and the second top electrode 145 form the second sub-capacitor 14 of the pillar capacitor 100.
In addition, an electrode connection layer (not shown) is deposited on the top surface of the second upper electrode 145, and is used for connecting the electrode plate assembly of the capacitor with the metal wire.
It should be noted that, in the present embodiment, only two layers of sub-capacitors are taken as an example for description, the two layers of sub-capacitors are electrically connected in parallel, and the cylindrical capacitor 100 in the present embodiment may also be provided with three, four, five or even more layers of sub-capacitors, which can be flexibly selected by a person skilled in the art according to needs, and the present embodiment is not limited herein.
Compared with the prior art, this application sets up multilayer electrode board subassembly, fills the conductive medium cylinder at the inner wall of bottom electrode, uses the outer wall of bottom electrode as the bottom electrode, has increased the area of electric capacity to the electric capacity of condenser has been improved.
The capacitor of the present embodiment can be used in DRAM, Flash and Logic, and the transistors (not shown) coupled in series with the capacitor can be formed by a known manufacturing process to complete the manufacturing of the DRAM.
Further, the DRAM, Flash, and Logic having the capacitor in this embodiment can be used in various chips.
Still further, the chip with the above capacitor may be used in various electronic devices, in particular, smart phones, computers, tablets, wearable smart devices, artificial smart devices, mobile power sources, and the like.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (15)

1. A capacitor, comprising:
a substrate;
forming a first sub-capacitor on the substrate;
second to nth sub-capacitors sequentially stacked above the first sub-capacitor along a vertical direction;
each sub-capacitor comprises a cylindrical lower electrode, and a conductive medium cylinder is filled in the cylindrical lower electrode;
the lower electrodes of the second to Nth sub-capacitors are respectively connected with the conductive medium cylinders of the sub-capacitors below the lower electrodes;
n is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel.
2. The capacitor of claim 1 wherein said sub-capacitances further comprise a dielectric layer outside said lower electrode and an upper electrode outside said dielectric layer.
3. The capacitor of claim 1 wherein said conductive dielectric cylinder is selected from the group consisting of boron doped polysilicon, tantalum nitride and titanium nitride.
4. The capacitor of claim 2, wherein the dielectric layer of the first sub-capacitor and the substrate have a first insulating layer therebetween.
5. The capacitor of claim 2, wherein a second insulating layer is disposed between the dielectric layer of each of the second to nth sub-capacitors and the upper electrode of the adjacent lower sub-capacitor.
6. The capacitor of claim 2, wherein a third insulating layer is disposed between the lower electrode of each of the second to nth sub-capacitors and the upper electrode of the adjacent lower sub-capacitor.
7. The capacitor of claim 6, further comprising:
and the storage node contact plug is arranged in the substrate and is in contact with the lower electrode of the first sub-capacitor.
8. The capacitor of claim 7, further comprising:
and the electrode connecting layer is arranged on the surface of the upper electrode of the Nth sub-capacitor.
9. The capacitor of claim 8, further comprising:
and the at least one supporting layer is arranged at the periphery of the upper electrode of one or more of the first to the Nth sub-capacitors.
10. A method for manufacturing a capacitor, comprising the steps of:
providing a substrate;
forming a first sub-capacitor on the substrate;
sequentially stacking the first sub-capacitor above the second sub-capacitor along the vertical direction to form second to Nth sub-capacitors;
the step of forming each sub-capacitor comprises:
forming a cylindrical lower electrode, wherein a conductive medium cylinder is filled in the cylindrical lower electrode;
the lower electrodes of the second to Nth sub-capacitors are respectively connected with the conductive medium cylinders of the sub-capacitors below the lower electrodes;
n is an integer greater than or equal to zero, and the N sub-capacitors are connected in parallel.
11. The method of manufacturing a capacitor according to claim 10, wherein the step of forming the first sub-capacitance comprises:
depositing a first insulating layer on the substrate provided with the storage node contact plugs;
forming a first molding layer on the first insulating layer;
patterning the first molding layer to form a first sub-capacitance trench communicated with a storage node contact plug;
and forming a cylindrical lower electrode in the first sub-capacitor groove, and filling a conductive medium cylinder in the cylindrical lower electrode.
12. The method for producing a capacitor as claimed in claim 11, further comprising the steps of:
removing the first molding layer;
forming a dielectric layer covering the outer side wall of the cylindrical lower electrode, the top surface of the cylindrical lower electrode and the top surface of the conductive dielectric cylinder;
and forming an upper electrode covering the outer side of the dielectric layer.
13. The method of manufacturing a capacitor as claimed in claim 12, wherein the step of forming the second to nth sub-capacitances comprises:
depositing a second insulating layer above the adjacent lower layer sub-capacitors;
forming a second or nth molding layer over the second insulating layer;
patterning the second or Nth molding layer to form a second or Nth sub-capacitance groove;
and forming a cylindrical lower electrode in the second or Nth sub-capacitor groove, and filling a conductive medium cylinder in the cylindrical lower electrode.
14. The method for producing a capacitor as claimed in claim 13,
the step of patterning the second or nth molding layer to form a second or nth sub-capacitor trench includes:
etching the second or N molding layer until the upper electrode of the adjacent lower-layer sub capacitor is exposed;
etching to remove the top surface of the upper electrode to expose the dielectric layer of the adjacent lower-layer sub-capacitor;
forming a third insulating layer on the dielectric layer;
and etching part of the third insulating layer and the dielectric layer of the adjacent lower-layer sub-capacitor until the top surface of the conductive column of the adjacent lower-layer sub-capacitor is exposed.
15. The method for producing a capacitor as claimed in claim 14, further comprising the steps of:
removing the second nth molding layer;
forming a dielectric layer covering the outer side wall of the cylindrical lower electrode, the top surface of the cylindrical lower electrode and the top surface of the conductive dielectric cylinder;
and forming an upper electrode covering the outer side of the dielectric layer.
CN202011019867.3A 2020-09-24 2020-09-24 Capacitor and preparation method thereof Pending CN114256240A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937739A (en) * 2022-04-02 2022-08-23 威海嘉瑞光电科技股份有限公司 Capacitor forming method and capacitor
WO2023197440A1 (en) * 2022-04-11 2023-10-19 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor, and memory
WO2023206669A1 (en) * 2022-04-26 2023-11-02 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing semiconductor structure
WO2023245758A1 (en) * 2022-06-21 2023-12-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor, and memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937739A (en) * 2022-04-02 2022-08-23 威海嘉瑞光电科技股份有限公司 Capacitor forming method and capacitor
WO2023197440A1 (en) * 2022-04-11 2023-10-19 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor, and memory
WO2023206669A1 (en) * 2022-04-26 2023-11-02 长鑫存储技术有限公司 Semiconductor structure and method for manufacturing semiconductor structure
WO2023245758A1 (en) * 2022-06-21 2023-12-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor, and memory

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