CN111900168A - Memory cell, memory device and electronic apparatus - Google Patents

Memory cell, memory device and electronic apparatus Download PDF

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Publication number
CN111900168A
CN111900168A CN202010944026.7A CN202010944026A CN111900168A CN 111900168 A CN111900168 A CN 111900168A CN 202010944026 A CN202010944026 A CN 202010944026A CN 111900168 A CN111900168 A CN 111900168A
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layer
memory cell
conductive
capacitor
conductive layer
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朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

A memory cell, a memory device and an electronic apparatus are disclosed. According to an embodiment, the memory unit may include: a transistor; and a capacitor assembly connected with the transistor, wherein the capacitor assembly includes a positive capacitor and a negative capacitor connected in series with each other. The capacitor assembly is formed into a groove capacitor, the groove is U-shaped and comprises two vertical side walls and a bottom wall connected with the vertical side walls; the capacitor assembly includes a stack of a first conductive layer-a dielectric layer-a second conductive layer-a negative capacitor material layer-a third conductive layer; and each conductive layer comprises a layer of metallic electrode material.

Description

Memory cell, memory device and electronic apparatus
The present application is a divisional application of a parent application having an application number of "201610048641.3", an application date of 2016, 25/01, and an invention name of "memory cell, memory device, and electronic device", and the entire contents of the parent application are incorporated herein by reference.
Technical Field
The present disclosure relates to the field of storage, and more particularly, to a memory cell having a large storage capacitance, a memory device including the memory cell, and an electronic device including the memory device.
Background
Capacitors are often utilized in memory devices to store charge in order to store data. However, as devices are miniaturized, the chip area for forming the capacitor is reduced, and the capacitance value of the capacitor is reduced. In order to ensure memory performance, it is desirable to obtain as large a capacitance as possible without occupying an excessively large chip area.
Disclosure of Invention
An object of the present disclosure is to provide, at least in part, a memory cell having a large storage capacitance, a memory device including the memory cell, and an electronic device including the memory device.
According to an aspect of the present disclosure, there is provided a memory cell including: a transistor; and a capacitor assembly connected with the transistor, wherein the capacitor assembly includes a positive capacitor and a negative capacitor connected in series with each other.
According to another aspect of the present disclosure, there is provided a memory device including the above memory cell.
According to still another aspect of the present disclosure, there is provided an electronic device including the above memory device.
According to embodiments of the present disclosure, a storage capacitance component is formed using a series combination of a negative capacitor and a conventional capacitor (or, stated alternatively, a positive capacitor). Such a capacitive component can realize a large storage capacitance with the same footprint compared to a conventional storage capacitance.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
FIG. 1 is a schematic circuit diagram illustrating a memory cell according to an embodiment of the present disclosure;
2(a) -2(g) are cross-sectional views illustrating a middle staging of a flow of fabricating a memory cell according to an embodiment of the disclosure;
fig. 3 is a sectional view showing a configuration of a memory cell according to another embodiment of the present disclosure;
4(a) -4(d) are cross-sectional views illustrating a middle staging of a flow for fabricating a memory cell according to another embodiment of the present disclosure;
fig. 5 is a sectional view showing a configuration of a memory cell according to another embodiment of the present disclosure.
The same reference numbers will be used throughout the drawings to refer to the same or like parts.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Fig. 1 is a schematic circuit diagram illustrating a memory cell according to an embodiment of the present disclosure.
As shown in fig. 1, the memory cell 100 according to this embodiment includes a transistor 101 and a capacitor element 103 connected to the transistor. For example, such memory cells may constitute 1T1C configured Dynamic Random Access Memory (DRAM) cells.
Transistor 101 may include various forms of transistors, such as various forms of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), such as fin field effect transistors (finfets), semiconductor-on-insulator (SOI) MOSFETs, nanowire field effect transistors (nanowire FETs), and so forth.
In general, the transistor 101 may include a gate, a source, and a drain. In the example of fig. 1, the gate may be connected to the terminal T1, one of the source/drains may be connected to the terminal T2, and the other of the source/drains may be connected to the capacitive component 103. The other end of the capacitor assembly 103 is connected to a terminal T3. Thus, in this example, the transistor 101 is connected in series with the capacitive component 103.
The capacitive component 103 may include a conventional capacitor (or, a positive capacitor) 1031 and a negative capacitor 1033 connected in series. Generally, a capacitor includes a plate-dielectric layer-plate configuration, which can store charge. Conventional capacitors exhibit a "positive" capacitance characteristic, i.e., the voltage between the two plates increases as the charge stored by the dielectric layer increases. In the present disclosure, such a dielectric layer is referred to as a conventional dielectric layer, or simply as a dielectric layer, as that term is used conventionally in the art. In contrast, some materials may exhibit "negative" capacitance characteristics under certain conditions, i.e., as the charge stored therein increases, the voltage between the plates instead appears to decrease. Such materials are referred to as "negative capacitance materials". For example, certain ferroelectric materials (e.g., Zr, Ba, or Sr containing materials, such as HfZrO)2、BaTiO3、KH2PO4Or NBT, etc.) when a certain critical electric field is reached, a polarization phenomenon may occur. Polarization causes a large amount of bound charges to instantaneously accumulate on the surface of the material, reducing the voltage across the ferroelectric material.
Capacitance C of the capacitive assembly 103 due to the series relationshiptCan be expressed as:
Ct＝|Cn|C/(|Cn|-C)，
wherein C is the capacitance of positive capacitor 1031, CnIs the capacitance value (negative as described above) of negative capacitor 1033, | CnI represents CnAbsolute value of (a). From the above formula, it can be seen that when | CnWhen | is approximately equal to C, CtMay tend to be infinite. Of course, this is an ideal situation, and in practice, also considerable electricity can be realizedContainer Ct(e.g., about 2 to 5 times the absolute value of C). Preferably, | Cn|＞C。
In view of the stacked arrangement of the capacitors and the series connection relationship, the capacitance component 103 may be formed in a stacked form of a first conductive layer-a dielectric layer-a second conductive layer-a negative capacitance material layer-a third conductive layer. At this time, the first conductive layer-the dielectric layer-the second conductive layer may constitute a positive capacitor 1031, and the second conductive layer-the negative capacitance material layer-the third conductive layer may constitute a negative capacitor 1033, and they form a series connection due to the common second conductive layer. Alternatively, the capacitor assembly 103 may be formed in a laminate form of a first conductive layer-a dielectric layer-a negative capacitor material layer-a third conductive layer. At this time, the first conductive layer and the third conductive layer constitute two plates of the capacitor element 103, and the combination of the dielectric layer and the negative capacitor material layer constitutes a capacitor medium of the capacitor element 103.
According to an embodiment of the present disclosure, the capacitive component may be formed in the form of a trench capacitor. In a limited area, a trench capacitor may increase the area of the opposing plates of the capacitor and thus increase the capacitance value. For example, a trench may be formed in the substrate in which the transistor is formed, or in one or more layers of a metallization stack over the transistor and a capacitive component formed in the trench. The layers in the capacitor stack configuration may extend along the sidewalls and bottom wall of the trench.
Each of the conductive layers (first conductive layer, second conductive layer, and third conductive layer) may include various suitable conductive materials, such as metals, metal nitrides, and the like. For better compatibility with semiconductor processing, the conductive material may include materials used in semiconductor processing to form conductive contacts, such as conductive diffusion barrier materials like TiN and metal electrode materials like W, etc. The metal electrode material may form a low ohmic contact suitable for conductive layers (e.g., first conductive layer or third conductive layer) that require forming connections with other components. In addition, in order to avoid diffusion of the metal electrode material, a conductive diffusion barrier material layer may be used in combination therewith.
Further, when a trench capacitor is formed in a substrate, the outermost layer (first conductive layer or third conductive layer) of the capacitor can be formed using a doped region in the substrate. In this case, the doped region may be directly connected to one of the source/drain of the transistor (which may also be a doped region) and thus connect the capacitive component to the transistor.
It is noted here that although the 1T1C configuration is described herein as an example, the present disclosure is not so limited. The capacitive assemblies disclosed herein may be applied to any application where large capacitances are desired, including various forms of capacitor-based memory devices.
There is also provided, in accordance with an embodiment of the present disclosure, a memory device, which may include a plurality of such memory cells. For example, the memory cells may be arranged in a two-dimensional array, the terminal T1 of each memory cell may be connected to a word line, the terminal T2 may be connected to a bit line, and the terminal T3 may be connected to a common potential (e.g., ground potential). A row of memory cells corresponding to the bit line can be selected by the word line; through the bit line, data can be written to or read from the memory cell in the selected row corresponding to the bit line. Of course, the memory device may also be implemented in a variety of other configurations.
Fig. 2(a) -2(g) are cross-sectional views showing a middle staging of a process for fabricating a memory cell according to an embodiment of the disclosure.
As shown in fig. 2(a), a substrate 1001 is provided. Here, the fabrication of an n-type transistor is taken as an example for description, so the substrate 1001 may be a p-type lightly doped silicon wafer. However, the present disclosure is not limited thereto. Substrate 1001 may include a variety of suitable substrates, such as a semiconductor-on-insulator (SOI) substrate, a compound semiconductor such as SiGe, and the like.
In the substrate 1001, as described above, a trench may be formed so as to form a capacitive component therein.
For this, a hard mask layer may be formed on the substrate 1001 as shown in fig. 2 (a). In this example, the hard mask layer includes an oxide (e.g., silicon oxide) layer 1003 and a nitride (e.g., silicon nitride) layer 1005. For example, the thickness of the oxide layer 1003 is about 5 to 20nm, and the thickness of the nitride layer 1005 is about 50 to 200 nm. A patterned (e.g., photolithographic by exposure, development) photoresist 1007 can be formed on the hard mask layer. Here, the photoresist 1007 is patterned to have an opening corresponding to a trench to be formed.
Then, as shown in fig. 2(b), the hard mask layer (1005, 1003) may be patterned, such as Reactive Ion Etching (RIE), using the patterned photoresist 1007 as a mask, to transfer the pattern of the photoresist 1007 into the hard mask layer (1005, 1003). Next, the substrate 1001 may be patterned, such as RIE, using the hard mask layers (1005, 1003) as a mask to form a trench R therein. Subsequently, a capacitive component will be formed in this trench R. After forming the trench R, the photoresist 1007 may be removed. Here, the hard mask layer may not be removed first in order to protect the surface of the substrate 1001.
In this example, portions of substrate 1001 proximate the sidewalls and bottom wall of trench R may be doped to form doped regions (i.e., conductive regions) extending along the sidewalls and bottom wall of trench R and thereby constitute one plate of a capacitive component (e.g., the first conductive layer described above). Such a doped region can be formed, for example, as follows. Specifically, as shown in fig. 2(c), a dopant source layer 1009 may be formed (e.g., by deposition) on the substrate 1001 in which the trench R is formed (where the hard mask layer facilitates formation of doped regions extending along the sidewalls and bottom wall of the trench R). A dopant source layer refers to a layer of material that includes dopants. For example, the dopant source layer 1009 may include an oxide doped with an n-type dopant such As or P. The dopant source layer 1009 may have a thickness that does not fill the trench R and thus extends along the sidewalls and bottom wall of the trench R. The dopant source layer 1009 may preferably be deposited in a substantially conformal manner. Subsequently, an anneal may be performed to drive dopants from the dopant source layer 1009 into the substrate 1001. Since the dopant source layer 1009 is disposed along the sidewalls and the bottom wall of the trench R, the n-type doped region 1011 is formed along the sidewalls and the bottom wall of the trench R. Thereafter, the dopant source layer 1009 may be removed, as shown in fig. 2 (d).
It is noted herein that the doped regions may be formed in various other suitable manners (e.g., ion implantation).
Next, the trenches R may be filled with material layers to form a stacked arrangement of capacitor elements. In this example, after the n-type doped region 1011 as the first conductive layer is formed as described above, the trench R may be sequentially filled with a dielectric layer, a second conductive layer, a negative capacitance material layer, and a third conductive layer to form a capacitance component.
Specifically, as shown in fig. 2(e), a high-K dielectric layer 1013, a conductive diffusion barrier 1015, a negative capacitance material layer 1017, a conductive diffusion barrier 1019, and a metal electrode material layer 1021 may be formed in this order in the trench R. For example, high-K dielectric layer 1013 may include HfO2And a thickness of about 1 to 10 nm. At this time, an interface layer (not shown), such as an oxide layer, having a thickness of about 0.5 to 5nm, may be formed on the sidewalls and bottom wall of the trench R, and then a high-K dielectric layer 1013 may be formed on the interface layer. Alternatively, instead of the high-K dielectric layer 1013, an oxide layer may be formed, for example, to a thickness of about 2-10 nm. For example, the conductive diffusion barrier 1015 may comprise TiN with a thickness of about 1-10 nm; the negative capacitance material layer 1017 may include HfZrO2A thickness of about 3 to 15 nm; the conductive diffusion barrier 1019 may comprise TiN with a thickness of about 2-10 nm; the metal electrode material layer 1021 may include W, and its thickness may fill the trench R. In this case, the n-type doped region 1011 (first conductive layer) -the high-K dielectric layer 1013 (dielectric layer) -the conductive diffusion barrier 1015 (second conductive layer) may constitute a positive capacitor; the conductive diffusion barrier 1015 (second conductive layer) -negative capacitance material layer 1017-conductive diffusion barrier 1019-and metal electrode material layer 1021 (third conductive layer) may constitute a negative capacitor. Here, the third conductive layer includes a metal electrode material layer 1021, which is for better forming a low ohmic contact with a subsequently formed contact (see 1035-3 in fig. 2 (g)); the conductive diffusion barrier layer 1019 may prevent diffusion of the metal electrode material layer 1021 into the negative capacitance material layer 1017. For example, the trench R may be filled by sequentially depositing a high-K dielectric layer 1013, a conductive diffusion barrier 1015, a negative capacitance material layer 1017, a conductive diffusion barrier 1019 in a substantially conformal manner, and a metal electrode material layer 1021, followed by a planarization process such as Chemical Mechanical Polishing (CMP) (which may be a hard mask layer as a stop point) and then an etch back processTo fill these layers into the trench R.
In this example, the dielectric layer 1013 is formed and then the negative capacitance material layer 1017 is formed. However, the present disclosure is not limited thereto. For example, the layer of negative capacitance material may be formed first, followed by the formation of the dielectric layer.
After the capacitive components are formed, the hard mask layer may be removed and transistors formed on the substrate 1001. There are many ways in the art to form various forms of transistors, such as MOSFETs, which are not described in detail herein. Fig. 2(f) shows an example of one transistor. As shown in fig. 2(f), the transistor may include a gate stack (including a gate dielectric layer 1025 and a gate electrode layer 1027), a gate sidewall spacer 1029 formed around the gate stack, and a source/drain region 1031. Further, Shallow Trench Isolation (STI)1023 is also shown in fig. 2 (f). In this example, the transistor is an n-type device whose source/drain regions 1031 are in the form of n-type doped regions in the substrate 1001. One of the source/drain regions of the transistor (in this example the source/drain region to the right in figure 2 (f)) extends to meet the n-doped region 1011, thereby enabling connection between the transistor and the capacitive component.
Contact portions with other members may also be formed. For example, as shown in fig. 2(g), an interlayer dielectric layer 1033 (e.g., nitride) may be formed on the substrate where the transistor and the capacitor element are formed as shown in fig. 2 (f). In the interlayer dielectric layer 1033, contact holes are formed, for example, by etching, at positions corresponding to the other of the gate electrode, the source/drain region of the transistor (one not connected to the capacitor element), and the capacitor element (specifically, the metal electrode material layer 1021), and the contact portions 1035-1, 1035-2, and 1035-3 are formed by filling the contact holes with a conductive material layer (for example, a metal contact material such as W). Of course, it is also possible to first form a (conductive) diffusion barrier layer on the sidewalls and bottom wall of the contact hole and then refill the metal contact material layer. Contacts 1035-1, 1035-2, and 1035-3 may correspond to terminals T1, T2, and T3, respectively, in fig. 1.
Fig. 3 is a sectional view showing a configuration of a memory cell according to another embodiment of the present disclosure.
The memory cell shown in fig. 3 is substantially the same as the memory cell shown in fig. 2(g), except that the conductive diffusion barrier 1015 as the second conductive layer is omitted. In this example, the n-doped region 1011 (the first conductive layer) constitutes one plate of the capacitive assembly, the conductive diffusion barrier layer 1019 and the metal electrode material layer 1021 (the third conductive layer) constitute the other plate of the capacitive assembly, and the stack of the high-K dielectric layer 1013 (the dielectric layer) and the negative capacitive material layer 1017 constitutes the capacitive medium of the capacitive assembly. Also, the order of the high-K dielectric layer 1013 and the negative capacitance material layer 1017 may be exchanged.
In the above embodiments, the capacitor element is formed over the substrate as a transistor. However, the present disclosure is not limited thereto. For example, the capacitive component may also be formed in the metallization stack.
Fig. 4(a) -4(d) are cross-sectional views illustrating a middle staging of a process for fabricating a memory cell according to another embodiment of the present disclosure.
As shown in fig. 4(a), a transistor can be formed over a substrate 2001. There are many ways in the art to form various forms of transistors, such as MOSFETs, which are not described in detail herein. Fig. 4(a) shows an example of one transistor. As shown in fig. 4(a), the transistor may include a gate stack (including a gate dielectric layer 2025 and a gate electrode layer 2027), a gate sidewall spacer 2029 formed around the gate stack, and a source/drain region 2031. Further, Shallow Trench Isolation (STI)2023 is also shown in fig. 4 (a).
An interlayer dielectric layer 2033 may be formed on the substrate on which the transistor is formed, and contacts 2035-1, 2035-2, and 2035-3 that contact the gate and each source/drain region of the transistor may be formed in the interlayer dielectric layer 2033. As for the interlayer dielectric layer and the contact, the above description can be referred to.
Next, as shown in fig. 4(b), another interlayer dielectric layer 2037 (e.g., nitride) may be formed on the interlayer dielectric layer 2033. In the interlayer dielectric layer 2037, a trench R1 may be formed, for example, by etching, and then a capacitive component may be formed in this trench R1. In this example, the trench R1 is located to correspond to a source/drain region (source/drain region on the right side in fig. 4 (b)) to which the capacitance element is to be connected, and penetrates the interlayer dielectric layer 2037 to expose a contact portion 2035-3 corresponding to the source/drain region.
Subsequently, various material layers may be filled into the trench R1 to form a capacitive component. In this example, a conductive diffusion barrier layer 2039 (e.g., TiN, having a thickness of about 1-10nm, which may be formed by Atomic Layer Deposition (ALD)), a metal electrode material layer 2041 (e.g., W, having a thickness of about 5-50nm, which may be formed by ALD, Chemical Vapor Deposition (CVD), etc.), a conductive diffusion barrier layer 2043 (e.g., TiN, having a thickness of about 1-10nm, which may be formed by ALD), a negative capacitance material layer 2045 (e.g., HfZrO), for example, may be formed in sequence in the trench R12About 3-15 nm thick and can be formed by ALD), a conductive diffusion barrier layer 2047 (e.g., TiN with a thickness of about 1-10nm and can be formed by ALD), a high-K dielectric layer 2049 (e.g., HfO)2About 3 to 15nm thick and can be formed by ALD), a conductive diffusion barrier layer 2051 (e.g., TiN, about 1 to 10nm thick and can be formed by ALD), and a metal electrode material layer 2053 (e.g., W, can be formed by ALD, CVD, etc.). In this case, the conductive diffusion barrier layer 2039, the metal electrode material layer 2041, and the conductive diffusion barrier layer 2043 (first conductive layer) -negative capacitance material layer 2045-conductive diffusion barrier layer 2047 (second conductive layer) may constitute a negative capacitor. Here, the first conductive layer includes a metal electrode material layer 2041, which is for better low ohmic contact with the underlying contact 2035-3; the conductive diffusion barrier layer 2039 and the conductive diffusion barrier layer 2043 may prevent the metal electrode material layer 2041 from diffusing into other layers (e.g., the negative capacitance material layer 2045). In addition, the conductive diffusion barrier layer 2047 (second conductive layer) -the high-K dielectric layer 2049-the conductive diffusion barrier layer 2051 and the metal electrode material layer 2053 (third conductive layer) may form a positive capacitor. Here, the third conductive layer includes a layer 2053 of metal electrode material for better forming a low ohmic contact with a subsequently formed contact (see 2059-3 in fig. 4 (d)); the conductive diffusion barrier 2051 may prevent diffusion of the metal electrode material layer 1021 into other layers. For example, the conductive diffusion barrier layer 2039, the metallic electrode material layer 2041, the conductive diffusion barrier layer 2043, the negative capacitance material layer 2045, the conductive diffusion barrier layer 2045, and the conductive electrode material layer 2045 may be deposited in a substantially conformal manner in that orderA sexual diffusion barrier 2047, a high-K dielectric layer 2049, a conductive diffusion barrier 2051, and a layer 2053 of metal electrode material are deposited to fill trench R1, followed by a planarization process such as CMP to fill the trenches R1 with these layers.
In this example, negative capacitance material layer 2045 is formed first, and then dielectric layer 2049 is formed. However, the present disclosure is not limited thereto. For example, the layer of negative capacitance material may be formed first, followed by the formation of the dielectric layer.
Further, as shown in fig. 4(d), in the 0 interlayer dielectric layer 2037, contact portions 2055-1 and 2055-2 corresponding to the contact portions 2035-1 and 2035-2 may be formed. Thereafter, a further interlayer dielectric layer 2057 (e.g., nitride) may be formed. In the interlayer dielectric layer 2057, contacts 2059-1, 2059-2, and 2059-3 may be formed corresponding to the contacts 2055-1 and 2055-2 and the capacitor element (specifically, the metal electrode material layer 2053). The contacts 2059-1, 2059-2, and 2059-3 may correspond to terminals T1, T2, and T3, respectively, in fig. 1.
Fig. 5 is a sectional view showing a configuration of a memory cell according to another embodiment of the present disclosure.
The memory cell shown in fig. 5 is substantially the same as the memory cell shown in fig. 4(d), except that the conductive diffusion barrier layer 2047 as the second conductive layer is omitted. In this example, the conductive diffusion barrier layer 2039, the metal electrode material layer 2041, and the conductive diffusion barrier layer 2043 (first conductive layer) constitute one plate of the capacitive assembly, the conductive diffusion barrier layer 2051 and the metal electrode material layer 2053 (third conductive layer) constitute the other plate of the capacitive assembly, and the stack of the negative capacitive material layer 2045 and the high-K dielectric layer 2049 constitute the capacitive medium of the capacitive assembly. Likewise, the order of negative capacitance material layer 2045 and high-K dielectric layer 2049 may be switched.
The memory device according to the embodiments of the present disclosure may be applied to various electronic devices. Such as smart phones, tablet computers (PCs), Personal Digital Assistants (PDAs), etc.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (14)

1. A memory cell, comprising:
a transistor; and
a capacitive component connected to the transistor and having a capacitance,
the capacitor assembly includes a positive capacitor and a negative capacitor connected in series with each other;
the capacitor assembly is formed into a groove capacitor, the groove is U-shaped and comprises two vertical side walls and a bottom wall connected with the vertical side walls;
the capacitor assembly includes a stack of a first conductive layer-a dielectric layer-a second conductive layer-a negative capacitor material layer-a third conductive layer; and each conductive layer comprises a layer of metallic electrode material.
2. The memory cell of claim 1, wherein the material of the negative capacitance material layer is a Zr, Ba, or Sr containing material.
3. The memory cell of claim 1, wherein the material of the negative-capacitance material layer comprises one of: HfZrO2、BaTiO3、KH2PO4Or NBT.
4. The memory cell of claim 1, wherein an absolute value of a capacitance of the negative capacitor is greater than or equal to a capacitance value of a positive capacitor.
5. The memory cell of claim 1, wherein the capacitive component is formed on a substrate on which the transistor is formed, and the first conductive layer or the third conductive layer comprises a doped region in the substrate.
6. The memory cell of claim 5, wherein the doped region is coupled to one of the source/drain regions of the transistor, thereby coupling the capacitive component to the transistor.
7. The memory cell of claim 1, wherein the second conductive layer comprises a layer of conductive diffusion barrier material.
8. The memory cell of claim 1, wherein at least one of the first conductive layer and the third conductive layer comprises a stack of a conductive diffusion barrier material layer and a metal electrode material layer.
9. The memory cell of claim 7 or 8, wherein the conductive diffusion barrier material layer comprises TiN.
10. The memory cell of claim 8, wherein the metal electrode material layer comprises W.
11. The memory cell of claim 8, wherein the capacitive component is formed in a metallization stack over a transistor.
12. The memory cell of claim 11, wherein the first conductive layer or the third conductive layer proximate to the underlying layer comprises a stack of a conductive diffusion barrier material layer-a metal electrode material layer-a conductive diffusion material layer.
13. A memory device comprising a plurality of memory cells according to any one of claims 1 to 12.
14. An electronic device comprising the memory device of claim 13.
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