CN1290038A - Piled capacitor memory units and manufacture thereof - Google Patents
Piled capacitor memory units and manufacture thereof Download PDFInfo
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- CN1290038A CN1290038A CN99120763.7A CN99120763A CN1290038A CN 1290038 A CN1290038 A CN 1290038A CN 99120763 A CN99120763 A CN 99120763A CN 1290038 A CN1290038 A CN 1290038A
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- memory cell
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- 239000003990 capacitor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 208000005189 Embolism Diseases 0.000 claims description 16
- 229910052697 platinum Inorganic materials 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229910004200 TaSiN Inorganic materials 0.000 claims description 5
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 229910010037 TiAlN Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 230000005669 field effect Effects 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 22
- 239000000758 substrate Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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Abstract
A memory unit if composed of field effect transistor and stack capacitor. Said stack capacitor has a plate electrode formed by the Pt layer on the side wall positioned at medium layer part. Said medium layer is overlapped on the conductive layer of memory node. The medium layer of capacitor is overlapped on the side wall and upper part of said medium layer. The another plate electrode of the capacitor is formed by the Pt layer on the medium of capacitor.
Description
The present invention relates to a kind of dynamic random access memory (DRAM), particularly a kind of memory cell and manufacture method thereof that is used to comprise the DRAM of field-effect transistor and stacked capacitor.
DRAM is one of most important integrated circuit.A kind of typical DRAM comprises the memory cell of the big array that is arranged in rows and columns, each memory cell be used to store can control unit the binary digit that reads in and read (position).In order to store the data bit of write and read operation room, each memory cell generally comprises and is generally the switch series capacitors of MOS transistor.For the memory cell of big array is provided on single silicon chip, importantly adopt to take chip area and memory cell that can intensive encapsulation.Because this switching transistor must be arranged in silicon wafer, so thereby a kind of formation of memory cell is by forming the holding capacitor conserve space on the upper surface of silicon rather than in silicon inside.Because general by multilayer laminated formation the on the silicon upper surface, so the capacitor that forms is commonly referred to stacked capacitor like this.
Because the little density height of size of this capacitor on the chip upper surface so need to form their technology, the invention provides a kind of improvement technology that forms this stacked capacitor.
The present invention is devoted to comprise the memory cell and the manufacture method thereof of transistor and stacked capacitor.
The following manufacturing of this memory cell:
At first, prepare the silicon that has formed field-effect transistor on its upper surface with leakage and source region.The source region is electrically connected with the bottom crown of stacked capacitor.Claim this current terminal for leaking for convenience.Generally speaking, the upper surface of chip has blanket dielectric layer, except that stacked capacitor, wherein also will comprise providing to memory cell writing and reading the bit line of usefulness and each layer of word line from memory cell.
For forming stacked capacitor, at first in dielectric passivation, form the contact hole of aiming at the source of the memory node that is used as memory cell.Preferably this hole utilizes anisotropic etch to form, thereby this hole can have vertical substantially sidewall.
Behind the formation hole,, form the conductive plug that generally constitutes, thereby form and be used as the low resistance connection of the transistor drain of memory node by highly doped polysilicon with conductor filled this hole.Produce good the connection in order to ensure embolism, preferably cross and fill this embolism, general using chemico-mechanical polishing then (CMP) complanation should the surface.
Though can omit, preferably then cover the upper surface of embolism with diffusion impervious layer, this layer is connected with embolism generation with the conduction that will be deposited on the metal level that is preferably platinum on the barrier layer subsequently, this metal level will be as first pole plate or the memory node of stacked capacitor.This diffusion impervious layer for example will be as the barrier layer, stop any unwanted material for example polysilicon be diffused in this metal level.This is even more important when not wishing that platinum with pasc reaction constitutes at this metal level.Suitable barrier material comprises TiN, TaSiN and TiAlN.
After forming the barrier layer, blanket dielectric layer.This dielectric layer of photoetching composition, staying in former dielectric layer with the conductive plug is the limited portion at center.The surface area of this qualifying part sidewall of dielectric layer will be provided by capacitance to a great extent that provided, so will select the size of this part suitably.
Then, depositing metal on the sidewall of this qualifying part, preferably platinum.Randomly, this metal can also cover upper surface.This metal will be as the bottom crown of capacitor.
Then, corrosion barrier layer makes it conformal.Then, on platinum layer, be conformally formed the material layer of the medium that is suitable for use as stacked capacitor.
At last, deposit second metal level on condenser dielectric also is a platinum preferably, finishes capacitor.This will form capacitor second (on) pole plate, this pole plate generally remains on fixed potential, generally is earth potential.
From the device aspect, the present invention is devoted to memory cell.This memory cell is included in the semiconductor body that its upper surface has first and second districts of a kind of conduction type that the mesozone by films of opposite conductivity separates, and is used to form transistor and capacitor.This capacitor is formed in first district, comprising: the conductive plug that electrically contacts with said first district; Constitute the conductive layer of folding the diffusion impervious layer on said embolism; Fold on the said barrier layer and be positioned at dielectric layer part on the said embolism; The first metal layer on the sidewall of said at least dielectric layer, this layer and barrier layer electrically contact, as the internal polar plate of capacitor; Conformally surround the layer of dielectric material of the last and sidewall surfaces of said dielectric layer part, this layer material is as condenser dielectric; Second metal level, it is conformally folded on last-mentioned layer of dielectric material, as the external polar plate of capacitor.
From process aspect, the present invention is devoted to form the method for memory cell.This method may further comprise the steps: form transistorized source that separates and drain region on the upper surface of silicon body; On the upper surface of silicon body, form dielectric passivation; Folding in will a part, form contact hole with basic vertical sidewall as the dielectric passivation of the spaced regions of the memory node of unit; Fill this contact hole with electric conductor, be formed into the conductive plug of said last-mentioned spaced apart regions; On conductive plug, form electrically conductive barrier; On electrically conductive barrier, form the dielectric layer part; On the sidewall at least of dielectric layer part, form conductive layer, as the internal polar plate of holding capacitor; Form dielectric layer on said last-mentioned conductive layer, the top of this dielectric layer part is suitable for the dielectric layer as holding capacitor; On the dielectric capacitor layer, form conductive layer, as the external polar plate of holding capacitor.
From the concrete introduction below in conjunction with each accompanying drawing, the present invention may be better understood.
Fig. 1 has showed the circuit diagram and the semiconductor section of the memory cell of typical existing DRAM;
Fig. 2 has showed and has comprised the storage chip that schematically is shown in the stacked capacitor on its upper surface; And
Fig. 3-9 has showed the manufacture method of the stacked capacitor of the present invention of the memory cell that has adopted Fig. 2.
Notice that each accompanying drawing is not drawn in proportion.
Fig. 1 has showed the existing memory cell 10 of the typical case who is used for present many DRAM.Show memory cell 10 and semiconductor device has been shown with the circuit diagram form with profile.This unit comprises the capacitor 18 with the first and second pole plate 18a and 18b, and isolated-gate field effect transistor (IGFET) (IGFET), and this transistor is known as mos field effect transistor (MOSFET).IGFET is formed in the semiconductor body (substrate) 11, comprises the drain region 12 and the source region 13 that are separated by the part of substrate 11.Dielectric layer 14 covers will distinguish the 12 and 13 that part of substrates 11 of isolating, and be expressed as gate oxide.Grid conductor 15 cover layers 14 with the coupling of the word line of DRAM.At least the part of covering leakage is the contact 16 of being coupled to the bit line of DRAM.At least the part of the area of coverage 13 is the contact 17 of being coupled to the pole plate 18a of capacitor 18.The pole plate 18b of capacitor 18 generally is coupled to fixed potential, is depicted as ground 19.The district 12 that has been expressed as leakage becomes the source in some part of memory cell 10 operations.The district 12 that has been expressed as the source becomes leakage in some part of memory cell 10 operations.Substrate 11 is generally n type silicon, and district 12 and 13 is the p type.For the n channel transistor, substrate 11 is p types, and district 12 and 13 is the n type.After signal put on bit line and word line, binary digit write capacitor 18 and reads from capacitor 18.
Fig. 2 shows the big p type profile partly that must be enough to hold the silicon body (substrate) 20 of a memory cell of the present invention.In the upper surface 21 of substrate 20, form two n type district 20a and 20b that separated by the part of substrate 20, form transistorized source and leakage.Dielectric layer 22a is that gate oxide is folded on the part of the substrate 20 between district 20a and 20b, and grid 22b folds on layer 22a.Be coated with the layer 24 that is mainly dielectric material on the upper surface 21, be generally the combination of silica and silicon nitride layer, comprising as bit line and word line and be connected the various conductive layer (not shown) that contact the embolism (not shown) of transistor terminal and these lines.
The capacitor that is depicted as stacked capacitor will be formed in the groove 23 that extends through floor 24 arrival downwards district 20a.
Fig. 3 has showed the part of the structure of Fig. 2, comprises district 20a, floor 24 and contact hole 23.For forming stacked capacitor of the present invention, at first in dielectric layer 24, form contact hole 23, expose the part of the district 20a of substrate 20.This contact hole preferably has vertical sidewall, generally under the mask control that is formed by well known photolithography composition technology, utilizes the reactive ion etching (RIE) of anisotropic etch to form.
In accompanying drawing subsequently, only show part dielectric layer 24, wherein be formed with the stacked capacitor of the transistorized n type district 20a of low resistance connection.
As shown in Figure 4, fill this contact hole, be formed into the low-resistance conduction contact embolism 26 of the bottom region 20a of substrate 20 with the electric conducting material of the polysilicon that is generally the doping of n type.In order to fill reliably, the enough polysilicons of general using chemical vapor deposition (CVD) deposit with blanket dielectric layer 24 surfaces, utilize known chemico-mechanical polishing (CMP) complanation should the surface then, only stay filler.
Also as shown in Figure 4, then, the district that surrounds contact embolism 26 preferably covers with the electrically conductive barrier 27 that is generally electric conducting materials such as TaSiN, can be used for limiting the migration from polysilicon silicon fill of the outdiffusion of n type dopant or silicon.Its thickness does not need thicker, as long as just be enough to stop effectively can.Any dielectric layer 28 covers this barrier layer in silica, silicon nitride or the silicon oxynitride with being generally then.
Then, as shown in Figure 5, it is the layer 28a at center with contact embolism 26 basically that this dielectric layer 28 is trimmed to, and this layer generally has the cross section greater than embolism, because the surface area of its sidewall is the surface area of capacitor plate basically.
Then, as shown in Figure 6, on the sidewall of dielectric layer 28a, form the metal level 29 that is preferably platinum at least.Preferably, it can also deposit becomes the upper surface of blanket dielectric layer 28a, and is shown in Figure 9 as what will discuss later on.If desired 29 on layer is restricted on the sidewall, general preferably even deposit platinum on all exposed surfaces of layer 28a, utilize then known way for example ion beam milling remove the platinum that does not need the position.Then, remove all the other expose portions on barrier layer 27 again, stay structure shown in Figure 7.The platinum layer 29 that is retained on layer 28a sidewall will be as the bottom crown of capacitor, and this pole plate will be connected with the current terminal of switching transistor, as shown in Figure 1.
Then, as shown in Figure 8, and then deposit will be as the dielectric layer 30 of capacitor dielectric and will be as the metal level 31 of capacitor top crown.Dielectric layer 30 should constitute by having high dielectric constant materials, and barium strontium titanate for example is to provide holding capacitor needed high capacitance.Metal level 31 should by good conductor preferably platinum constitute.Generally the part that need be used as the dielectric layer 30 of condenser dielectric is extended fully to prevent capacitor each several part and any misalignment that contacts embolism.Generally will on the surface of chip, extend as the skin 31 of capacitor external polar plate, with serve as with array in similar role in other unit.
In the embodiment shown, the height of the stacked capacitor on contact embolism 26 upper surfaces is about 0.25 micron, and the thickness of layer 27 is about 200-500 dust, and the width of the dielectric layer 28a between the vertical sidewall of layer 29 is about three characteristic sizes.The degree of depth of layer 28 is about a characteristic size.
Fig. 9 shows another embodiment of the present invention, and except that the layer 29 of Fig. 7 extends the layer 29a become on layer 28a, the embodiment of this embodiment and Fig. 8 is very similar.This extension 29a of layer 29 has increased the electric capacity of stacked capacitor.
Because metal level 31 is generally in earth potential work, so can be attached thereto at other layer of earth potential work.
Should be understood that the embodiment that is introduced only is used to show the present invention.Under the situation that does not break away from the spirit and scope of the present invention, can make the various shapes that change.For example, the layer that is generally the layer 28a of silica and is generally platinum can use silicon nitride layer between 29, to improve a layer 28a, 29 and the adhesiveness of 29a.In addition, can use the material except that above-mentioned material to replace above-mentioned material, as long as these other materials have the characteristic of used each concrete layer.For example, can replace platinum to form capacitor with metals such as for example iridium, copper or gold.Can replace barium strontium titanate with similar other material with high-k.In addition, can select generally to be essentially the contact embolism of rectangle and the shape in the cross section of layer 28a on request, so that make.
Claims (12)
1 one kinds of memory cell comprise:
Semiconductor body, the part of its upper surface have first and second districts of a kind of conduction type that the mesozone by films of opposite conductivity separates, and are used to form transistor;
Be formed at the capacitor in first district, comprise:
The conductive plug that electrically contacts with said first district;
The conductive layer of the diffusion impervious layer on said embolism is folded in formation;
Fold on the said barrier layer and be positioned at dielectric layer part on the said embolism;
At least the first metal layer on the said dielectric layer sidewall, itself and barrier layer electrically contact, as the internal polar plate of capacitor;
Conformally surround the layer of dielectric material of the last and sidewall surfaces of said dielectric layer part, as condenser dielectric; And
Conformally fold second metal level on said last-mentioned layer of dielectric material, as the external polar plate of capacitor.
2 memory cell according to claim 1, wherein conductive plug is made of the polysilicon that is doping to a kind of conduction type.
3 memory cell according to claim 2, wherein two metal levels all are made of platinum.
4 memory cell according to claim 3, wherein the barrier layer is made of a kind of material that is selected among TiN, TaSiN and the TiAlN.
5 memory cell according to claim 1, wherein the first metal layer also extends on the upper surface of said dielectric layer.
6 memory cell according to claim 3, wherein the dielectric layer as electrode for capacitors is made of barium strontium titanate.
7 memory cell according to claim 1, wherein semiconductor body is a silicon.
8 one kinds of methods that form memory cell may further comprise the steps:
On the upper surface of silicon body, form transistorized source that separates and drain region;
On the upper surface of silicon body, form dielectric passivation;
Folding in will a part, form contact hole with basic vertical sidewall as the dielectric passivation in the district that separates of the memory node of unit;
Fill this contact hole with electric conductor, be formed into the conductive plug in the said last-mentioned zone that is spaced;
On conductive plug, form electrically conductive barrier;
On electrically conductive barrier, form the dielectric layer part;
On the sidewall at least of dielectric layer part, form conductive layer, as the internal polar plate of holding capacitor;
Form dielectric layer on said last-mentioned conductive layer, the top of this dielectric layer part is suitable for the dielectric layer as holding capacitor; And
On dielectric layer, form conductive layer, as the external polar plate of holding capacitor.
9 according to Claim 8 methods, wherein contact hole forms and has vertical sidewall, and the conductive layer that constitutes the pole plate of capacitor is made of platinum.
10 according to Claim 8 methods, wherein the barrier layer is selected from TiN, TaSiN and TiAlN.
11 methods according to claim 9, wherein condenser dielectric is a barium strontium titanate.
12 according to Claim 8 methods, wherein semiconductor body is a silicon, and conductive plug is a polysilicon, and each metal level is a platinum, and condenser dielectric is a barium strontium titanate, diffusion impervious layer is made of the material that is selected from TiN, TaSiN and TiAlN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99120763.7A CN1290038A (en) | 1999-09-28 | 1999-09-28 | Piled capacitor memory units and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99120763.7A CN1290038A (en) | 1999-09-28 | 1999-09-28 | Piled capacitor memory units and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1290038A true CN1290038A (en) | 2001-04-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99120763.7A Pending CN1290038A (en) | 1999-09-28 | 1999-09-28 | Piled capacitor memory units and manufacture thereof |
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| Country | Link |
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| CN (1) | CN1290038A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751243A (en) * | 2011-04-20 | 2012-10-24 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method of semiconductor device |
| CN111900168A (en) * | 2016-01-25 | 2020-11-06 | 中国科学院微电子研究所 | Memory cell, memory device and electronic apparatus |
-
1999
- 1999-09-28 CN CN99120763.7A patent/CN1290038A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751243A (en) * | 2011-04-20 | 2012-10-24 | 旺宏电子股份有限公司 | Semiconductor device and manufacture method of semiconductor device |
| CN111900168A (en) * | 2016-01-25 | 2020-11-06 | 中国科学院微电子研究所 | Memory cell, memory device and electronic apparatus |
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