CN1627504A - Method for improving contact resistance value of bit line - Google Patents
Method for improving contact resistance value of bit line Download PDFInfo
- Publication number
- CN1627504A CN1627504A CN200310121355.8A CN200310121355A CN1627504A CN 1627504 A CN1627504 A CN 1627504A CN 200310121355 A CN200310121355 A CN 200310121355A CN 1627504 A CN1627504 A CN 1627504A
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- Prior art keywords
- layer
- insulating barrier
- conductive
- polysilicon
- bit line
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- 238000000034 method Methods 0.000 title claims description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 37
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 40
- 230000008569 process Effects 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 150000003657 tungsten Chemical class 0.000 claims 2
- 238000005546 reactive sputtering Methods 0.000 claims 1
- 239000002210 silicon-based material Substances 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- 239000012528 membrane Substances 0.000 description 6
- 230000005055 memory storage Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000002650 habitual effect Effects 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- -1 tungsten metals Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Through depositing polysilicon thin film layer in hemishere shape on bit line contact, the invention increases contact area of polysilicon layer. Hemisphere shaped polysilicon increases contact area and reduces resistance value. Thus, in dynamic memory, current from upper layer is easy to pass through array type transistors swimmingly so as to reduce problem of high value of resistance relatively.
Description
Technical field
It is relevant to form the bit line connector in the present invention and the semiconductor, especially a kind ofly utilizes coarse spherical polysilicon membrane strengthening its contact area, thereby reduces a kind of method of bit line contact resistance value.
Background technology
Because memory storage is widely used on various application, memory storage such as DRAM (Dynamic Random Access Memory) are flourish fast in recent years.Wire density in the memory storage is grown up in recent years significantly fast.Integrated circuit (IC) design person, usually in the face of how in the wafer circuit, increase memory size and effect with limited space, but must not increase the area of circuit in large quantities.
DRAM (Dynamic Random Access Memory) is put together by millions of identical circuit, is called the Dram born of the same parents, and this Dram born of the same parents are an address (address), to store the data of a bit.Dram born of the same parents' making comprises that a transistor, an electric capacity contact a character line and a reference voltage with a bit line.
The Dram manufacturing is a high emulative cause.There is pressure continuously in manufacturer always, forces them must reduce its size dimension in single born of the same parents, and increases the density of memory cell, gets into a single memory wafer to allow more internal memory.
For making chip hold more substantial internal memory, cause the capacitor design of Dram manufacturer towards three-dimensional, comprise stack type electric capacity (stacked capacitors), this kind stack type electric capacity is put on access transistor.
On the other hand, the intraconnections of memory cell, also be the interesting part of Dram memory storage merchant, because the lead live width has very big related with the size of semiconductor device: for example work as live width and reduce to 0.11 micron, semi-conductive size meeting thereby reduce to 75% of original area by 0.14 micron.In addition, when live width reduced to 0.09 micron by 0.14 micron, semi-conductive size will reduce to 50% of original area.Therefore how to effectively reduce the live width of intraconnections, will relatively dwindle the area of semiconductor device.But when the Dram size has been dwindled, the live width of plain conductor but can not be dwindled in response to mos device dwindles principle (shrinking ratio), its reason is that plain conductor can face dwindling of area and makes and the significantly increase of resistance value cause the electric current on upper strata can't flow to smoothly in source, drain and the field oxide of lower floor.In addition, another normal problem of finding is generally can bestow doping (doping) process in the MOS structure to reduce the RC time of delay of gate conducting layer, but in fact because the thickness that mixes only is 2000 to 4000 dusts approximately, because the restriction of leakage current (leakage current), the degree of depth of its doping can not be too dark, otherwise will cause the significantly reduction of yield in the manufacture process, if the circuit of bit line reduces then resistance sometimes even meeting thereby rise to 1000 ohm spectrum relatively; Therefore, the electric current on upper strata will be difficult to effectively arrive the FET zone of MOS, and this situation also can cause the reduction of process rate.
Summary of the invention
The present invention is intended to overcome the problems in the above-mentioned memory storage manufacture process, main purpose provides a method to increase the contact area of polysilicon layer, by depositing one deck dome-type polysilicon membrane in the forming process of bit line contact, therefore the dome-type polysilicon membrane is semi-spherical shape can effectively increase its contact area, and reduces its resistance value relatively.So, the electric current that is come by the upper strata in the Dram just can be easily and the array type transistors of the Dram of flowing through smoothly, thereby make the problem of high resistance to overcome.
The present invention's one purpose provides the polysilicon of identical material, in the Dram manufacture process, can eliminate common heterogeneous joint situation and significantly reduce resistance value.
Another object of the present invention, provide a material and have the dome-type polysilicon membrane, the doped polycrystalline silicon of its material and dome-type polysilicon membrane below belongs to identical material, thereby in the Dram manufacture process, can not produce heterogeneous joint phenomenon (heterojunction) and take place.
These and other characteristics provided by the present invention are only utilized habitual manufacture of semiconductor technology, do not need to use expensive or trifling process, therefore are unlikely to cause the extra increase that spends in the processing procedure.
Description of drawings
Fig. 1 is for showing that memory cell of the present invention comprises gate structure and clearance wall;
Fig. 2 is for showing that memory cell of the present invention comprises BPSG and doped polysilicon layer;
Fig. 3 removes BPSG and doped polysilicon layer formation connector for showing memory cell of the present invention;
Fig. 4 is for showing that memory cell of the present invention comprises the dopant deposition polysilicon layer and the rough polysilicon thin layer is deposited in this connector;
Fig. 5 comprises deposition one deck diffused barrier layer at this above rough polysilicon film for showing memory cell of the present invention;
Fig. 6 comprises deposition one deck tungsten metal level at this above coarse conductive film for showing memory cell of the present invention; And
Fig. 7 comprises etch back process to form the bit line contact for showing memory cell of the present invention.Among the figure
18DRAM born of the same parents' 39 first insulating barriers
40 not busy crack walls, 41 second insulating barriers
43 first conductive layers, 45 second conductive layers
47 the 3rd conductive films, 51 ions are implanted with laser and are handled
53 diffused barrier layers, 55 tungsten metals
64,62 active area, 70 clearance walls
72 clearance walls, 75 lock oxide layers
96 plug open zones
Embodiment
The Dram memory structures are present most popular internal memory treatment system.The present invention recalls the relevant relevant apparatus of structure with discussing with Dram, but is not limited to the Dram memory structures; Opposite, it is broader that it comprises scope, also can comprise other memory structures, as (SRAM) static random access memory; Simultaneously, the present invention can be applied to the correlated process of intraconnections in the semiconductor metallization process.
Below only do an explanation with regard to embodiments of the invention.It must be appreciated this semiconductor structure and manufacture process, only is a variety of examples in may structures.For example, BPSG is used for isolated two conductive layers, and as for other insulation material, for example, phosphorosilicate glass (PSG) or silicon dioxide also can be used for as isolated purposes.Also can use as for electric capacity, stacking type groove or plane formula electric capacity.In addition, cmp or do, wet etching also can be used for etching process.The present invention also should not be limited to special construction as described below.
In addition, the present invention also can be used for other field of manufacture of semiconductor, so long as on the intraconnections of memory storage district and logic control circuit.Therefore, method of the present invention also is suitable for Dram, SRAM, and EDRAM, VDRAM, NVSRAM, NVDRAM, PSDRAM and ROM (EPROM for example, EEPROM, EAROM) and relevant metal interconnecting.
Among Fig. 1, FET comprises two active area 64,62.Lock oxide layer 75 can be made of silica or silicon nitride with clearance wall 70, and lock top insulating barrier 72 is made of silicon nitride or TEOS, and ground then is made of monocrystalline silicon wafer crystal.Be to be used as Background explanation in the present embodiment with this figure.Among Fig. 2, one first insulating barrier 39 is deposited on above the structure of Fig. 1, the material of first insulating barrier can be BPSG and through CMP to polish this surface.Among Fig. 2, one second insulating barrier 41 is deposited on first insulating barrier 39 with above the gate structure, and the material of first insulating barrier can be TEOS.Then one first conductive layer 43 is deposited on above second insulating barrier 41.
Among Fig. 3, for convenience of description for the purpose of, the source in the understructure, drain and active area no longer show.
Process several light shield, etching process are to remove first insulating barrier 39, second insulating barrier 41 and first conductive layer 43 partly to form plug open zone 96.FET zone under this plug open zone 96 can expose is with the usefulness as the metallization intraconnections.
Among Fig. 4, one second conductive layer, 45 conformality ground (conformally) be deposited on plug open zone 96 and first conductive layer 43 above.In fact, the polysilicon of the material of second conductive layer 45 for mixing, this polysilicon layer are to contact with ground FET zone.In addition, the ion implantation is to be used for lowering its resistance value with laser processing 51.Then, one the 3rd conductive layer 47 be deposited on second conductive layer 45 above, the material of the 3rd conductive film 47 is a polysilicon, its shape is similar hemispherical, have another name called hemispherical particle (hemispheric silicon grain, HSG).
Characteristic of the present invention promptly be its hemispheric contact area can than the plane formula contact area of other traditional type come big because the feature that this contact area strengthens can thereby significantly lower its resistance value.Another feature of the present invention is that coarse formula polysilicon membrane is the same with the material of its last layer doped polysilicon layer (doped polysilicon layer), all contain polysilicon, therefore can reduce the possibility that high resistance takes place between different materials in the heterogeneous joint (heterojunction).
Among Fig. 5, one diffused barrier layer 53 be deposited on the 3rd conductive layer 47 above, this diffused barrier layer 53 is to be used for preventing that silicon and intermetallic spike (spike) phenomenon from producing, the material of diffused barrier layer 53 is Ti/TiN, can find out obviously that at this resistance value bigger among the present invention can produce in this layer, this be because of its material obviously with due to other layer material is different significantly.
Among Fig. 6, follow a metal level 55, for example the tungsten metal is deposited on above the 3rd conductive film 47 through selectivity tungsten process (selectivetungsten process) and fills up this plug open zone 96 fully to carry out metallization processes.
Among Fig. 7, then carry out a planarization process, contact to expose this bit line with first conductive layer 43 of part with the tungsten metal level 55 that eat-backs part, the diffused barrier layer 53 of part, hemispherical the 3rd conductive polycrystalline silicon floor 47 of part, second doped polysilicon layer 45 of part.
The present invention is not only applicable to semiconductor Dram processing procedure and is applicable to other field arbitrarily yet, so long as the field of the relevant intraconnections of circuit.Therefore, method of the present invention also is applicable in CMOS processing procedure field and the relevant metal interconnecting process thereof.
The above person only is in order to explain preferred embodiment of the present invention; be not that the attempt tool is to do any pro forma restriction to the present invention; therefore, all have in that identical creation spirit is following do relevant any modification of the present invention or variation, all must be included in the category of rights protection of the present invention.
Claims (18)
1. one kind forms circuit contacts to improve the method for this circuit contacts resistance value, and this method comprises the following step:
Formation source, drain and block the zone on ground;
Form gate structure on ground, this gate structure comprises lock oxide layer, clearance wall and lock top insulating barrier;
Form an active area, this active area comprises source, drain;
Form one first insulating barrier to cover this gate structure and this clearance wall;
Grind this first insulating barrier to expose this lock top insulating barrier with planarization process;
Form one second insulating barrier at this lock top insulating barrier and this is above first insulating barrier;
Form one first conductive layer at this above second insulating barrier;
This first conductive layer, second insulating barrier and this first insulating barrier partly of removing part are to form plug open zone (plug opening);
Form one second conductive doped film at this plug open zone and this first conductive layer, this second conductive doped film contacts with source, drain on the ground;
Form one the 3rd conductive film, this coarse conductive film is that a dome-type shape is at this above second conductive doped thin layer;
Form a diffused barrier layer on the 3rd conductive film;
Form a tungsten metal level on this diffused barrier layer with the open area of this connector;
Eat-back partly this tungsten metal level, this diffused barrier layer, the 3rd conductive film, with this second conductive layer and this first conductive layer to form this circuit contacts.
2. the method for claim 1, this formation active area more comprise and form circuit contacts in this above active area.
3. the method for claim 1, this formation active area more comprise deposition, light shield, etching process to form the bit line contact.
4. the method for claim 1, this forms first insulating barrier and comprises BPSG at least.
5. method as claimed in claim 4, this formation bpsg layer are to polish this surface with cmp.
6. the method for claim 1, this second insulating barrier comprises TEOS at least.
7. the method for claim 1, this first conductive layer comprises polysilicon layer at least.
8. the method for claim 1, this second conductiving doping conductive layer comprises the doped polycrystalline silicon material at least.
9. the method for claim 1, the 3rd conductive layer is a rough polysilicon material.
10. method as claimed in claim 9, this rough polysilicon comprise a plurality of hemispherical dome at least to increase contact area.
11. method as claimed in claim 10, this rough polysilicon are to be used for improving its contact resistance value.
12. the method for claim 1, this second and the 3rd conductive layer is an identical material, and this material comprises polysilicon at least.
13. the method for claim 1, this diffused barrier layer comprises Ti/TiN at least.
14. method as claimed in claim 13, this diffused barrier layer are to deposit with reaction equation sputtering way (reactive sputtering).
15. the method for claim 1, this etch back process comprise most inferior light shields, development, etching process to improve the resistance value of electrode contact.
16. one kind forms the bit line contact to improve the method for this bit line contact resistance value, this method comprises the following step:
Formation source, drain and block the zone on ground;
Form gate structure on ground, this gate structure comprises lock oxide layer, clearance wall and lock top insulating barrier;
Form an active area, this active area comprises source, drain;
Form a bpsg layer and cover this gate structure and this clearance wall;
Grind this bpsg layer to expose this lock top insulating barrier with planarization process;
Form a TEOS layer at this lock top insulating barrier and this is above bpsg layer;
Form a polysilicon layer at this above TEOS layer;
This bpsg layer that removes this polysilicon layer, this TEOS layer and the part of part contacts to form bit line;
Form a doped polycrystalline silicon film layer at this bit line contact area and this above polysilicon layer, this doped polycrystalline silicon film layer is to contact with active area on this ground;
Form a rough polysilicon film, this rough polysilicon film has the dome-type shape at this above doped polycrystalline silicon film layer;
Form a diffused barrier layer at this above rough polysilicon film;
Forming a tungsten metal level contacts with this bit line on this diffused barrier layer; And
Eat-backing this tungsten metal level, this diffused barrier layer, this rough polysilicon film, this doped polycrystalline silicon film layer partly contacts to expose this bit line with this polysilicon layer.
17. method as claimed in claim 16, this bpsg layer are to polish this surface with cmp.
18. method as claimed in claim 16, the purpose of this deposition rough polysilicon film are to increase contact area to improve the too big problem of its resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200310121355.8A CN1627504A (en) | 2003-12-12 | 2003-12-12 | Method for improving contact resistance value of bit line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200310121355.8A CN1627504A (en) | 2003-12-12 | 2003-12-12 | Method for improving contact resistance value of bit line |
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| Publication Number | Publication Date |
|---|---|
| CN1627504A true CN1627504A (en) | 2005-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200310121355.8A Pending CN1627504A (en) | 2003-12-12 | 2003-12-12 | Method for improving contact resistance value of bit line |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930977B (en) * | 2009-06-19 | 2012-07-04 | 万国半导体股份有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) device with tungsten spacing layer in contact hole and preparation method thereof |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN105097775A (en) * | 2015-04-20 | 2015-11-25 | 宁波时代全芯科技有限公司 | Memory body structure and preparation method thereof |
| CN107170706A (en) * | 2016-03-08 | 2017-09-15 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| WO2022179028A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
-
2003
- 2003-12-12 CN CN200310121355.8A patent/CN1627504A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930977B (en) * | 2009-06-19 | 2012-07-04 | 万国半导体股份有限公司 | Power metal oxide semiconductor field effect transistor (MOSFET) device with tungsten spacing layer in contact hole and preparation method thereof |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN104766799B (en) * | 2014-01-07 | 2018-07-06 | 北大方正集团有限公司 | A kind of preparation method of field-effect transistor and corresponding field-effect transistor |
| CN105097775A (en) * | 2015-04-20 | 2015-11-25 | 宁波时代全芯科技有限公司 | Memory body structure and preparation method thereof |
| CN105097775B (en) * | 2015-04-20 | 2017-12-29 | 江苏时代全芯存储科技有限公司 | Memory structure and its preparation method |
| CN107170706A (en) * | 2016-03-08 | 2017-09-15 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| US11232985B2 (en) | 2016-03-08 | 2022-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming contact metal |
| US11791208B2 (en) | 2016-03-08 | 2023-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming contact metal |
| WO2022179028A1 (en) * | 2021-02-25 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure forming method and semiconductor structure |
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