CN105097775B - Memory structure and its preparation method - Google Patents
Memory structure and its preparation method Download PDFInfo
- Publication number
- CN105097775B CN105097775B CN201510188810.9A CN201510188810A CN105097775B CN 105097775 B CN105097775 B CN 105097775B CN 201510188810 A CN201510188810 A CN 201510188810A CN 105097775 B CN105097775 B CN 105097775B
- Authority
- CN
- China
- Prior art keywords
- conductive contact
- height
- hard cover
- insulating barrier
- cover screen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 230000008569 process Effects 0.000 claims description 26
- 239000007789 gas Substances 0.000 description 18
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 238000005240 physical vapour deposition Methods 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 238000007747 plating Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 7
- 229910018503 SF6 Inorganic materials 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 230000008020 evaporation Effects 0.000 description 6
- 239000001307 helium Substances 0.000 description 6
- 229910052734 helium Inorganic materials 0.000 description 6
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 6
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 6
- 229960000909 sulfur hexafluoride Drugs 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000008378 aryl ethers Chemical class 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920000052 poly(p-xylylene) Polymers 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229960004643 cupric oxide Drugs 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical class O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010025 steaming Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 210000003135 vibrissae Anatomy 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of memory structure and its preparation method.Memory structure includes an insulating barrier, a perforation, a conductive contact and a memory cell.Perforation runs through this insulating barrier.Conductive contact has a difference in height then in perforation, and with one first height and one second height between the first height and the second height.And memory cell is located on conductive contact.
Description
Technical field
The present invention is a kind of relevant memory structure, more particularly to a kind of memory structure with larger junction and its
Preparation method.
Background technology
Memory body is to store data or the semiconductor element of data, can be divided mainly into non-volatility memory and volatilization
Two kinds of memory body of property.With flourishing for science and technology, industry is also gradually lifted for the demand of memory body, such as high-reliability,
High erasable number, quick storage speed and Large Copacity etc..Therefore, semiconductor industry ongoing effort develops various technologies to contract
Subtract component size, and increase the component density of memory body.
Generally, memory cell is to be electrically connected to semiconductor element by conductive contact, but reduces component size
The contact area between memory cell and conductive contact is decreased simultaneously, and this will increase junction resistance, and note is greatly reduced
Recall the efficiency of body unit.Therefore, industry is badly in need of developing a kind of memory structure with large contact area, and prepares this note
Recall the method for body structure, it is above-mentioned to solve the problems, such as.
The content of the invention
It is an aspect of the present invention to provide a kind of memory structure, comprising an insulating barrier, a perforation, a conductive contact and
One memory cell.Wherein, perforation runs through insulating barrier, and conductive contact is then in perforation, and have one first height and one
Second height, and there is a difference in height between the first height and the second height.Memory cell is then on conductive contact.
According to one or more embodiments of the invention, a beveled profile or single order are formed between the first height and the second height
Shape profile.
According to one or more of the invention embodiments, angle between beveled profile and a side wall of perforation between 110 to
Between 150 degree.
According to one or more embodiments of the invention, the height formed between the second height of scalariform profile and the first height
Ratio is between 0.5 to 0.8.
According to one or more embodiments of the invention, memory cell includes resistance-type memory body and magnetic-type memory body.
According to one or more embodiments of the invention, a barrier layer surround conductive contact in perforation.
Another aspect of the present invention is to provide a kind of preparation method of memory structure, comprises the steps of.It is initially formed one
Insulating barrier forms a perforation and runs through the insulating barrier in a basic unit.A conductive contact is subsequently formed in perforation；More it is recessed this
Conductive contact, order make it have one first height and one second height, and high with one between the first height and second height
Degree is poor.A memory cell is eventually formed on this conductive contact.
According to one or more embodiments of the invention, depression conductive contact comprises the steps of.Be initially formed a photoresist layer in
On insulating barrier and conductive contact, then photoresist layer is patterned with expose portion conductive contact.Then partially electronically conductive contact is removed, then is moved
Removing photoresistance layer.
According to one or more embodiments of the invention, the conductive contact that is recessed comprises the steps of.It is initially formed a hard cover screen
On insulating barrier and conductive structure, a photoresist layer is re-formed on hard cover screen, and pattern photoresist layer with expose portion hard cover screen.
Then part hard cover screen and part photoresist layer are removed, makes the hard cover screen on conductive contact that there is difference in height with order.Finally removal portion
Divide hard cover screen to be contacted with partially electronically conductive, conductive contact is formed a beveled profile with order.
According to one or more of the invention embodiments, it is with one first etch process while removes part hard cover screen and part
Photoresist layer；With one second etch process, part hard cover screen contacts with partially electronically conductive simultaneously.First etch process and the second etching are made
Journey is a gas plasma etch process, and the gas that gas plasma etch process uses includes sulfur hexafluoride, helium, tetrafluoro
Change carbon, fluoroform or its combination.
According to one or more embodiments of the invention, depression conductive contact comprises the steps of.Be initially formed a photoresist layer in
Insulating barrier is with conductive contact, then patterning photoresist layer with expose portion conductive contact.Partially electronically conductive contact is finally removed, with
Order makes conductive contact form a scalariform profile.
Brief description of the drawings
For allow the present invention above and other purpose, feature, advantage and embodiment can become apparent, appended accompanying drawing it is detailed
Carefully it is described as follows：
Fig. 1 illustrates a kind of profile of memory structure according to some embodiments of the present invention；
Fig. 2 illustrates a kind of profile of memory structure according to other parts embodiment of the present invention；
Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate Fig. 1 memory structure, upper in processing procedure each stage
View；
Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate Fig. 1 memory structure, in cuing open for processing procedure each stage
Face figure.
Fig. 9 A, Figure 10 A, Figure 11 A and Figure 12 A illustrate Fig. 2 memory structure, in the top view in processing procedure each stage；With
And
Fig. 9 B, Figure 10 B, Figure 11 B and Figure 12 B illustrate Fig. 2 memory structure, in the profile in processing procedure each stage.
Embodiment
Multiple embodiments of the present invention, as clearly stated, the details in many practices will be disclosed with accompanying drawing below
It will be explained in the following description.It should be appreciated, however, that the details in these practices is not applied to limit the present invention.Also
It is to say, in some embodiments of the present invention, the details in these practices is non-essential.In addition, for the sake of simplifying accompanying drawing, one
A little known usual structures will be illustrated in a manner of simply illustrating in the accompanying drawings with element.
In addition, relative vocabulary, as " under " or " bottom " with " on " or " top ", it is shown in the accompanying drawings in text for describing
The relation of one element and another element.With respect to vocabulary be for describe device outer different azimuth described in the accompanying drawings be can
With what is be understood.If for example, the device in an accompanying drawing is reversed, element will be described be originally positioned at other elements " under "
Side by be oriented positioned at other elements " on " side.Exemplary vocabulary " under ", particular orientation with reference to the accompanying drawings can include
" under " and " on " two kinds of orientation.Similarly, if the device in an accompanying drawing is reversed, it was positioned at other originally that element, which will be described,
" lower section " of element or " under " will be oriented " top " in the other elements.Exemplary vocabulary " lower section " or " it
Under ", " lower section " and " top " two kinds of orientation can be included.
Please referring initially to Fig. 1.Fig. 1 illustrates a kind of profile of memory structure according to some embodiments of the present invention.Such as
Shown in Fig. 1, a memory structure 100 includes a basic unit 110, a contact zone 112, the conduction of an insulating barrier 120, one perforation 130, one
Contact 140, one memory cell 150 and a conductive layer 160.It is worth noting that, basic unit 110 described herein can include one
Semiconductor layer, metal level and insulating barrier, and contact zone 112 described herein can include the doped region and metal buffer of semiconductor
Layer.Above-mentioned memory structure 100 is electric current is flowed between conductive layer 160 and contact zone and/or basic unit 110.In this hair
In bright section Example, not necessarily, conductive contact 140 can be directly in electrical contact with basic unit 110 for contact zone 112.
Then in basic unit 100, the material of the material selection of insulating barrier 120 includes insulating barrier 120, such as：Silica, nitrogen
SiClx, silicon oxynitride or its combination, in the other parts embodiment of the present invention, the material of insulating barrier 120 can also include silicic acid
Salt, aromatic ether, Parylene (parylene), polymeric fluorochemical, noncrystalline fluorocarbons, diamond structures carbon, porous silicate,
Porous pi and porous aromatic ether.
Perforation 130 runs through insulating barrier 120 to expose the contact zone 112 in basic unit 110, and conductive contact 140 is positioned at perforation
In 130, and the contact zone 112 being electrically connected in perforation 130.The material of conductive contact 140 includes tungsten, copper, nickel, more
Crystal silicon or its combination, but be not limited.Conductive contact 140 in perforation 130 has one first height H1 and one second
Height H2, and there is a difference in height between the first height H1 and the second height H2.Referring to Fig. 2, the first height described herein
H1 and the second height H2 means the height of conductive contact 140 in basic unit 110.In this embodiment, a beveled profile 142 from first
Height H1 extends to the second height H2, and the angle α between beveled profile 142 and a side wall of perforation 130 is between 100 to 170
Between degree, preferably between 110 degree to 150 degree.In addition, the rough thickness T1 for being same as insulating barrier 120 of the first height H1, also
That is the first height H1 can be identical with the thickness T1 of insulating barrier, or the slightly less than thickness T1 of insulating barrier.In other words, conductive contact
140 be dishing relative to the upper surface of insulating barrier 120, but this dishing processing procedure and heterogeneous reduces conductive contact 140
Highly, the height of its side is only reduced to the second height H2 from the first height H1, to form leading with beveled profile 142
Electrical contact 140.In the other parts embodiment of the present invention, the first height H1 of conductive contact 140 extends to the second height H2
Profile also can be cambered surface profile.
In addition, memory structure 100 also has a barrier layer 170 in perforation 130, and around conductive contact 140.Cause
Conductive material in conductive contact 140 is easily spread in a manner of electrically migrating.Electrically migration is there may be whiskerses, and influences
Its neighbouring circuit.When being contacted with silicon, conductive material will more destroy the running of semiconductor element.Therefore, barrier layer need to be used
170 situation to prevent conductive material from spreading occurs.
Memory cell 150 then on conductive contact 140 and contacts conductive contact 140, makes memory cell 150 with order
It is electrically connected to contact zone 112.Contact zone 112 is had no in memory structure 100 in the section Example of the present invention, conduction connects
It is directly to be electrically connected to basic unit 110 to touch 140.Compared to it is known have flush the conductive contact in face, the invention discloses conduction
The beveled profile 142 of contact 140 adds its contact area between memory cell 150, reduces junction resistance, and then
Lift the efficiency of memory structure 100.Conductive layer 160 is then located on memory cell 150, to be electrically connected to memory cell
150.In the section Example of the present invention, memory cell 150 is a resistive random access memory body (resistive
Random access memory, RRAM), it is located at hearth electrode and top comprising a hearth electrode, a top electrode and monoxide layer
Between electrode.Wherein the material of hearth electrode and top electrode include platinum, gold, silver or its combine, and the material of oxide skin(coating) includes oxygen
Change nickel, zinc oxide, cupric oxide, zirconium oxide, titanium oxide, hafnium oxide or its combination.In the other parts embodiment of the present invention,
Memory cell 150 can be a magnetic-resistance random access memory body (magnetoresistive random-access
Memory, MRAM), comprising a reference layer, a free layer and monoxide layer between reference layer and free layer.At this
In the other parts embodiment of invention, the material of conductive layer 160 is included comprising tungsten, copper, nickel, polysilicon or its combination, but not with
This is limited.
Please referring next to Fig. 2 to understand the other embodiment of the present invention, Fig. 2 illustrates to be implemented according to other parts of the present invention
A kind of profile of memory structure of mode.It will be understood that the element material described will not be repeated again and repeat.Following
In narration, the memory structure of other embodiment will be described.
As shown in Fig. 2 a memory structure 200 includes a basic unit 110, an insulating barrier 120, one is perforated, and 130, one conduction connects
Touch 240, one memory cell 150 and a conductive layer 160.It is worth noting that, basic unit 110 described herein can include half
Conductor layer, metal level and insulating barrier, and contact zone 112 described herein can include the doped region and metal buffer of semiconductor
Layer.Above-mentioned memory structure 100 is electric current is flowed between conductive layer 160 and contact zone and/or basic unit 110.In this hair
In bright section Example, not necessarily, conductive contact 140 can be directly in electrical contact with basic unit 110 for contact zone 112.
Insulating barrier 120 is then located in basic unit 110, and perforates 130 through insulating barrier 120 to expose the contact in basic unit 110
Area 112.Conductive contact 240 is then located in perforation 130, to be electrically connected to the contact zone 112 being exposed in perforation 130.At this
Contact zone 112 is had no in the section Example of invention in memory structure 100, conductive contact 140 is directly to be electrically connected to base
Layer 110.Conductive contact 240 has one first height H4 and one second height H3, and between the first height H4 and the second height H3
With a difference in height.Referring to Fig. 2, the first height H4 and the second height H3 described herein means conductive contact in basic unit 110
240 height.The difference of Fig. 2 semiconductor structure 200 and Fig. 1 semiconductor structure 100 is that Fig. 2 conductive contact 240 has
There is a scalariform profile 242 to extend to the second height H3, and the rough thickness for being same as insulating barrier 130 of the first height H4 from the first height H4
Spend T1.That is, first height H4 can be identical with the thickness T1 of insulating barrier, or the slightly less than thickness T1 of insulating barrier.In the portion of the present invention
Divide in embodiment, the second height H3 is less than the first height H4.In the other parts embodiment of the present invention, the second height H3 and the
Height ratio between one height H4 is between 0.5 to 0.8.Conductive contact 240 is recessed relative to the upper surface of insulating barrier 130
Sunkenization, but this dishing processing procedure and the height heterogeneous for reducing conductive contact 240, and it is only that the height of its side is high from first
Degree H4 is reduced to the second height H3, to form the conductive contact 240 with scalariform profile 242.
Memory cell 150 is located on conductive contact 240 and contacts conductive contact 240, makes the electricity of memory cell 150 with order
Property is connected to contact zone 112.The scalariform profile 242 of conductive contact 240 can equally increase its connecing between memory cell 150
Contacting surface is accumulated, and reduces junction resistance, and then lift the efficiency of memory structure 200.Conductive layer 160 is then located at memory cell 150
On, to be electrically connected to memory cell 150.
Refer to Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A and Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B
To understand the preparation method of Fig. 1 memory structure 100.Fig. 3 A, Fig. 4 A, Fig. 5 A, Fig. 6 A, Fig. 7 A and Fig. 8 A illustrate Fig. 1 note
Recall body structure 100, in the top view in processing procedure each stage, and Fig. 3 B, Fig. 4 B, Fig. 5 B, Fig. 6 B, Fig. 7 B and Fig. 8 B illustrate Fig. 1's
Memory structure 100, in the profile in processing procedure each stage.
As shown in Fig. 3 A and Fig. 3 B, insulating barrier 120 is formed in basic unit 110, and is formed perforation 130 and run through insulating barrier 120,
Then conductive contact 140 is re-formed in this perforation 130.Insulating barrier 120 is formed using any suitable mode, such as：Thing
Physical vapor deposition (PVD), chemical vapor deposition (CVD) or ald (ALD).After depositing insulating layer 120, lithographic is utilized
Etching mode forms the perforation 130 through insulating barrier 120, to expose the contact zone 112 in basic unit 110.Then can be used for example
It is sputter (sputtering), evaporation (evaporating), plating (electroplating) or electroless plating (electroless
Plating mode) come deposit conductive material in perforation 130 in, to form conductive contact 140.Implement in the part of the present invention
In example, barrier layer 170 can be initially formed to the side wall of perforation 130, re-form conductive contact 140, barrier layer 170 can pass through physics gas
Mutually deposition, chemical vapor deposition or ald mode are formed.
Please referring next to Fig. 4 A and Fig. 4 B.In Fig. 4 A and Fig. 4 B, a hard cover screen 410 is initially formed in insulating barrier 120 with leading
In electric structure 140, a photoresist layer 420 is subsequently formed on hard cover screen 410, and pattern this photoresist layer 420 with expose portion
Hard cover screen 410.The mode for forming hard cover screen 410 may be, for example, physical vapour deposition (PVD), chemical vapor deposition or ald, connect
On the rotary coating of photoresist layer 420 to hard cover screen 410.The pattern of one light shield (not illustrating) is transferred to photoresist layer using exposure
On 420, to form the first of expose portion hard cover screen 410 the opening 430, and the width of this first opening 430 is D1.
Please referring next to Fig. 5 A and Fig. 5 B.In Fig. 5 A and Fig. 5 B, part hard cover screen 410 and part photoresist layer 420 are removed,
Make the hard cover screen 410 on conductive contact 140 that there is a thickness difference with order.In this step, the first opening of photoresist layer 420 is passed through
430 remove part hard cover screen 420, and are to remove part hard cover screen 420 using the first etch process.It is worth noting that, this
Step will not do too many protection to the side wall of photoresist layer 420, therefore can also remove part while hard cover screen 410 are etched
Photoresist layer 420, the width of the first opening 430 is set to increase to D2 from D1.More clearly, this step is not only etched exposed to first
Hard cover screen 410 in opening 430, the photoresist layer 420 of more lateral etch part, originally it was covered in exposure under photoresist layer 420
Hard cover screen 410.In the case where losing the protection of photoresist layer 420, the first etch process can equally remove these hard cover screens 410, due to hard
The difference of each position etching period length in mask 410, thus the hard cover screen 410 with thickness difference can be formed.First etching
Processing procedure is a gas plasma etch process, its gas used include sulfur hexafluoride, helium, carbon tetrafluoride, fluoroform or
It is combined.By regulate and control gas flow ratio can control the first etch process with and meanwhile remove part hard cover screen 410 and part light
Resistance layer 420, make hard cover screen 410 that there is thickness difference with order.
In the section Example of the present invention, the flow of sulfur hexafluoride between 10~100sccm, helium flow between 20
~100sccm, the flow of carbon tetrafluoride are between the flow of 10~100sccm and fluoroform between 10~30sccm.At this
In the section Example of invention, the first opening 430 formed after the first etch process not exposed conduction can connect as shown in scheming 5B
140 are touched, but is not limited.The first opening 430 formed can also expose conductive contact 140, the spirit without influenceing the present invention.
Please referring next to Fig. 6 A and Fig. 6 B.The step of depression conductive contact 140 are illustrated in Fig. 6 A and Fig. 6 B, order makes its tool
There are the first height H1 and the second height H2, and there is a difference in height between the first height H1 and the second height H2.Such as Fig. 6 A and figure
Shown in 6B, photoresist layer 420 is first removed, part hard cover screen 410 is then removed and contacts 140 with partially electronically conductive, conductive contact is made with order
140 form a beveled profile 142.Wherein, it is to remove part hard cover screen 410 using the second etch process to expose perforation 130
In conductive contact 140.It is worth noting that, the second etch process can remove the partially electronically conductive contact in perforation 130 simultaneously
140.More clearly, the hard cover screen 410 with thickness difference is gradually removed and the original covering of exposure in the second etch process
Conductive contact 140 under it.In the case where losing the protection of hard cover screen 410, the second etch process can equally remove these conductions and connect
140 are touched, and because of the difference of each position etching period length in conductive contact 140, and leading with beveled profile 142 can be formed
Electrical contact 140.Second etch process is similarly a gas plasma etch process, and its gas used includes sulfur hexafluoride, helium
Gas, carbon tetrafluoride, fluoroform or its combination.The second etch process is can control with same time shift by regulating and controlling gas flow ratio
Except part hard cover screen 410 with partially electronically conductive contacts 140, the conductive contact 140 with beveled profile 142 is formed.The present invention's
In section Example, the gas ratio of the first etch process can be same as the gas ratio of the second etch process, but not as
Limit.In the other parts embodiment of the present invention, the gas of the first etch process and the second etch process can be regulated and controled according to process requirement
Body ratio.
Please continue to refer to Fig. 7 A and Fig. 7 B.Illustrate to form memory cell 150 to conductive contact 140 in Fig. 7 A and Fig. 7 B
On step.In this step, deposit memory cell 150 using any suitable mode and be covered in insulating barrier 120 with leading
In electrical contact 140, and the difference of the visual species of memory cell 150, such as：Resistance-type memory body and magnetic-type memory body, with choosing
With suitable deposition materials.For example, if resistance-type memory body to be formed is on conductive contact 140, can first with sputter, steam
Plating, plating or electroless mode form hearth electrode on conductive contact 140, then with physical vapour deposition (PVD), chemical gaseous phase
Deposition or Atomic layer deposition method form oxide layer on hearth electrode, finally use sputter, evaporation, plating or electroless mode again
Top electrode is formed in oxide layer.Then photoresist layer (is not illustrated into) rotary coating to memory cell 150 again.Followed by
The pattern of light shield (not illustrating) is transferred on photoresist layer by exposure, with expose portion memory cell 150.Finally remove exposure
The step of region is with finishing patterns memory cell 150.As shown in 7B figures, memory cell 150 can directly contact conductive
The beveled profile 142 of contact 140, the junction area between memory cell 150 and conductive contact 140 is significantly increased in this, and drops
Low junction resistance.
Finally refer to Fig. 8 A and Fig. 8 B.Illustrate to form conductive layer 160 on memory cell 150 in Fig. 8 A and Fig. 8 B
The step of.In this step, first by sputter, evaporation, plating or it is electroless in a manner of deposit conductive material, such as：Tungsten, copper, nickel,
Aluminium, polysilicon are on insulating barrier 120 and memory cell 150, to form conductive layer 160.Then photoresist layer (not illustrating) is revolved
Turn to be applied on conductive layer 160, and the pattern of light shield (not illustrating) is transferred on photoresist layer using exposure, led with expose portion
Electric layer 160.Then exposed region is removed to complete the wiring of memory structure 100.
Then the description below is referred to further understand the preparation method of other memory structures.Refer to Fig. 3 A and figure
9A, Figure 10 A, Figure 11 A and Figure 12 A, with Fig. 3 B and Fig. 9 BA, Figure 10 B, Figure 11 B and Figure 12 B to understand Fig. 2 memory structure
200 preparation method.Fig. 3 A illustrate Fig. 2 memory structure 200 with Fig. 9 A, Figure 10 A, Figure 11 A and Figure 12 A, each in processing procedure
The top view in stage, and Fig. 3 B illustrate Fig. 2 memory structure 200 with Fig. 9 BA, Figure 10 B, Figure 11 B and Figure 12 B, it is each in processing procedure
The profile in individual stage.
As shown in Fig. 3 A and Fig. 3 B, insulating barrier 120 is initially formed in basic unit 110, and form perforation 130 and run through insulating barrier
120, conductive contact 240 is then re-formed in this perforation 130.Insulating barrier 120, example are formed using any suitable mode
Such as：Physical vapour deposition (PVD), chemical vapor deposition or ald.After depositing insulating layer 120, lithography mode shape is utilized
Into the perforation 130 through insulating barrier 120, to expose the contact zone 112 in basic unit 110.Then e.g. sputter, steaming can be used
Plating, plating or electroless mode come deposit conductive material in perforation 130 in, to form conductive contact 240.In the portion of the present invention
Divide in embodiment, barrier layer 170 can be initially formed to the side wall of perforation 130, re-form conductive contact 140, barrier layer can pass through thing
Physical vapor deposition, chemical vapor deposition or ald mode are formed.
Please referring next to Fig. 9 A and Fig. 9 B.In Fig. 9 A and Fig. 9 B, a photoresist layer 520 is formed in insulating barrier 120 and conduction
In structure 130, and this photoresist layer 520 is patterned with expose portion conductive contact 240.First by the rotary coating of photoresist layer 520 to exhausted
In edge layer and conductive structure, and the pattern of one light shield (not illustrating) is transferred on photoresist layer 520 using exposure, to form exposure
First opening 530 of partially electronically conductive contact 240.
Please referring next to Figure 10 A and Figure 10 B.The step of depression conductive contact 240 are illustrated in Figure 10 A and Figure 10 B, order makes
It has the first height H4 and the second height H3, and has difference in height between the first height H4 and the second height H3.In the present invention
Section Example in, the second height H3 is less than the first height H4.In the other parts embodiment of the present invention, the second height H3
Height ratio between the first height H4 is between 0.5 to 0.8.As shown in Figure 10 A and Figure 10 B, partially electronically conductive connect is removed
240 are touched to form the conductive contact 240 with scalariform profile 242.Wherein, it is to etch to be exposed to remove using gas plasma
First opening 530 in conductive contact 240, the gas used can include sulfur hexafluoride, helium, carbon tetrafluoride, fluoroform or
It is combined.It is worth noting that, need gas flow ratio to make the first opening 530 to protect photoresist layer 520 in this step
Maintained in etching process onesize.In addition, the partially electronically conductive contact 240 in the first opening 530, each of which position
Etching period all same, therefore height from the first height H4 is reduced to the second height H3, to be formed with scalariform profile 242
Conductive contact 240.After the conductive contact 240 that is recessed, you can remove photoresist layer 520.
In addition, the material character of barrier layer 170 is slightly same as conductive contact 240, therefore while conductive contact 240 are recessed
Also the barrier layer 170 of part can be removed, this causes the height of barrier layer 170 slightly to decline.
In the section Example of the present invention, the flow of sulfur hexafluoride between 10~100sccm, helium flow between 20
~100sccm, the flow of carbon tetrafluoride are between the flow of 10~100sccm and fluoroform between 10~30sccm.
Please continue to refer to Figure 11 A and Figure 11 B.Illustrated in Figure 11 A and Figure 11 B and to form memory cell 150 to conduction and connect
Touch the step on 140.In this step, first by photoresist layer rotary coating to memory cell 150.Using any suitable
Mode deposits memory cell 150 and is covered on insulating barrier 120 and conductive contact 240, and the visual species of memory cell 150
Difference, such as：Resistance-type memory body and magnetic-type memory body, to select suitable deposition materials.For example, if resistance to be formed
Formula memory body on conductive contact 240, can first by sputter, evaporation, plating or it is electroless in a manner of form hearth electrode in conduction
In contact 140, oxide layer is then formed in hearth electrode with physical vapour deposition (PVD), chemical vapor deposition or Atomic layer deposition method
On, finally top electrode is formed in oxide layer with sputter, evaporation, plating or electroless mode again.Then recycle exposure will
The pattern of light shield (not illustrating) is transferred on photoresist layer, with expose portion memory cell 150.Finally remove exposed region with
The step of finishing patterns memory cell 150.As shown in Figure 11 B, memory cell 150 can directly contact conductive contact 240
Scalariform profile 242, the junction area between memory cell 150 and conductive contact 240 is significantly increased in this, and reduces junction
Resistance.
Finally refer to Figure 12 A and Figure 12 B.Illustrate to form conductive layer 160 in memory cell in Figure 12 A and Figure 12 B
Step on 150.In this step, first by sputter, evaporation, plating or it is electroless in a manner of deposit conductive material, such as：Tungsten,
Copper, nickel, aluminium, polysilicon are on insulating barrier 120 and memory cell 150, to form conductive layer 160.Then photoresist layer is rotated
It is applied on conductive layer 160, and the pattern of light shield (not illustrating) is transferred on photoresist layer using exposure, it is conductive with expose portion
Layer 160.Then exposed region is removed to complete the wiring of memory structure 200.
From the embodiments of the present invention, the present invention has following advantages.The present invention reduces the height of conductive contact side
Degree, order make conductive contact have difference in height.In addition, more gas flow ratio can be controlled according to process requirement, make the height of conductive contact
Degree difference forms beveled profile or scalariform profile, and this can increase its contact area with memory cell, and then reduces junction electricity
Hinder and lift the efficiency of memory structure.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any to be familiar with this skill
Person, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations, therefore protection scope of the present invention is worked as
It is defined depending on the scope of which is defined in the appended claims.
Claims (2)
1. a kind of preparation method of memory structure, it is characterised in that include：
An insulating barrier is formed in a basic unit；
Form a perforation and run through the insulating barrier；
A conductive contact is formed in the perforation；
A hard cover screen is formed on the insulating barrier and the conductive contact；
A photoresist layer is formed on the hard cover screen, and patterns the photoresist layer with the expose portion hard cover screen；
The part hard cover screen and the part photoresist layer are removed, makes the hard cover screen on the conductive contact that there is a thickness difference with order；
And
Removal part hard cover screen and the part conductive contact, make the conductive contact high with one first height and one second with order
Degree, and form a beveled profile between first height and second height；And
A memory cell is formed on the conductive contact.
2. the preparation method of memory structure according to claim 1, it is characterised in that be same with one first etch process
When remove the part hard cover screen and the part photoresist layer, and continue with one second etch process to remove the part hard cover screen and simultaneously
Remove the part conductive contact.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510188810.9A CN105097775B (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
| CN201711257248.6A CN107833873A (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510188810.9A CN105097775B (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711257248.6A Division CN107833873A (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097775A CN105097775A (en) | 2015-11-25 |
| CN105097775B true CN105097775B (en) | 2017-12-29 |
Family
ID=54577866
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711257248.6A Pending CN107833873A (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
| CN201510188810.9A Active CN105097775B (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711257248.6A Pending CN107833873A (en) | 2015-04-20 | 2015-04-20 | Memory structure and its preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN107833873A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108346616B (en) * | 2017-01-25 | 2021-03-05 | 旺宏电子股份有限公司 | Interconnect structure and method of fabricating the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1627504A (en) * | 2003-12-12 | 2005-06-15 | 南亚科技股份有限公司 | Method for improving contact resistance value of bit line |
| TW200639938A (en) * | 2005-05-06 | 2006-11-16 | Taiwan Semiconductor Mfg Co Ltd | An innovation method to resolve arcing problem |
| CN101740545A (en) * | 2008-11-21 | 2010-06-16 | 三星电子株式会社 | Wiring structure of semiconductor device and method of forming a wiring structure |
| CN102194822A (en) * | 2010-03-01 | 2011-09-21 | 旺宏电子股份有限公司 | Bit line structure, semiconductor element and forming method thereof |
| CN102428554A (en) * | 2009-05-20 | 2012-04-25 | 美光科技公司 | Method For Providing Electrical Connections To Spaced Conductive Lines |
| CN103137849A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Magnetic tunnel junction and forming method thereof |
| CN103151458A (en) * | 2013-03-22 | 2013-06-12 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory array and manufacturing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100396470B1 (en) * | 2001-02-19 | 2003-09-03 | 삼성전자주식회사 | Non-volatile memory device having bitline contact pad and Method of manufacturing the same |
| KR100829556B1 (en) * | 2002-05-29 | 2008-05-14 | 삼성전자주식회사 | Magneto-resistive Random access memory and method for manufacturing the same |
| US7772581B2 (en) * | 2006-09-11 | 2010-08-10 | Macronix International Co., Ltd. | Memory device having wide area phase change element and small electrode contact area |
| US9040951B2 (en) * | 2013-08-30 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistance variable memory structure and method of forming the same |
-
2015
- 2015-04-20 CN CN201711257248.6A patent/CN107833873A/en active Pending
- 2015-04-20 CN CN201510188810.9A patent/CN105097775B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1627504A (en) * | 2003-12-12 | 2005-06-15 | 南亚科技股份有限公司 | Method for improving contact resistance value of bit line |
| TW200639938A (en) * | 2005-05-06 | 2006-11-16 | Taiwan Semiconductor Mfg Co Ltd | An innovation method to resolve arcing problem |
| CN101740545A (en) * | 2008-11-21 | 2010-06-16 | 三星电子株式会社 | Wiring structure of semiconductor device and method of forming a wiring structure |
| CN102428554A (en) * | 2009-05-20 | 2012-04-25 | 美光科技公司 | Method For Providing Electrical Connections To Spaced Conductive Lines |
| CN102194822A (en) * | 2010-03-01 | 2011-09-21 | 旺宏电子股份有限公司 | Bit line structure, semiconductor element and forming method thereof |
| CN103137849A (en) * | 2011-12-02 | 2013-06-05 | 中芯国际集成电路制造(上海)有限公司 | Magnetic tunnel junction and forming method thereof |
| CN103151458A (en) * | 2013-03-22 | 2013-06-12 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory array and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097775A (en) | 2015-11-25 |
| CN107833873A (en) | 2018-03-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9634250B2 (en) | Resistive RAM devices and methods | |
| US10056546B2 (en) | Metal nitride keyhole or spacer phase change memory cell structures | |
| CN105493244B (en) | The method of the parallel wire of different metal material is formed by double patterning and filling technique | |
| CN108962895A (en) | Semiconductor device, electronic system and the method for forming semiconductor device structure | |
| CN104979470A (en) | Rram cell bottom electrode formation | |
| CN106252505A (en) | RRAM device and method | |
| CN104900804A (en) | Rram cell structure with conductive etch-stop layer | |
| CN106158899A (en) | Improve the high k scheme of the holding performance of resistive random access memory (RRAM) | |
| CN101292327A (en) | Method of forming pitch multipled contacts | |
| JP5211483B2 (en) | Solid electrolyte switching element, manufacturing method thereof, and integrated circuit | |
| CN101114608B (en) | Method of forming a metal line of a semiconductor memory device | |
| CN106206937A (en) | There is variable resistance type memorizer and the manufacture method thereof of coat of metal | |
| CN108074911A (en) | Jump pore structure | |
| CN105097775B (en) | Memory structure and its preparation method | |
| CN110098325A (en) | Phase-change memory and its manufacturing method | |
| CN103943775B (en) | Resistive memory element | |
| JP5967835B2 (en) | Via with a substantially flat top surface | |
| WO2016084349A1 (en) | Variable-resistance element and method of manufacturing same, and semiconductor device | |
| JP2008503073A5 (en) | ||
| JP2006332428A (en) | Semiconductor integrated circuit device | |
| KR101159169B1 (en) | Fabrication Method of Phase-Change Random Access Memory Device | |
| CN112310278B (en) | Variable resistance memory and manufacturing method thereof | |
| KR100532405B1 (en) | Method for forming electrodes using electroplating | |
| CN109119328A (en) | To the method for destination layer setting pattern | |
| CN103531532A (en) | Method for forming contact window |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20170628 Address after: No. 188 East Huaihe Road, Huaiyin District, Jiangsu, Huaian Applicant after: Jiangsu times all core storage technology Co.,Ltd. Applicant after: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Applicant after: BEING ADVANCED MEMORY TAIWAN LIMITED Address before: 315195 Zhejiang city of Ningbo province Yinzhou Industrial Park (New Yinzhou District Jiang Shan Zhen Zhang Yu Cun) Applicant before: NINGBO ADVANCED MEMORY TECHNOLOGY Corp. Applicant before: BEING ADVANCED MEMORY TAIWAN LIMITED |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No. 601, Changjiang East Road, Huaiyin District, Huaian, Jiangsu Co-patentee after: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Patentee after: JIANGSU ADVANCED MEMORY TECHNOLOGY Co.,Ltd. Co-patentee after: BEING ADVANCED MEMORY TAIWAN LIMITED Address before: 223001 No. 188 Huaihe East Road, Huaiyin District, Huaian City, Jiangsu Province Co-patentee before: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Patentee before: Jiangsu times all core storage technology Co.,Ltd. Co-patentee before: BEING ADVANCED MEMORY TAIWAN LIMITED |
|
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 802, unit 4, floor 8, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing times full core storage technology Co.,Ltd. Patentee after: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Patentee after: BEING ADVANCED MEMORY TAIWAN LIMITED Address before: 223001 No. 601, Changjiang East Road, Huaiyin District, Huai'an City, Jiangsu Province Patentee before: JIANGSU ADVANCED MEMORY TECHNOLOGY Co.,Ltd. Patentee before: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Patentee before: BEING ADVANCED MEMORY TAIWAN LIMITED |
|
| CP03 | Change of name, title or address | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220124 Address after: 802, unit 4, floor 8, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing times full core storage technology Co.,Ltd. Address before: Room 802, unit 4, floor 8, building 2, yard 9, FengHao East Road, Haidian District, Beijing 100094 Patentee before: Beijing times full core storage technology Co.,Ltd. Patentee before: JIANGSU ADVANCED MEMORY SEMICONDUCTOR Co.,Ltd. Patentee before: BEING ADVANCED MEMORY TAIWAN LIMITED |
|
| TR01 | Transfer of patent right |