CN1236993A - DRAM cell capacitor and method for fabricating thereof - Google Patents
DRAM cell capacitor and method for fabricating thereof Download PDFInfo
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- CN1236993A CN1236993A CN99105863A CN99105863A CN1236993A CN 1236993 A CN1236993 A CN 1236993A CN 99105863 A CN99105863 A CN 99105863A CN 99105863 A CN99105863 A CN 99105863A CN 1236993 A CN1236993 A CN 1236993A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
Abstract
Disclosed is a double pole type stacked capacitor with increased surface area and a manufacturing method thereof. The double pole type stacked capacitor includes: a storage contact pad formed and electrically connected to the source/drain regions of the semiconductor substrate; an insulating layer on the semiconductor substrate including the storage contact pad; a storage electrode of the capacitor having a first conductive pole and a second conductive pole. The first conductive pole and the second conductive pole are separated with each other and electrically connected by a conductive layer pattern formed on the insulating layer. The first conductive pole perforates the insulating layer and is electrically connected to the storage contact pad.
Description
The present invention relates to semiconductor device, particularly dynamic random access memory (DRAM) cell capaciator and the manufacture method thereof of surface area increase.
In little area, obtain enough charge storage capacitance values and be in very lagre scale integrated circuit (VLSIC) (ULSI) the DRAM technology one of challenging design problem of tool.In order to improve the density of DRAM, each charge storing unit memory device must be structurally adapts with more and more littler area.By reduce cell capacitance value that memory cell area causes to reduce be to increasing a serious hindrance of packaging density among the DRAM.Therefore, must solve the problem that the cell capacitance value reduces, in semiconductor storage unit, to reach higher packaging density.
In order to make the capacitance with this capacitor remain on receivable value, the cascade capacitor with three-dimensional structure is adopted in suggestion.Described cascade capacitor comprises, for example, and the capacitor that columniform and simple box type constitutes.Because surfaces externally and internally all can be used as effective capacitor area, cylindrical structural especially is suitable as three-dimensional laminated capacitor thus.Recently, developed some new technologies, by the nucleation and the growth conditions of etching or control polysilicon, the configuration of surface that changes polysilicon storage electrode self increases effective surface area.Can be on storage electrode deposit hemisphere grain (HSG) polysilicon layer, to increase surface area and capacitance.
But the limitation of photoetching process makes in the application of very lagre scale integrated circuit (VLSIC) this cylindrical capacitor of composition very difficult, and the formation of HSG silicon may cause the short circuit between the adjacent storage electrode and the technology of needs complexity.On the other hand, the capacitor of simple case type structures has the shortcoming of the capacitance that can not provide enough.
Therefore, strong demand can provide the technology of the capacitor with very large storage electrode surface area, has high capacity, and process complexity is minimized.
Form the present invention in view of the above problems, the purpose of this invention is to provide a kind of capacitor and technology simple manufacturing method thereof with remarkable increase surface area.For reaching this purpose, the invention provides twin columns type capacitor, one of them polysilicon conductive pole is electrically connected on another polysilicon conductive pole by the conducting layer figure (being cross structure) by polysilicon.One of them conductive pole passes polysilicon graphics and insulating barrier, arrives the contact pad (or diffusion layer) of bottom.After forming one of them conductive pole and before forming another conductive pole, form cross structure with contact pad.By using polysilicon conductive sidewall spacers layer to form the conductive pole that contacts with contact pad (or diffusion layer) with Alignment Method.Briefly, form first opening, form side wall spacers subsequently within it at insulating barrier.Afterwards, use wall, in another insulating barrier of bottom, be formed into second opening of contact pad as mask.Deposit forms first conductive pole as the conductive layer of storage electrode in first and second openings.Therefore, reaching between first opening and second opening can not misalignment between corresponding storage contact hole and the storage electrode.
In order to obtain these and other advantage and according to purpose of the present invention, the method for making twin columns type capacitor comprises: form device isolation layer to limit active and passive region on Semiconductor substrate.Form gate electrode and source/drain region on Semiconductor substrate and in it.On whole Semiconductor substrate, form first oxide layer.In oxide layer, be formed into the storage contact pad in source/drain region by suitable method.On first oxide layer and connection pads, form second oxide layer.On second oxide layer, form bit line.On second oxide layer and bit line, form the 3rd oxide layer and silicon nitride layer subsequently.
Deposit first polysilicon layer on silicon nitride layer is used as the cross structure of two conductive poles.Composition first polysilicon layer forms the first new for purposes of the invention polysilicon graphics then, and described first polysilicon graphics covers contact pad and extends along the side surface direction of contact pad.On silicon nitride layer and polysilicon graphics, form the 4th oxide layer that is called sacrificial oxide layer.The thickness of sacrificial oxide layer is decided by the height of storage electrode, so its thickness capacitance variation as required.Preferred thickness is approximately from 8,000 to 11,000 .Have with respect to the 4th oxide layer and to corrode optionally material layer deposit thereon, as etching mask with post-etching the 4th oxide layer.For example polysilicon layer can be used as this material layer.
First photoresist layer is coated on the material layer of polysilicon and composition forms opening portion with an end alignment of polysilicon graphics.Use first photoresist layer of composition, corrosion material layer, the 4th oxide layer, polysilicon graphics and silicon nitride layer form first opening with basic vertical sidewall that arrives the 3rd oxide layer.Have to be noted that part polysilicon layer figure is buried in the 4th oxide layer and aims at the sidewall of first opening and be positioned on the silicon nitride layer.After removing the photoresist layer of first composition, in first opening, form the polysilicon side wall spacers that thickness is approximately the conduction of 250 .Use polysilicon material layer and polysilicon side wall spacers as etching mask, the corrosion of the 3rd and second oxide layer is arrived contact pad, form second opening thus.Because these side wall spacers, second opening and the first opening autoregistration.The storage electrode material, that is, polysilicon layer be deposited in first and second openings and polysilicon material layer on, then and be planarized to the 4th oxide layer, be formed for the first polysilicon conductive pole of twin columns type storage electrode thus.
Be coated on the 4th oxide layer second photoresist layer and composition, the opening portion that formation is aimed at polysilicon graphics and part silicon nitride layer.Use second photoresist layer of composition, the 4th oxide layer is eroded to polysilicon graphics and silicon nitride layer, thereby form the 3rd opening.Here, the part polysilicon graphics is buried in the 4th oxide layer, and aims at the sidewall of first conductive pole.Described the 3rd opening is electrically connected first conductive pole with the at interval about 100nm of first conductive pole and by the polysilicon graphics that is buried in the remainder in the 4th oxide layer.That is, Yu Xia polysilicon graphics extend into the 3rd opening from the sidewall of first conductive pole.After removing second photoresist of composition, will be as the electric conducting material of storage electrode, that is, polysilicon is deposited in the 3rd opening, is formed for second conductive pole of twin columns type storage electrode.As shown in the above description, the polysilicon graphics of the remainder of second conductive pole bottom being positioned at is connected to first conductive pole.Therefore, be completed into twin columns type capacitor.Thereby the quantity of second conductive pole can increase and further increase surface area.Subsequently, on storage electrode, form dielectric film and upper electrode, thereby form capacitor.
Described capacitor has following advantage: by forming additional storage electrode (second conductive pole) and linking to each other with the primary storage electrode and increase surface area by cross structure (polysilicon graphics).In addition, primary storage electrode (first conductive pole) utilizes the polysilicon side wall spacers to form with Alignment Method, and the processing step of primary storage electrode can be simplified.
By being appreciated that the present invention with reference to the accompanying drawings, for a person skilled in the art, it is obvious that purpose of the present invention will become.
Figure 1A shows in the choice phase of making to Fig. 1 G, according to one embodiment of present invention the profile that intercepts along DRAM cell capaciator bit line direction;
Fig. 2 A shows in the choice phase of making to Fig. 2 G, according to one embodiment of present invention the profile that intercepts along DRAM cell capacitance word-line direction;
Fig. 3 is for forming the top plan view of DRAM cell capaciator behind the polysilicon graphics according to one embodiment of present invention;
Fig. 4 is for forming the top plan view of DRAM cell capacitance behind first opening according to one embodiment of present invention;
Fig. 5 is for forming the top plan view that the sidewall polycrystalline silicon wall forms DRAM cell capaciator behind second opening then according to one embodiment of present invention in first opening;
Fig. 6 is for forming the top plan view of DRAM cell capaciator behind second conductive pole according to one embodiment of present invention; And
Fig. 7 schematically shows the twin columns type storage electrode structure that obtains according to one embodiment of present invention.
With reference now to description of drawings the preferred embodiments of the present invention.The present invention relates to DRAM cell capaciator and manufacture method thereof.Briefly introduce the present formation field oxide of in reality manufacturing DRAM unit, implementing and the technology of field-effect transistor structure for a better understanding of the present invention.Figure 1A shows the choice phase of making to Fig. 1 G, DRAM cell capacitance according to an embodiment of the invention is along the profile of bit line direction intercepting, and Fig. 2 A shows in the choice phase of making to Fig. 2 G, according to one embodiment of present invention the profile of intercepting along the DRAM cell capaciator along word-line direction.In Fig. 2 G, the part identical with Figure 1A function in Fig. 1 G represented with identical reference number, for a better understanding of the present invention, will introduce the preferred embodiments of the present invention with reference to figure 1 and Fig. 2 simultaneously at Fig. 2 A.
With reference now to Figure 1A and Fig. 2 A,, device isolation layer 12, i.e. field oxide is formed on the presumptive area of Semiconductor substrate 10, to determine active area 11 and the passive region on the substrate.By routine techniques for example shallow trench isolation from forming device isolation layer 12.Also can use localized oxidation of silicon.A plurality of gate electrodes 14 with protection insulating barrier (that is, hard mask and side wall spacers) use conventional photoetching and etching process to be formed on the semiconductor chip 10.The lateral margin of multiple source/drain region (not shown) alignment grid electrode 14 is formed in the semiconductor chip 10 with conventional ion implantation technology.First oxide layer 15 is formed on the whole semiconductor substrate 10 that comprises gate electrode 14.The suitable method of a plurality of storage contact pad 16 usefulness is formed in first oxide layer 15 and touches source/drain region.Second oxide layer 18 is formed on first oxide layer 15 and the contact pad 16.A plurality of bit lines 19 are formed on second oxide layer 18.The 3rd oxide layer 20 is formed on second oxide layer 18 and the bit line 19.Have optionally layer 22 of corrosion with respect to the 3rd oxide layer 20, for example silicon nitride layer 22 is formed on the 3rd oxide layer 20.Described silicon nitride layer 22 also can form as the etch stop layer with post-etching the 4th oxide layer.
Next step is very crucial to the present invention.First polysilicon layer 24 is deposited on to be used as on the silicon nitride layer 22 with cross structure 24a and forms electrical connection bridge 24a between two conductive poles 38 and 44 of Fig. 1 G of storage electrode 46.Form first polysilicon layer 24, its thickness is approximately 550 to 1,000 .
With reference to Figure 1B and Fig. 2 B, be coated in first photoresist layer on first polysilicon layer 24 and constitute figure 26.Utilize first photoresist layer 26 of this composition, first polysilicon layer 24 is eroded to silicon nitride layer 22 form new for purposes of the invention a plurality of polysilicon graphics (cross structure).For example form polysilicon graphics 24a cover contact pad 16 and contact pad 16 laterally in extension.Elaborate with reference to figure 3, the figure illustrates the top plan view that forms DRAM cell capacitance behind the polysilicon graphics 24a.Among Fig. 3, polysilicon graphics 24a is formed on the silicon nitride layer 22 by predetermined figure.The polysilicon graphics 24a that forms is overlapping with the part of active area 11, more specifically, aim at contact pad 16 as storage electrode also simultaneously contact pad 16 is arranged on polysilicon graphics 24a an end below.Polysilicon graphics 24a has overlapping (eclipse) shape or rectangle, and the long about 350nm of direction (" a ") of polysilicon graphics 24a, and its short direction (" c ") is 150nm approximately.Along the about 250nm of the distance (" b ") between the adjacent polysilicon graphics of bit line direction, along the about 150nm of the distance (" d ") between the adjacent polysilicon graphics of word-line direction.
With reference now to Fig. 1 C and Fig. 2 C,, remove first photoresist layer 26 of composition after, the 4th oxide layer 28 is also referred to as sacrificial oxide layer, is formed on silicon nitride layer 22 and the polysilicon graphics 24a.The thickness of this sacrificial oxide layer 28 is decided by the height of storage electrode, so its thickness changes according to required capacitance.In the present embodiment, sacrificial oxide layer 28 thickness of formation are about 8,000 to 11,000 .To have with respect to the 4th oxide layer 28 and corrode optionally that material layer 30 is deposited on the 4th oxide layer 28, as the etching mask with post-etching the 4th oxide layer 28.For example polysilicon layer can be used as described material layer, and its thickness is approximately 1,500 to 2,000 .
Be coated in second photoresist layer on the material layer 30 and constitute figure 31, to form the opening portion of aiming at polysilicon graphics 24a one end, this polysilicon graphics 24a one end is aimed at contact pad 16.Utilize this second photoresist layer 31 of composition, corrosion material layer 30, the 4th oxide layer 28, polysilicon graphics 24a and silicon nitride layer 22 are to form a plurality of first openings.For example, first opening 32 of formation has vertical substantially sidewall and arrives the 3rd oxide layer 20.Must be noted that part polysilicon graphics 24a is buried in the 4th oxide layer 28 and aims at a sidewall of first opening 32 and on silicon nitride layer 22.The opening size (" e ") of first opening 32 that forms is approximately 150nm.Fig. 4 is for forming the top plan view of first opening, 32 back DRAM cell capaciators.Aim at the end of the polysilicon graphics 24a on the contact pad 16 with reference to figure 4, the first openings 32.
After removing second photoresist layer 31 of composition, form conductive sidewall spacers layer 34 by polysilicon in first opening 32 shown in Fig. 1 E and Fig. 2 E, its thickness is approximately 250 .Use polysilicon material layer 30 and polysilicon side wall spacers 34 as etching mask, corrode the 3rd and second oxide layer 20 and 18 and arrive contact pad 16, thereby form a plurality of second openings.For example the opening size of second opening 36 of Xing Chenging is approximately 100nm.Because side wall spacers 34, the second openings 36 and 32 autoregistrations of first opening.Here, second opening 36 is corresponding to the contact hole of the storage electrode of the simple single-casing-type capacitor of routine.Therefore, can avoid the storage contact hole that runs in the prior art and the dislocation between the storage electrode.Fig. 5 is the top plan view of the DRAM cell capaciator after forming sidewall polycrystalline silicon wall 34 and form second opening 36 in first opening 32.As can be seen, second opening, 36 to the first openings 32 the are little thickness of sidewall polycrystalline silicon wall 34.
With reference to figure 1F and Fig. 2 F, the electric conducting material that will be used for storage electrode for example polysilicon is deposited on first and second openings 32 and 36 and polysilicon material layer 30.Arrive the 4th oxide layer 28 at polysilicon and polysilicon material layer 30 enterprising parallel planes corrosion, form a plurality of first conductive poles that are used for storage electrode.For example, first conductive pole 38 is formed on the contact pad 16.Planarization-etching can be CMP (chemico-mechanical polishing) or deep etch technology.As mentioned above, polysilicon graphics 24a is electrically connected to a lateral margin of first conductive pole 38 and stretches out silicon nitride layer 22.
Next step forms second conductive pole.Require second conductive pole to be connected with first conductive pole 38 by the polysilicon graphics 24a that stretches out by the side of first conductive pole 38.Reach this purpose, be coated to second photoresist layer on the 4th oxide layer 28 and constitute figure 40, to form the other end of aiming at polysilicon graphics 24a and the opening portion of silicon nitride layer 22.Utilize the 3rd photoresist layer 40 of described composition, corrode the 4th oxide layer 28 and form a plurality of the 3rd openings.For example the 3rd opening 42 is formed on the other end and silicon nitride layer 22 of polysilicon graphics 24a.Therefore, polysilicon graphics 24a and silicon nitride layer 22 have played the effect that stops layer.Under the situation that does not form silicon nitride layer 22, adopt regularly corroding method to corrode the 4th oxide layer 28.In this embodiment, the opening size of the 3rd opening 42 (" h ") be approximately 200nm and with first conductive pole 32 at a distance of about 100nm (" g ").
After removing the 3rd photoresist layer 40 of composition, will be as the electric conducting material of storage electrode, promptly polysilicon is deposited on the 3rd opening and neutralizes on the 4th oxide layer 28.Enterprising parallel planes corrosion arrives the 4th oxide layer 28 and forms a plurality of second conductive poles as storage electrode thus to polysilicon.Second conductive pole 44 that for example forms is electrically connected with first conductive pole 38 by polysilicon graphics 24a.Afterwards, form a plurality of twin columns type storage electrodes 46 thereby remove the 4th oxide layer 28 with the wet corrosion agent, each electrode pair comprises first conductive pole 38, second conductive pole 44 and polysilicon graphics 24a, shown in Fig. 1 G and Fig. 2 G.The quantity of second conductive pole 44 can increase, thereby further increases surface area.
Fig. 6 is the top plan view of the DRAM cell capaciator behind formation second conductive pole 44.With reference to figure 6, twin columns type storage electrode comprises first conductive pole 38, second conductive pole 44 and the polysilicon graphics 24a that is connected the above two with the contact of storage contact pad (not shown).The distance of measuring between the adjacent storage electrode along bit line direction (" i ") is approximately 150nm.The distance of measuring between the adjacent storage electrode along word-line direction is approximately 150nm.
Subsequently, on storage electrode 46, form deielectric-coating (not shown) and top electrode (not shown), thereby form twin columns type capacitor.Therefore, the capacitor of formation has following advantage: increased surface area by forming extra storage electrode (second conductive pole) and linking to each other by cross structure (polysilicon graphics) thereby with the primary storage electrode.In addition, utilize the polysilicon side wall spacers to adopt self aligned mode to form primary storage electrode (first conductive pole), simplified the processing step of primary storage electrode.According to the present invention, owing to increased the surface area of capacitor greatly, can use Ta2O5 to obtain required capacitance, and not need with the ferroelectric media material that also produces for example BST that does not wish stress that requires high temperature to form as deielectric-coating.
Fig. 7 schematically shows according to two adjacent twin columns type storage electrode structures of the present invention.Twin columns type storage electrode structure can be with reference to figure 1G and Fig. 7.Twin columns type storage electrode 46 comprises first conductive pole 38, second conductive pole 44 and polysilicon graphics 24a.First and second conductive poles 38 and 44 are electrically connected mutually by polysilicon graphics 24a.First conductive pole 38 passes the end of polysilicon graphics 24a and arrives the storage contact pad 16 that contacts with source/drain region.Second conductive pole 44 contacts with the other end of polysilicon graphics 24a.In the first conductive pole size below the polysilicon graphics 24a less than the size more than polysilicon graphics 24a.For a person skilled in the art, owing to the size of second conductive pole 44 and polysilicon graphics 24a, can increase the quantity of second conductive pole 44.The upper dimension of first conductive pole 38 is approximately 150nm, and its underpart size is approximately 100nm.The size of second conductive pole 44 is approximately 200nm.Distance between the adjacent storage electrode is approximately 150nm, and the distance between first and second conductive poles is approximately 100nm.
, it will be appreciated by those skilled in the art that not deviating from the spirit and scope of the present invention can much change in form and details now in conjunction with the detailed diagram of the preferred embodiments of the present invention with the present invention has been described.
Claims (14)
1. method of making the DRAM cell capaciator comprises following each step:
Provide have gate electrode and with the Semiconductor substrate of the pair source of the side in alignment of described gate electrode;
Be formed into a pair of storage contact pad on described source/drain region;
On described Semiconductor substrate, form first insulating barrier;
On first insulating barrier, form conducting layer figure described, described conducting layer figure cover in the described storage contact pad one and in described storage contact pad one laterally in extension, described conductive pattern has two opposite ends;
Comprising formation second insulating barrier and first material layer on described first insulating barrier of described conducting layer figure subsequently, described first material layer has selective etching with respect to described second insulating barrier;
Use described first material layer of photoetching corrosion, described second insulating barrier and described conducting layer figure for the first time subsequently, form first opening on described first insulating barrier on one in described storage contact pad, described first opening passes an end of described conductive pattern;
In described first opening, form the conductive sidewall spacers layer;
Utilize described conductive sidewall spacers layer and described first material layer as mask and corrode described first insulating barrier and arrive in the described storage contact pad one, form second opening;
Depositing conductive material in described first and second openings and on described first material layer is planarized to described second insulating barrier, then to form first conductive pole;
Using for the second time, described second insulating barrier of photoetching corrosion forms and isolated the 3rd opening of described first opening up to the other end that exposes described first insulating barrier and described conducting layer figure; And
With filling described the 3rd opening to form second conductive pole with the described first conductive pole identical materials, described second conductive pole is connected to described first conductive pole by described conducting layer figure,
Wherein said first conductive pole, described second conductive pole and described conducting layer figure have constituted the storage electrode of described DRAM cell capaciator.
2. make according to the process of claim 1 wherein that described conducting layer figure is used with the described first conductive pole identical materials.
3. the thickness with described storage electrode is identical at least according to the process of claim 1 wherein the thickness of described second insulating barrier.
4. according to the process of claim 1 wherein that described second insulating barrier comprises oxide layer, described first material layer comprises polysilicon layer.
5. according to the process of claim 1 wherein that the thickness of described conducting layer figure is approximately 550 to 1,000 , the thickness of described second insulating barrier is approximately 8,000 to 11,000 , the thickness of described first material layer is approximately 1,500 to 2,000 .
6. make according to the process of claim 1 wherein that described side wall spacers is used with the described first post identical materials.
7. carry out described complanation according to the process of claim 1 wherein by CMP or deep etch.
8. according to the process of claim 1 wherein that the diameter of described first opening is approximately 150nm, the diameter of described second opening is approximately 100nm, and the diameter of described the 3rd opening is approximately 200nm.
9. according to the process of claim 1 wherein described first conductive pole and described second conductive pole apart from one another by being approximately 100nm, described storage electrode and adjacent storage electrode are approximately 150nm apart.
10. according to the method for claim 1, also be included in before the described step that forms described conducting layer figure, on described first insulating barrier, form second material layer, described second material layer has selective etching with respect to described second insulating barrier, and as the etch stop layer in the described step that forms the 3rd opening.
11. according to the method for claim 10, wherein said second material layer is made by silicon nitride layer.
12. a DRAM cell capaciator comprises:
Be formed on the Semiconductor substrate and be electrically connected to the storage contact pad in the source/drain region on the described Semiconductor substrate;
Comprise the insulating barrier on the described Semiconductor substrate of described storage contact pad; Storage electrode with described DRAM cell capaciator of first and second conductive poles, described first and second conductive poles are spaced-apart and be electrically connected mutually by the conducting layer figure that is formed on the described insulating barrier, and described first conductive pole passes described insulating barrier and is electrically connected with described storage contact pad.
13. according to the DRAM cell capaciator of claim 12, the upper diameter of wherein said first conductive pole is approximately 150nm, the lower diameter in described insulating barrier is approximately 100nm, and the diameter of described second conductive pole is approximately 200nm.
14. according to the DRAM cell capaciator of claim 12, the wherein said first and second conductive pole each intervals are approximately 100nm, described storage electrode and adjacent storage electrode are approximately 150nm at interval.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980014851A KR100270210B1 (en) | 1998-04-25 | 1998-04-25 | DRAM cell capacitor and method of manufacturing the same |
| KR14851/98 | 1998-04-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1236993A true CN1236993A (en) | 1999-12-01 |
Family
ID=19536714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99105863A Pending CN1236993A (en) | 1998-04-25 | 1999-04-23 | DRAM cell capacitor and method for fabricating thereof |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JP2000022099A (en) |
| KR (1) | KR100270210B1 (en) |
| CN (1) | CN1236993A (en) |
| DE (1) | DE19908446A1 (en) |
| FR (1) | FR2778019A1 (en) |
| GB (1) | GB2336716B (en) |
| TW (1) | TW412828B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405589C (en) * | 2003-06-25 | 2008-07-23 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN106206586A (en) * | 2015-04-30 | 2016-12-07 | 联华电子股份有限公司 | Static RAM |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6426249B1 (en) * | 2000-03-16 | 2002-07-30 | International Business Machines Corporation | Buried metal dual damascene plate capacitor |
| KR100502410B1 (en) * | 2002-07-08 | 2005-07-19 | 삼성전자주식회사 | DRAM cells |
| KR100510527B1 (en) | 2003-05-01 | 2005-08-26 | 삼성전자주식회사 | Semiconductor device having storage node and method for manufacturing the same |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438011A (en) * | 1995-03-03 | 1995-08-01 | Micron Technology, Inc. | Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples |
| JP2776331B2 (en) * | 1995-09-29 | 1998-07-16 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US5643819A (en) * | 1995-10-30 | 1997-07-01 | Vanguard International Semiconductor Corporation | Method of fabricating fork-shaped stacked capacitors for DRAM cells |
| US5721154A (en) * | 1996-06-18 | 1998-02-24 | Vanguard International Semiconductor | Method for fabricating a four fin capacitor structure |
| US5744833A (en) * | 1996-08-16 | 1998-04-28 | United Microelectronics Corporation | Semiconductor memory device having tree-type capacitor |
| GB2322964B (en) * | 1997-03-07 | 2001-10-17 | United Microelectronics Corp | Polysilicon CMP process for high-density DRAM cell structures |
-
1998
- 1998-04-25 KR KR1019980014851A patent/KR100270210B1/en not_active IP Right Cessation
-
1999
- 1999-01-27 TW TW088101191A patent/TW412828B/en active
- 1999-02-26 DE DE19908446A patent/DE19908446A1/en not_active Withdrawn
- 1999-03-05 GB GB9905192A patent/GB2336716B/en not_active Expired - Fee Related
- 1999-03-31 FR FR9904014A patent/FR2778019A1/en not_active Withdrawn
- 1999-04-23 JP JP11117080A patent/JP2000022099A/en active Pending
- 1999-04-23 CN CN99105863A patent/CN1236993A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100405589C (en) * | 2003-06-25 | 2008-07-23 | 三星电子株式会社 | Semiconductor device and method of manufacturing the same |
| CN106206586A (en) * | 2015-04-30 | 2016-12-07 | 联华电子股份有限公司 | Static RAM |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2336716B (en) | 2000-11-15 |
| DE19908446A1 (en) | 1999-11-04 |
| FR2778019A1 (en) | 1999-10-29 |
| GB9905192D0 (en) | 1999-04-28 |
| TW412828B (en) | 2000-11-21 |
| GB2336716A (en) | 1999-10-27 |
| KR19990081113A (en) | 1999-11-15 |
| JP2000022099A (en) | 2000-01-21 |
| KR100270210B1 (en) | 2000-10-16 |
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