JP2000022099A - Dram cell capacitor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DRAM cell capacitor and a manufacturing method thereof, wherein a storage electrode forming process is simplified, and a storage electrode is enlarged in surface area. SOLUTION: A first step where a storage electrode pad 16 is formed, a second step where a first insulating layer including the storage electrode pad 16 is formed, a third step where a poly-pattern 24a is formed, a fourth step where a first material layer, a second insulating layer, and the poly-pattern 24a are successively etched to form a first opening 32, a fifth step where a poly-spacer is formed on each side wall of the first opening, a sixth step where a second opening 36 is formed by etching the first insulating layer, a seventh step where the first and second opening are filled up with a polysilicon film for the formation of a first polysilicon rod, and an eighth step where a third opening 42 is formed are provided, a second polysilicon rod is formed, and a storage electrode composed of the first polysilicon rod, the second polysilicon rod and a polysilicon pattern is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic random access memory (DRAM) cell capacitor.
r) and a method of manufacturing the same, and more particularly, a DR that simplifies the process of forming a storage electrode and increases the surface area of the storage electrode.
The present invention relates to an AM cell capacitor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, capacitors up to 1G DRAM are used.
Ta as a dielectric layer_TwoO _FiveWas used,
4G DRAM with 0.30 μm pitch or less
In manufacturing, Ta_TwoO_FiveAnd the capacitor dielectric film
And use it to achieve the desired capacitance.
Is difficult to form. This
Of Ba (Sr, Ti) O [BST]
Applicability has been tested, but BST is still being applied.
Is only in the development stage.

On the other hand, as a storage electrode structure for increasing the capacitance, a cylinder type (cylinder type) is used.
e) and the simple box type are used. The patterning of the cylinder is difficult due to the progressively smaller pitch. Further, the simple box shape has a problem in that not only a patterning problem but also a sufficient storage electrode surface area cannot be obtained.

[0004]

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned various problems. It is an object of the present invention to provide a DRAM cell capacitor and a method of manufacturing the same, which can facilitate a patterning process of a storage electrode. There is a purpose. It is another object of the present invention to provide a DRAM cell capacitor capable of increasing the surface area of a storage electrode having a simple box shape and thereby increasing the capacitance, and a method of manufacturing the same.

[0005]

According to the present invention, there is provided a method of manufacturing a DRAM cell capacitor, comprising the steps of: forming a source / drain region on a semiconductor substrate having a source / drain region and a gate electrode; Forming a storage electrode pad so as to be electrically connected to the first electrode; and forming a first electrode on the semiconductor substrate including the storage electrode pad.
Forming an insulating layer, forming a conductive layer pattern on the first insulating layer so as to overlap with one of the storage electrode pads, and to extend in one direction of the one storage electrode pad; Forming a second insulating layer and a first material layer having an etching selectivity with the second insulating layer on the first insulating layer including the layer pattern, and forming an upper surface of the first insulating layer on the storage electrode pad. Forming at least one first opening by sequentially etching the first material layer, the second insulating layer, and the conductive layer pattern until exposed, and forming conductive layer spacers on both side walls of the first opening; And etching the first insulating layer using the conductive layer spacer and the first material layer as an etching mask until the upper surface of the storage electrode pad is exposed. Forming a second opening in one Kutomo, second opening and the first opening is filled with a conductive layer at least one first Shirubedenbo (Condu
forming a conductive pole and a first conductive rod by flattening and etching the conductive layer and the first material layer until the upper surface of the second insulating layer is exposed; and isolating the first conductive rod from each other. Etching a second insulating layer in a region having a distance from one side, until a portion of the conductive layer pattern and a surface of the first insulating layer are exposed to form a third opening; Filling the opening with the same material as the first conductive rod to form a second conductive rod electrically connected to the first conductive rod by a conductive layer pattern. This is a method of forming a storage electrode using a conductive rod and a conductive layer pattern.

In a preferred embodiment of the method, D
The method of manufacturing a RAM cell capacitor may further include forming a second material layer having an etching selectivity with respect to the second insulating layer on the first insulating layer before forming the conductive layer pattern. Serves as an etching stop layer at the time of forming the third opening.

According to the present invention, a DRAM cell capacitor is formed on a semiconductor substrate having a source / drain region and a gate electrode so as to be electrically connected to the source / drain region. A storage electrode pad, an insulating layer formed on the semiconductor substrate including the storage electrode pad, and formed in a rod shape on the insulating layer, but electrically connected to the storage electrode pad through the insulating layer. A first conductive rod formed on the first conductive rod, at least one second conductive rod formed on the insulating layer on at least one side of the first conductive rod, and a first conductive rod and a second conductive rod. And at least one storage electrode having at least one conductive layer pattern formed on the insulating layer so as to be connected to each other.

(Operation) Referring to FIGS. 7 and 14, a novel DRAM cell capacitor according to an embodiment of the present invention and a method of manufacturing the same are overlapped with one of storage electrode pads on a first insulating layer. A poly pattern is formed to extend to one side of one storage electrode pad. The opening for forming the storage electrode is filled with a polysilicon film to form at least two rod-shaped poly with a thickness of the storage electrode which is electrically connected to each poly pattern.

According to the semiconductor device and the method of manufacturing the same, the self-alignment of the storage electrode contact hole and the storage electrode can prevent misalignment of the storage electrode contact hole and the storage electrode, and the storage electrode forming step can be prevented. Can be simplified. In addition, the surface area of the storage electrode can be increased by electrically connecting the rod-shaped poly using the poly pattern formed before forming the storage electrode.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. 8 to 14, the same reference numerals are given to components having the same functions as the components of the DRAM cell capacitor shown in FIGS. 1 to 7.

FIGS. 1 to 7 are flow charts sequentially showing steps of a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, and are cross-sectional views taken along an extending direction of a bit line. . 8 to FIG.
FIGS. 6A to 6C are diagrams showing a process order of a method for manufacturing a DRAM cell capacitor according to an embodiment of the present invention, and show word lines (w
FIG. 3 is a cross-sectional view cut in the extension direction of the ord line).

Referring to FIGS. 1 and 8, a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention will first be described.
An element isolation film 12 is formed on a semiconductor substrate 10 to define an active region 11 and an inactive region. Element isolation film 12
Is formed, for example, by an STI (Shallow Trench Isolation) method. Source / drain region on semiconductor substrate 10
A gate electrode 14 (not shown), that is, a word line is formed. Oxide film 15 is formed on semiconductor substrate 10 including gate electrode 14. Storage electrode pads 16 are formed through oxide film 15 to be electrically connected to the source / drain regions.

Another oxide film 18 is formed on the entire surface of the semiconductor substrate 10 including the pad 16. Oxide film 1 between pads 16
A bit line 19 is formed on 8. Bit line 1
9, another oxide film 20 and a material having an etch selectivity with the oxide film 20, for example, a silicon nitride film (SiN) 22 are sequentially formed on the oxide film 18. The silicon nitride film 22 is not necessarily required to be used as an etch stopping layer in a subsequent oxide film etching process. The same material as the storage electrode material, for example, a polysilicon layer 24 is formed on the silicon nitride film 22 so as to have a thickness in the range of 550.degree.

2 and 9, the polysilicon layer 2
4 overlaps with one storage electrode pad 16 (o
Then, a photo resist pattern 26 is formed so as to block an area extending to one side of the storage electrode pad 16. If the polysilicon layer 24 is etched using the photoresist pattern 26 as a mask until the upper surface of the silicon nitride film 22 is exposed, a new poly pattern 24a according to the present invention is formed.

FIG. 15 shows a DRA according to an embodiment of the present invention.
FIG. 9 is a plan view after forming a poly pattern 24a of the M cell capacitor. Referring to FIG. 15, the poly pattern 24a is
Each is formed so as to overlap a part of the active region 11. For example, the shape is formed in an elliptical or rectangular shape so that the length in the long direction (reference numeral a) is about 350 nm, and the length in the short direction (reference numeral c) is about 15 nm.
It is formed to have a thickness of 0 nm.

In the direction along the bit line (not shown), that is, in the long direction of the poly pattern 24a, the distance (reference numeral b) between adjacent poly patterns 24a is about 250 nm. Then, in a direction along a word line (not shown), that is, in a short length direction of the poly pattern 24a, a distance (reference numeral d) between adjacent poly patterns 24a is formed to be about 150 nm.

3 and 10, after the photoresist pattern 26 is removed, at least the thickness of the storage electrode, that is, the thickness within the range of 8000.degree. To 11000.degree. A thick oxide film 28 is formed. On the thick oxide film 28, a material layer having an etching selectivity with respect to the oxide film, for example, a polysilicon layer 30 is formed in a thickness range of 1500 to 2000 degrees. The polysilicon layer 30 is used as an etching mask (e) in the subsequent step of etching the thick oxide film 28.
tch mask).

A photoresist pattern 31 is formed on the polymask layer 30 by defining a storage electrode formation region. The photoresist pattern 31 is formed such that the storage electrode formation region is exposed. That is, the first reverse pattern (reverse p
attern) 31 is formed. Photoresist pattern 3
Using the mask 1 as a mask, the poly mask layer 30, the thick oxide film 28, the poly pattern 24a, and the silicon nitride film 22 are sequentially etched until the upper surface of the oxide film 20 is exposed. Then, as in FIGS. 4 and 11, at least one first opening 32 is formed. The first opening 32 is formed to have a diameter (reference numeral e) of about 150 nm.

FIG. 16 shows a DRA according to an embodiment of the present invention.
FIG. 5 is a plan view after forming a first opening 32 of the M cell capacitor. Referring to FIG. 16, the first opening 32
Are formed so as to overlap with one side region of the poly pattern 24a.

5 and 12, after the photoresist pattern 31 is removed, the same material as the storage electrode forming material, for example,
A spacer 34 is formed of polysilicon. The poly spacers 34 are each formed to have a thickness of about 250 °. Using the poly mask layer 30 and the poly spacer 34 as a mask, the oxide films 20 and 18 are sequentially etched until the upper surface of the storage electrode pad 16 is exposed to form a second opening 36. The second opening 36 is formed to have a diameter (reference numeral f) of about 100 nm.

At this time, the second opening 36 is a contact hole (conta) of the existing simple box type storage electrode.
ct hole). FIG. 17 is a plan view of the DRAM cell capacitor according to the embodiment of the present invention after the poly spacer 34 is formed. In FIG. 17, a second opening 36 having a size smaller than that of the first opening 32 by the size of the polyspacer 34 is formed in the first opening 32.

Referring to FIGS. 6 and 13, when the second opening 36 and the first opening 32 are filled with a conductive material for a storage electrode, for example, a polysilicon film, a first poly rod 38 is formed. That is, the second opening 3
6, the first poly rod 38 is self-aligned. Thick oxide film 28
The polysilicon film and the poly mask layer 30 are planarized etch until the upper surface of the substrate is exposed.
Is done. Then, the first poly rods 38 are isolated from each other.
n) is done. The planarization etching process is performed by CMP (Chemical Me
This is performed by mechanical polishing or etch back.

A photoresist pattern 40 is formed on thick oxide film 28 such that a portion of thick oxide film 28 on one side of first poly rod 38 is exposed. That is, the second reverse pattern 40 for forming the storage electrode is formed. Using the photoresist pattern 40 as a mask, the oxide film 28 is etched until the surfaces of the poly pattern 24a and the silicon nitride film 22 are exposed. Then, a third opening 42 is formed. At this time, the poly pattern 24a and the silicon nitride film 2
2 is used as an etch stop layer. On the other hand, when the silicon nitride film 22 is not used, the etching is stopped by a time etch.

The third opening 42 is formed to have a diameter (reference numeral h) of about 200 nm and to have a distance (reference number g) of about 100 nm from the first opening 32.

Finally, after the photoresist pattern 40 is removed, the third opening 42 is filled with the same conductive material as the first poly rod 38, that is, a polysilicon film to form the second poly rod 44. When the polysilicon film is planarized and etched until the upper surface of the thick oxide film 28 is exposed, the second poly rods 44 are isolated from each other. The planarization etching process is the same as the isolation process of the first poly rod 38 by CMP.
Or, it is performed by etch back or the like.

When the thick oxide film 28 is removed by wet etching or the like using the silicon nitride film 22 as an etching stop layer, as shown in FIGS.
The second poly rod 44, and the first poly rod 38 and the second poly rod 4
A simple box-shaped storage electrode 46 having an increased surface area due to the poly pattern 24a electrically connecting the storage electrodes 4 is formed.

By adding a step of further increasing the number of the poly patterns 24a and the second poly rods 44, the surface area of the storage electrode 46 can be further increased. FIG. 18 is a plan view of the DRAM cell capacitor according to the embodiment of the present invention after the second poly rod 44 is formed.

Referring to FIG. 18, the first opening 3
A second opening 42 is formed on one side of the second 2 so as to overlap with a part of the poly pattern 24a. At this time, the third opening 42 on the other poly pattern sharing the same active region 11 as the first opening 32 on one poly pattern is formed to have a distance (reference numeral i) of about 150 nm. One storage electrode and the other storage electrode are also formed to have a distance of about 150 nm in the short length direction of the poly pattern. That is, the adjacent storage electrode 46
The distance between them is about 150 nm.

As a subsequent step, a capacitor dielectric film (not shown) and a capacitor upper electrode are formed on the storage electrode 46.
(Not shown) are formed in order. At this time, since the surface area of the storage electrode 46 is sufficiently increased by the method of manufacturing a capacitor according to the present invention, a desired cell capacitance can be sufficiently obtained even with a capacitor dielectric film such as Ta ₂ O ₅ . FIG. 19 is a three-dimensional view schematically showing the structure of a DRAM cell capacitor according to an embodiment of the present invention. The structure of the DRAM cell capacitor will be described with reference to FIGS.

Referring to FIGS. 7 and 19, D according to the present invention is shown.
The RAM cell capacitor has a storage electrode pad 16 formed on a semiconductor substrate 10 having a source / drain region (not shown) and a gate electrode 14 so as to be electrically connected to the source / drain region. An oxide film 18 on the semiconductor substrate 10 including the storage electrode pads 16;
20 and a silicon nitride film 22 are sequentially formed. At least one storage electrode 46 is formed on the silicon nitride film 22.

As shown in FIG. 19, the storage electrode 46 has a poly pattern 24a and the poly pattern 24.
a has a plurality of rod-shaped poly rods 38 and 44 formed on the rod. One of the poly rods 38 and 44 is poly pattern 2
4a.

In other words, referring to FIG. 5, the storage electrode 46 includes the silicon nitride film 22 and the oxide films 18 and 2.
And a first poly rod 38 formed to penetrate through the storage electrode pad 16 and to be electrically connected to the storage electrode pad 16.
In addition, a second poly rod 44 formed on the silicon nitride film 22 on at least one side of the first poly rod 38 is included. In addition, at least one poly pattern formed on the silicon nitride film 22 to electrically connect the first poly rod 38 and the second poly rod 44 is included.

The upper diameter of the first poly rod 38 is about 150 n.
m, and the lower diameter of the first poly rod 38 is about 100 n
m. The diameter of the second poly rod 44 is about 200
nm. The distance between the first poly rod 38 and the second poly rod 44 of one storage electrode 46 is about 100 nm, and the distance between adjacent storage electrodes 46 is about 150 n.
m.

[0034]

According to the present invention, by self-aligning the storage electrode contact hole and the storage electrode,
This has the effect of preventing misalignment of the storage electrode contact hole and the storage electrode and simplifying the storage electrode formation process.

Also, by electrically connecting the rod-shaped poly using the poly pattern formed before forming the storage electrode, the surface area of the storage electrode can be increased, thereby increasing the capacitance. be able to.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which are cut in an extending direction of a bit line.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a bit line.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 9 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 10 is a sectional view of a DRAM cell capacitor according to an embodiment of the present invention, taken in a process direction of a method of manufacturing the DRAM cell capacitor, the sectional view being taken in a word line extending direction;

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 13 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 14 is a cross-sectional view illustrating a method of manufacturing a DRAM cell capacitor according to an embodiment of the present invention, which is cut in an extending direction of a word line.

FIG. 15 is a plan view after forming a poly pattern of the DRAM cell capacitor according to the embodiment of the present invention.

FIG. 16 is a plan view of a DRAM cell capacitor according to an embodiment of the present invention after a first opening is formed.

FIG. 17 is a plan view of a DRAM cell capacitor according to an embodiment of the present invention after forming a poly spacer.

FIG. 18 is a plan view of a DRAM cell capacitor according to an embodiment of the present invention after a second poly rod is formed.

FIG. 19 is a perspective view schematically showing a structure of a DRAM cell capacitor according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12 Element isolation film 14 Gate electrode 15, 18, 20, 28 Oxide film 16 Storage electrode pad 19 Bit line 22 Silicon nitride film 24a Poly pattern 26, 31, 40 Photoresist pattern 30 Poly mask layer 32 First opening 34 Poly spacer 36 2nd opening 38 1st poly rod 42 3rd opening 44 2nd poly rod 46 Storage electrode

Claims (14)

[Claims] Forming a storage electrode pad on a semiconductor substrate having a source / drain region and a gate electrode so as to be electrically connected to the source / drain region; and a semiconductor substrate including the storage electrode pad. First on
Forming an insulating layer; and forming a conductive layer pattern on the first insulating layer so as to overlap with one of the storage electrode pads and to extend in one side direction of the one storage electrode pad. Forming a second insulating layer and a first material layer having an etching selectivity with the second insulating layer on the first insulating layer including the conductive layer pattern; and forming a first material layer on the storage electrode pad. Etching at least one first opening by sequentially etching the first material layer, the second insulating layer, and the conductive layer pattern until an upper surface of the insulating layer is exposed; and both side walls of the first opening. Forming a conductive layer spacer on the storage electrode pad, exposing an upper surface of the storage electrode pad using the conductive layer spacer and the first material layer as an etching mask. Etching the first insulating layer to form at least one second opening until filling, and filling the second opening and the first opening with a conductive layer to form at least one first conductive rod. Flattening and etching the conductive layer and the first material layer until the upper surface of the second insulating layer is exposed to isolate the first conductive rods from each other; Etching the second insulating layer in a region having a certain distance, forming a third opening by etching until a part of the conductive layer pattern and the surface of the first insulating layer are exposed; Filling the opening with the same material as the first conductive rod to form a second conductive rod electrically connected to the first conductive rod by the conductive layer pattern; Denbo, DRA second Shirubedenbo and conductive layer pattern, the that and forming a storage electrode
A method for manufacturing an M cell capacitor. 2. The method as claimed in claim 1, wherein the conductive layer pattern is formed of the same material as the first conductive rod. 3. The device according to claim 1, wherein the second insulating layer has a thickness of at least a storage electrode.
3. The method for manufacturing a DRAM cell capacitor according to 1. 4. The method as claimed in claim 1, wherein the second insulating layer is formed of an oxide film, and the first material layer is formed of a polysilicon film. 5. The conductive layer pattern is formed in a thickness range of 550 ° to 1000 °, and the second insulating layer is
The DRA of claim 1, wherein the first material layer is formed in a thickness range of 8000 to 11000 mm, and the first material layer is formed in a thickness range of 1500 to 2000 mm.
A method for manufacturing an M cell capacitor. 6. The method as claimed in claim 1, wherein the conductive layer spacer is formed of the same conductive material as the first conductive rod. 7. The method according to claim 7, wherein the planarizing etching step is performed by CMP.
2. The method of claim 1, wherein the method is performed by one of etch-back and etch-back. 8. The first opening is about 150 n.
The second opening may be formed to have a diameter of about 100 nm, and the third opening may be formed to have a diameter of about 200 nm. DR according to item 1
A method for manufacturing an AM cell capacitor. 9. The method of claim 1, wherein a distance between the first conductive rod and the second conductive rod is about 100 nm, and a distance between adjacent storage electrodes is about 150 nm. Of manufacturing a DRAM cell capacitor. 10. The method of manufacturing a DRAM cell capacitor, further comprising, before forming the conductive layer pattern, forming a second material layer having an etching selectivity with the second insulating layer on the first insulating layer. 2. The method according to claim 1, wherein the second material layer includes an etching stop layer at the time of forming the third opening. 11. The DR according to claim 10, wherein the second material layer is formed of a silicon nitride film.
A method for manufacturing an AM cell capacitor. 12. A storage electrode pad formed on a semiconductor substrate having a source / drain region and a gate electrode so as to be electrically connected to the source / drain region, and on a semiconductor substrate including the storage electrode pad. An insulating layer formed on the insulating layer, and a first conductive rod formed in a rod shape on the insulating layer, but formed so as to be electrically connected to the storage electrode pad through the insulating layer. At least one second conductive rod formed on the insulating layer on at least one side of the first conductive rod, and on the insulating layer so as to electrically connect the first conductive rod and the second conductive rod. And at least one storage electrode having at least one conductive layer pattern formed thereon. 13. The first conductive rod has an upper diameter of about 1
50 nm, and the lower diameter of the first conductive rod is about 100 n.
13. The DRAM cell capacitor according to claim 12, wherein the second conductive rod has a diameter of about 200 nm. 14. The storage electrode of claim 1, wherein a distance between the first conductive rod and the second conductive rod is about 100 nm, and a distance between adjacent storage electrodes is about 150 nm. 13. The DRAM cell capacitor according to claim 12.