TW412828B - DRAM cell capacitor and method for fabricating thereof - Google Patents

Abstract

A double pole type stacked capacitor with significantly increased surface area and a method for fabricating thereof with process simplicity are disclosed. The double pole type capacitor is constituted by a first pole and a second pole which are spaced apart from each other but electrically connected to each other through a conductive pattern. The method for fabricating double pole type capacitor includes the step of forming a conductive layer pattern over a first insulating layer having a storage contact pad therein, sequentially forming a second insulating layer and a first material layer over the first insulating layer including the conductive layer pattern, sequentially etching the first material layer, the second insulating layer, and the conductive layer pattern using a first photolighography, and thereby forming a first opening to the first insulating layer over the one of the storage contact pad, forming a conductive sidewall spacers in the first opening, using the sidewall spacers and the first material layer as a mask and etching the first insulating layer down to the one of the storagecontact pad, and thereby forming a second opening, depositing a conductive material in the first and second openings and over the first material layer and planarizing down to the second insulating layer to form a first conductive pole, etching the second insulating layer until the first insulating layer and the other end of the conductive layer pattern is exposed using a second photolithography, and thereby forming a third opening spaced apart from the first opening, and filling the third opening with the same material as the first conductive pole to form a second conductive pole.

Description

412828 at ^^^^ pif.doc / 0〇8 gy '' ~ _ ___. ________--- " ** ---------- --- " " V. Description of the Invention (I) This The invention relates to a semiconductor device, and more particularly to a method for increasing the surface area of a cell capacitor of a dynamic random access memory and a method for manufacturing the same. In ULSI's technology, it can be used on a small substrate area || A sufficient charge storage capacitor is--Xian Shenxin and ft. As the high-density dynamic random access memory is gradually expanded, the charge storage element of each memory cell must be suitable for a small area. However, the decrease in cell capacitance 値 caused by reducing the memory cell area will affect the increase in the packing density of dynamic random access memory. Therefore, the problem of reduction in cell body capacitance must be solved in order to achieve the purpose of high packaging density of semiconductor devices. In order to keep the capacitance of the capacitor to an acceptable level, a stacked capacitor having a three-dimensional structure was proposed. The stacked capacitors include cylindrical and simple box-shaped capacitors. When the outer surface and the inner surface can be used as an effective capacitance area, a capacitor with a cylindrical structure is more suitable for a stacked capacitor with a three-dimensional structure. Recently, the surface shape of the polycrystalline silicon storage electrode itself is adjusted by engraving or controlling the conditions of nucleation and grain growth of the polycrystalline sand to increase the effective area and capacitance of the capacitor. A new technology of hafnium, a hemispherical-grain polysilicon / 'tlSG layer deposited over a storage electrode, has been developed. However, the limitations of the lithography process, such as the capacitors that cause the cylindrical structure, are used in ULSI applications || Miles, and the two called gingiva are easy to make _ || ji 〇 In addition, simple rectangular capacitors have the disadvantage that they cannot provide sufficient capacitance. 5 Clothes ------ Order ------ Ice (I read the precautions on the back first, and then write this page) This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 2 ~ 7 mm) ) 412828 4384pif.doc / 008 V. Description of the Invention (>) Therefore, a process that can provide a large surface area of high capacitance of the capacitor storage electrode while reducing the complexity of the process is urgently needed. In view of this, it is an object of the present invention to provide the 遂 穆 遂 遂 遂 遂 遂 & ._ 墓 焉 屋 逸 逍 基. In order to achieve this object, the present invention provides a two-pole type capacitor, in which a lion is electrically connected to another polycrystalline silicon conductive electrode by defining a spirit (like a bridge for connection). One of the polycrystalline silicon conductive electrodes penetrates through the polycrystalline silicon pattern layer and the insulating layer to the contact pad (or diffusion layer) located below. This connected bridge was formed after the polycrystalline silicon conductive electrode connected to the contact pad was formed, but was formed before another polycrystalline silicon conductive electrode was formed. The polycrystalline silicon conductive electrode connected to the contact pad (or the diffusion layer) is formed by a self-aligned method using a conductive side wall spacer of the polycrystalline silicon material. In short, a first opening is formed in an insulating layer, and then a sidewall gap is formed in the first opening. After that, using the side wall gap as a cover, a second opening of the contact pad is formed in another insulating layer below the first opening. The conductive layer serving as a storage electrode is inserted into the first opening and the second opening to form a first conductive electrode. Therefore, between the first opening and the second opening, there is no misalignment between the storage contact hole and the storage electrode. To achieve the above and other objectives, the present invention proposes a method for manufacturing a two-pole type capacitor. The two-pole type capacitors are included in # 导. 厅 (Zhenjishe: forming a filling section isolation layer), which is used to define the main .. area and the non .. area. Gao Wei JI Cao and-: il_ / Ji Ji District speculated that Gu Cheng was on the bottom of Liang's tomb and in the semiconductor substrate. Ammonia is fully covered on the semiconductor substrate 6 — 1 n i. Ordering n envy (" Read the precautions on the back before filling this page} This paper size is applicable to China National Standard (CNS) A4 (210 X 297 (Mm) ^ In the middle of the clip " ί (, Α'ΛΤ, eliminate the oblique "? wood 412828 4384pif, doc / 008 V. Description of the invention (ingenious) square. A storage contact pad by appropriate The method is formed in the first oxide layer and connected to the source / drain region. A second oxide layer is formed over the first oxide layer and the contact pad. A bit line is formed on the second oxide layer. A third oxide A layer and a silicon nitride layer are sequentially formed over the second oxide layer and the bit line. A first polycrystalline silicon layer is deposited over the silicon nitride layer and serves as a bridge connecting the two conductive electrodes. After the crystalline silicon layer is defined, a first polycrystalline silicon pattern layer is formed, and the position corresponding to the first polycrystalline silicon pattern layer overlaps the contact pad and extends to the side of the contact pad. A fourth oxide layer is a so-called sacrificial An oxide layer is formed over the nitrided sand layer and the first polycrystalline cut pattern layer. The degree depends on the height of the storage electrode, so the thickness of the sacrificial oxide layer will change with the preset capacitance 値, and in this embodiment, the preferred thickness of the sacrificial oxide layer is about 100 angstroms. A material layer such as It is deposited on the fourth oxide layer and has an etch selectivity different from that of the fourth oxide layer, and is used as an etching mask for one of the fourth oxide layers to be subsequently etched. — A cloud: ϊ: 直: Recommended_Shock on the explosion win || .Hangyihuang. This first photoresist layer is defined to form an opening aligned with one end of the polycrystalline silicon pattern layer. The first photoresist layer is defined as Engraving the mask, etching the polycrystalline silicon material layer, the fourth oxide layer, the polycrystalline silicon pattern layer and the silicon nitride layer to form a first opening exposing the third oxide layer, the first opening having almost vertical sidewalls It must be noted that a part of the polycrystalline silicon pattern layer is still located above the silicon nitride layer and buried in the fourth oxide layer, and is aligned with one side of the first opening. Remove the defined first layer After the photoresist layer, a conductive spacer made of polycrystalline silicon is formed on the first The thickness of the side wall of the opening is about 250 Angstroms. Lee 7 This paper is a standard of the Chinese state of Shizhou (CNS > Α4 size (210X297 mm) -------- installation ------ order-- ---- Ga (诮 Please read the notes on the back before filling in this 萸) A7 B7 4384pif.doc V. Description of the invention (U) Use the polycrystalline silicon material layer and the polycrystalline silicon spacer as the etching mask, and etch the 3_ And the second oxide layer until the contact pad is exposed to form a second opening. The second opening is automatically aligned with the first opening due to the formation of the gap wall. A storage electrode is, for example, a conductive material of a polycrystalline silicon layer Into the first and second openings, and into the second opening, and the intrusion height exceeds the polycrystalline silicon material layer. Then, the fourth oxide layer is exposed until the fourth oxide layer is exposed to form a first conductive pole of the bipolar type storage electrode. A second photoresist layer is coated on the fourth oxide layer. This second photoresist layer is defined to form an opening portion aligned with the polycrystalline silicon pattern layer and a portion of the silicon nitride layer. Using the defined second photoresist layer as an etching mask, the fourth oxide layer is etched until the polycrystalline sand pattern layer and the nitrided sand layer are exposed to form a third opening. In this article, a part of the polycrystalline silicon pattern layer is still buried in the fourth oxide layer and is in contact with the sidewall of the first conductive electrode. The distance between the third opening and the first conductive electrode is about 100 nm, and the conductive material that is subsequently inserted will be electrically coupled to the first conductive electrode through the remaining polycrystalline silicon pattern layer buried in the fourth oxide layer. Pick up. That is, the remaining polycrystalline silicon pattern layer protruding from one side of the first conductive electrode projects into the third opening. After the defined second photoresist layer is removed, a conductive material for forming a storage electrode is formed in the second opening to form a second conductive electrode for a storage electrode of a bipolar type. It can be known from the above that the second conductive electrode can be electrically connected to the first conductive electrode through the polycrystalline silicon pattern layer remaining below. Therefore, a bipolar type storage electrode is formed. The number of the second conductive electrodes may be increased in order to further increase the surface area of the storage electrode. After that, a dielectric layer and a top electrode are sequentially formed over the storage electrode to form a capacitor. {诮 Read the 意 things on the back first and then moth the page j " " Γ 浐 浐 部 十 央 ^^^^^ 消 贽 合: ^^ 印 * 11 ^ This paper is suitable for Chinese interpreter standards ((: Yang) eight 4 rules ^ (210 > < 297 mm) 412Q28 4 3 8 4 pif. Doc / 008 V. Description of the invention (() A two-pole type capacitor can be added with an additional storage electrode (second Conductive electrode), and a connecting bridge (polycrystalline silicon pattern layer) for connecting the first and second conductive electrodes, which makes this capacitor have the advantage of increasing the surface area. In addition, the main storage electrode (the first conductive electrode) It is formed by the self-alignment of the polycrystalline silicon spacer, so the main storage electrode process can be simplified. Yunli 5 Fan's above-mentioned purpose, especially exciting, ancestral advantages are even more obvious; J, Qi: Ji Wen Saifeng's style: .work-say the abdomen is as follows: Figures 1A to 1G illustrate a preferred embodiment of the invention, a dynamic random access memory cell capacitor bit according to a preferred embodiment of the present invention A schematic sectional view in the direction of a line; FIGS. 2A to 2G show a preferred embodiment according to the present invention. In the embodiment, a cross-section along the direction of a word line of a capacitor of a dynamic random access memory cell shows an 'intention; FIG. 3 illustrates a preferred embodiment of the present invention, after forming a poly ... silicon pattern layer , A top plan view of a dynamic random access memory cell capacitor; FIG. 4 shows a top plan view of a dynamic random access memory cell capacitor after forming a first opening according to a preferred embodiment of the present invention; FIG. 5 is a top plan view of a dynamic random access memory cell capacitor after forming a polycrystalline silicon spacer on a side wall of a first opening and before forming a second opening according to a preferred embodiment of the present invention; FIG. 9 The size of this paper is suitable for China National Standards (CNsTA4g (210X297 Gong Chu Υ T-Silver (诮 Please read the precautions on the back before filling in this page)

41282S A7 4384pif.doc / 008 β7 ___ 5. Description of the Invention (t) Figure 6 shows the top view of the 'Dynamic Random Access Memory Cell Capacitor' after forming a first conductive electrode according to a preferred embodiment of the present invention. A plan view; and FIG. 7 is a schematic diagram of a one-pole type storage electrode structure according to a preferred embodiment of the present invention. Among them, the element structures represented by the symbols shown in the figures are as follows: 10: semiconductor substrate 11: active area 12: element isolation structure 14: gate electrode 15, 18, 20, 28: oxide layer 16: storage contact pad 19: bit Line 22: nitrided sand layer 24, 24a: polycrystalline silicon layer 26, 3 1, 40: photoresist layer 30: material layer 32, 36, 42: opening 34: conductive sidewall spacer 38, 44: conductive electrode 46: storage Electrode embodiment The preferred embodiment of the present invention will be described in detail in conjunction with the attached drawings. National paper standard (CNS) A4 specification (210X297 cm) in this paper standard. -------- A 丨, (诮 Please read the notes on the back before filling this page) Order 412828 A7

^ 3g4〇if.doc / 008 A _ _. 1 .. _ B7 5 'Description of the Invention (q) The present invention relates to a dynamic random access memory cell capacitor and a method for manufacturing the same. In order to better understand the present invention, in the simple political process of the dragon, the dynamics, dynamics, and benefits are inevitable, and the violent gas path will be affected by the explosion of waves and the effects of field effects. Figures 1A to ig show schematic cross-sections along the direction of a dynamic random access memory cell capacitor & element according to a preferred embodiment of the present invention. Figures 2A to 2G are schematic cross-sectional views of a dynamic random access memory cell capacitor according to a preferred embodiment of the present invention. In FIGS. 2A to 2G, the present invention is illustrated in detail. Therefore, the same parts as those in FIGS. 1A to 1G may be given the same reference numerals. In the preferred embodiment of the present invention, description will be made with reference to Figs. 1 and 2 at the same time. Please refer to FIG. 1 and FIG. 2 at the same time. An element isolation structure 12 is formed in a predetermined area of a semiconductor substrate 10 to define an active region 11 and an inactive region. The element isolation structure 12 is, for example, ~ Field oxide / This element isolation structure 12 is formed using conventional techniques. In addition, field oxidation of silicon can also be used selectively. Using a conventional lithographic etching process, a plurality of rhenium electrodes I4 are formed on the semiconductor substrate 10, and the periphery thereof is covered with a protective insulating layer (e.g. agricultural 1 hard mmit #). Using a conventional ion implantation step, a plurality of source / drain regions (not shown) are formed over the semiconductor substrate 10, and the plurality of source / drain regions are respectively adjacent to the side of the gate electrode I4 &. A first-oxidation position is covered by 1 side. The mouse wind is not the base of the genus μ o 『plural 存 save and connect. £%, 6 (? T〇ra ^ —onta 义 卫 ^ £ 1 wind g is formed in The first oxide layer 15 is in contact with the source / drain regions. A second oxide paper is wrapped around the Chinese National Standard (CNS) M specifications (210X297 mm) (谙 Read the precautions on the back before writing Page) Binding 412828 V. Description of the invention (3) The layer 18 fully covers the first oxide layer 15 and the contact pad 16. A plurality of bit lines I9 are formed on the second oxide layer 18. A third oxide layer 20 completely covers the first The second oxide layer 18 and the bit line 19 are formed. Then, for example, a silicon nitride layer 22 is formed over the third oxide layer 20, and the etching selectivity is different from that of the third oxide layer 20. Silicon nitride may be used. The layer 22 is used as an etching stop layer for subsequent etching of a fourth oxide layer, but the formation of the silicon nitride layer 22 is determined as needed. A first polycrystalline silicon layer 24 is deposited on the silicon nitride layer 22 This first polycrystalline silicon layer 24 is used as a wind-side volume electrode 38 plus 1 ^ 44 ^ when electrically connected). Among them, a storage electrode 46 That is, two conductive electrodes 38 and 44 and a connecting bridge electrically connected to the two conductive electrodes 38 and 44 are shown in FIG. 1G. The thickness of the first polycrystalline silicon layer M is about 550-1000. Please refer to FIG. 1B and FIG. 2B, a first photoresist layer is coated on the first to polycrystalline silicon layer 24. The first photoresist layer 26 is defined as an etching mask, and the first photoresist layer is etched. The crystalline silicon layer 24 is exposed until the silicon nitride layer 22 is exposed to form a plurality of poly crystalline silicon pattern layers 24a for connecting bridges. A poly crystalline silicon pattern layer 24a is formed, for example, corresponding to a contact pad. The position above u and the lateral extension to the contact pad 16. For detailed description, please refer to FIG. 3, which shows a dynamic state after the polycrystalline silicon pattern layer 24a is formed according to a preferred embodiment of the present invention. A top plan view of a random access memory cell capacitor. In Figure 3, the polycrystalline sand pattern layer 24a is formed at a predetermined position above the silicon nitride layer 22. The formation position and part of the polycrystalline silicon pattern layer 24a The active area 11 overlaps, and at the same time it is especially located at the -------- political --------, η ------ line {阅读 Read the notes on the back before filling out this page j

412828 4 3 8 4 pi f. Doc / 008 V. Description of the invention (A) The contact pads under one of the polycrystalline sand pattern layers 24a are arranged in a row. The polycrystalline sand pattern layer 24a is an i-shaped circle (Ellipse shape) or a rectangular shape (rectangle shape), and the length in the long direction ("a") is about 350 nm and the length in the short direction ("c") It is about 150nm. The distance ("b") between the adjacent polycrystalline silicon pattern layers 24a in a line with the bit line direction is about 250 nm, and the distance between the adjacent polycrystalline silicon pattern layers 24a with a line in the word line direction is about 250 nm. The distance ("d") is about 150nm. Please refer to FIG. 1C and FIG. 2C. After removing the defined first photoresist layer 26, a fourth oxide layer 28 is a sacrificial oxide layer. It is formed on the nitride cutting layer 22 and the polycrystalline sand pattern layer 24a. The thickness of the sacrificial oxide layer 28 is a predetermined height of the storage electrode. Therefore, the thickness of the sacrificial oxide layer 28 changes with a predetermined capacitance 値. In this embodiment, the sacrificial oxide layer 28 is formed to a thickness of about 8000 to 1000 angstroms. A material layer 30 is formed above the fourth oxide layer 28, and the material is, for example, polycrystalline silicon, and the thickness is about 1500-2000 angstroms. Since the material layer 30 has an etching selectivity different from that of the fourth oxide layer 28, it can be used as an etching mask when the subsequent step of etching the fourth oxide layer 28 is performed. A second photoresist layer covers the material layer 30, and the defined second photoresist layer 31 is used to form an opening portion corresponding to one end of the polycrystalline silicon pattern layer 24a aligned with the contact pad 16. Next, using the defined second photoresist layer 31 as a mask, the material layer 30, the fourth oxide layer 28, the polycrystalline silicon pattern layer 24a and the silicon nitride layer 22 are etched to form a plurality of first openings 32. The first opening 32 has, for example, a substantially vertical sidewall, and the first opening 32 exposes the third oxide layer 20. What you should pay attention to is a part of the polycrystalline silicon pattern-ΐ 衣 ΐHI ί I Bing (Please read the precautions on the back before filling this page} This paper is a fast-moving Chinese national standard (CNS > A4 specifications ( 2i × 297mm> 412828 A7 ^ 384pj. F.doc / 008 D / V. Description of the Invention (b) If the layer 2 is still located above the silicon nitride layer 22 and buried in the fourth oxide layer 28, and the first opening One side of 32 is connected to one end of the polycrystalline silicon pattern layer. The opening size ("e") of the first opening 32 is about 150 nm. Figure 4 illustrates a preferred embodiment according to the present invention. After forming the first opening 3 2, a top plan view of the DRAM cell capacitor. Referring to FIG. 4, the first opening 32 corresponds to the contact pad 16 and is connected to one end of the polycrystalline silicon pattern layer 24 a. After removing the defined second photoresist layer 31, as shown in FIG. 1E and FIG. 2E, a polycrystalline silicon material is formed in the first opening 32, and its thickness is about 250 nm. Using polycrystalline The silicon material layer 30 and the polycrystalline silicon spacer wall 34 are etching masks, and the third oxide layer 20 and the second oxide layer 18 are etched until exposed. The contact pad 16 is formed to form a plurality of second openings 36. The opening size of the second openings 36 is, for example, about 100 nm. Due to the formation of the gap wall 34, the second openings 36 and the first openings 32 are automatically aligned to form themselves. One column. The second opening 36 here is equivalent to the contact window of the storage electrode of a traditional simple rectangular structure capacitor. Therefore, the misalignment between the storage contact window and the storage electrode that occurs in the conventional technique can be detected. Avoid. Figure 5 illustrates a dynamic random access memory after forming a polycrystalline silicon spacer 34 on the side wall of the first opening 32 and before forming a second opening 36 according to a preferred embodiment of the present invention. A top plan view of a cell capacitor. As can be seen from the figure, due to the thickness of the polycrystalline silicon spacer 34, the opening of the second opening 36 is smaller than that of the first opening 32. Please refer to FIGS. 1F and 2F as A conductive material of the storage electrode, such as polycrystalline silicon. This polycrystalline silicon is filled with the first opening 32 and binding, (诮 Please read the precautions on the back first and then read this page) This paper size is applicable to China Home standard (CNS > A4 specification (210X297 mm) 麫 " Central part of the Ministry n · ^ · and 妁 T. " 'f < c: 5 ^ nf, I $, 412828 4384pif.doc / 008 gj __L_ _. --'' ~.. ~ V. Description of the invention ((M) The second opening 36, and the full height exceeds the polycrystalline silicon material layer 30. The polycrystalline sand and the polycrystalline silicon material layer 30 are planarized. The uranium engraving step is performed, for example, using chemical mechanical honing (CMP) or etching techniques, until the fourth oxide layer 28 is exposed to form a plurality of first conductive electrodes 38 of the storage electrode. The first conductive electrodes 38 are formed, for example, in contact. On pad 6 and in contact with it. As can be seen from the above, the polycrystalline silicon pattern layer 24a is electrically connected to one side of the first conductive electrode 38, and extends outwardly above the silicon nitride layer 22. The formation of the second conductive electrode is the next step. The second conductive electrode must be connected to the first conductive electrode 38 through a polycrystalline silicon pattern layer 24a protruding from the side of the first conductive electrode 38. To achieve this, a third photoresist layer covers the fourth oxide layer 28, and the third photoresist layer 40 is defined to form a pair of the polycrystalline silicon pattern layer 24a and the silicon nitride layer 22 at the other end. Quasi-opening. Using the defined third photoresist layer 40 as a mask, the fourth oxide layer 28 is etched to form a plurality of third openings 42. The third openings 42 are, for example, a polycrystalline silicon pattern layer 24a and silicon nitride formed at the other end. Above layer 22. Herein, the polycrystalline silicon pattern layer 24a and the silicon nitride layer 22 may be used as an etching stop layer. If a silicon nitride layer 22 ′ is not formed, the fourth oxide layer 28 must be time-controlled to achieve a better etching effect. In this preferred embodiment, the opening size ("h") of the third opening 42 is about 200 nm, and the distance ("g") from the first conductive electrode 38 is about 100 nm. After the defined third photoresist layer 40 is removed, a conductive material as a storage electrode is inserted into the third opening 42 and has a height exceeding the fourth oxide layer 28, and the conductive material is, for example, polycrystalline silicon. Next, enter 15 CNS of this polycrystalline silicon into A4 specification (2 丨 0X297mmΊ II — — — — — — — — —, order I nn vein (" Read the notes on the back first, then write the moth 蛾)浐 部 浐 Aii. ^-^ HJri / if and Mit India 412828 A7 ^ 384pif.doc / 008 ηΊ _____________ Η, _ 5. Description of the invention ((ν) ~ Perform a planarization etching step until the first The oxidized layer 28 is used to form a plurality of second conductive electrodes 44 of the storage electrode. The formed second conductive electrode 44 is electrically connected to the first conductive electrode 38 through the polycrystalline silicon pattern layer 24a. | Explode, with 'elea.rods.) 46, and each storage electrode 46 of a bipolar type includes a first conductive electrode 3 8', a second conductive electrode 44 and a polycrystalline silicon pattern layer 24a, as shown in Figure 1G And Figure 2 (shown in FIG. 3). Attached _at plus. Figure 6 shows a dynamic random access memory cell capacitor 0 after the second conductive electrode 44 is formed according to a preferred embodiment of the present invention. Figure. Please refer to Figure 6. Diode type storage electrode: 46w, including the first coupling with storage contact pad (not shown in the figure). The conductive electrode 38, the second conductive electrode 44, and the polycrystalline sand pattern layer 24a for connecting the first conductive electrode 38 and the second conductive electrode 44. The distance between adjacent storage electrodes is measured along the direction of the bit line. The distance ("i") is about I50nm, and the distance between adjacent storage electrodes measured along the direction of the word line is about 150nm. Next, a dielectric layer (not shown in the figure) and An upper electrode (not shown in the figure) is sequentially formed on the storage electrode 46 of the two-pole type to form a double-pole type capacitor. , Wu nose air surface «point. In addition, the main storage electrode (the first lead electrode 38) is the size of this paper suitable for Chinese National Standard (CNS) A4 specifications (2) 0 × 2ί > 7 mm) I, binding. Slave (I read it on the back first) ± Issue items and then fill out this page) A7 B7 Stress development — *-Πιι · ν., ... Two-phase 4 3 8 4 pif .doc / lo ^^^ V. Description of the invention ((Transfer): Difficult to accomplish, making the manufacturing process of the main storage electrode simplified. According to the present invention, when the increase in channeling device is increased, 'available .. α & amp The weeping fog is shocking, and it does not need to be like the BST iron zero snow layer because of the formation of the ferroelectric material's dielectric needs to be under high temperature conditions, it is easy to cause. Not _ Fusheng. Figure 7 shows It is a schematic diagram of a storage electrode structure of an adjacent bipolar type according to a preferred embodiment of the present invention. The storage electrode structure of this bipolar type will refer to FIGS. 1G and 7. The storage electrode 46 of the bipolar type includes a first conductive electrode 38, a second conductive electrode 44 and a polycrystalline silicon pattern layer 24a. The polycrystalline sand pattern ... SJ break surface 丄 6 to 16 is connected to the source / drain region. Therefore, the first conductive electrode 38 can be coupled to the source / drain region through the storage contact pad π. In addition, the second conductive electrode 44 is connected to the other end of the polycrystalline silicon pattern layer 24a. Bit size. The number of the second conductive electrodes 44 may be increased due to the reduction in the size of the second conductive electrodes 44 and the polycrystalline sand pattern layer 24a. The size of the upper half of the first conductive electrode 38 is about 150 nm, and the size of the lower half thereof is about 100 nm. The size of the second conductive electrode 44 is about 200 nm. The distance between two adjacent storage electrodes is about 150 nm, and the distance between the first conductive electrode 38 and the second conductive electrode 44 is about 100 nrn. Although the present invention has been disclosed as above with a preferred embodiment, it does not use 17 I ^ t I 1 > ', (" Read the precautions on the back before writing this page) CNS) A4 specification (210X297 mm) 412828 at d-384pif, doc / 008 g7 V. Description of the invention (called) To limit the invention, anyone skilled in the art can depart from the spirit and scope of the invention. Various modifications and retouchings are made, so the protection scope of the present invention shall be determined by the scope of the appended patent application. -------- 装 — (Please read the precautions on the back of the pin first, then this page.) Ding-° h 浐 部 屮 Ai; ^^, m; 7i 竹 合 竹. ^-印 ΐ

S This paper is suitable for Sichuan National Standard (CNS) Α4 size (210X297 mm)

Claims (1)

Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 412828 Μ α ο c '3 Ο f Six. Patent application scope 1. A method for manufacturing a cell capacitor of dynamic random access memory, the method includes: A gate electrode and a pair of semiconductor substrates in the source / drain region adjacent to the gate electrode side; forming a pair of storage contact pads in contact with the source / drain region; forming a first insulating layer on the A semiconductor substrate is formed; a conductive pattern layer is formed on the first insulating layer, the conductive layer pattern overlaps with the storage contact pad and extends to one of the storage contact pads; the conductive pattern layer has an opposite A second insulating layer and a first material layer are sequentially formed on the first insulating layer containing the conductive pattern layer, and the first material layer and the second green insulating layer have different etch rates; A first lithography step etches the first material layer, the second insulation layer and the conductive pattern layer to form a first opening that exposes the first insulation layer and is over one of the storage contact pads, and the first Opened Penetrating one end of the conductive pattern layer; forming a conductive sidewall gap wall at the first opening; using the conductive sidewall gap wall and the first material layer as a cover, etching the first insulating layer to one of the storage contact pads To form a second opening; deposit a conductive material in the first opening and the second opening and beyond the first material layer, and planarize until the second insulating layer is exposed to form a first conductive electrode ; Using a second lithography step, etching the second insulating layer until the other end of the first insulating layer and the conductive pattern layer is exposed, and forming a 19th paper standard applicable to China National Standards (CNS) Λ4 specification (210X297 mm) (Please read the precautions on the back before filling this page) • Equipment-Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 412828 A8 B8 4 3 S 4 ο 1 f, d ο c / Ο 0 S Yiliu, a third opening with an opening interval in the scope of patent application; and filling the third opening with the same material as the first conductive electrode to form a second conductive electrode through the conductive pattern Layer with The first conductive electrode is connected, wherein the first conductive electrode, the third conductive electrode, and the conductive pattern layer constitute a storage electrode of a cell capacitor of the dynamic random access memory. 2. The method according to item 1 of the scope of patent application, wherein the material of the conductive pattern layer is the same as that of the first conductive electrode. 3. The method according to item 1 of the scope of patent application, wherein the second insulating layer has at least the same thickness as the storage electrode. 4. The method according to item 1 of the scope of patent application, wherein the second insulating layer includes an oxide layer, and the first material layer includes a polycrystalline sand layer. 5. The method according to item 1 of the scope of patent application, wherein the conductive pattern layer has a thickness of about 550-1000 angstroms, the second insulating layer has a thickness of about 8000-1 1000 angstroms, and the first material layer has A thickness of about 1500-2000 Angstroms. 6. The method according to item 1 of the scope of patent application, wherein the material of the sidewall spacer is the same as that of the first conductive electrode. 7. The method according to item 1 of the scope of patent application, wherein the planarization method is, for example, one of chemical mechanical honing method and etch-back. 8. The method according to item 1 of the scope of patent application, wherein the diameter of the first opening is approximately 150 nm, the diameter of the second opening is approximately 100 nm, and the diameter of the second opening is approximately 200 nm. 9. The method as described in item 1 of the scope of patent application, wherein the first guide 20 I --------good --- I n _ τ _ _ _ _ _. Xiang (please read the first Note: Please fill in this page again) This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) A BCD 412828 SS ρ 1 i.doc / L! 〇8 6. Patent application scope electrode and the second guide The electrodes are approximately 100 nm apart from each other, and the storage electrode is approximately 150 nm apart from adjacent storage electrodes. 10. The method according to item 1 of the scope of patent application, further comprising forming a second material layer on the first insulating layer before forming the conductive pattern layer, and the second material layer has a second insulation from the second insulation layer. Layers with different etch rates, and the second material layer is an etching stop layer in the step of forming the third opening. 11. The method of claim 10, wherein the second material layer includes a silicon nitride layer. 12. —Dynamic random access memory cell capacitor, the device includes: a storage contact pad formed on a semiconductor substrate and electrically connected to a source / drain region of the semiconductor substrate; an insulating layer formed on the semiconductor substrate; A semiconductor substrate including a storage contact pad; and a storage electrode of a dynamic random access memory cell capacitor having a first and a second conductive electrode, the first and the second conductive electrode being spaced apart from each other, but formed by The conductive pattern layers on the insulating layer are electrically connected to each other. The first conductive electrode penetrates the insulating layer and is electrically connected to the storage contact pad. 13. The dynamic random access memory cell capacitor according to item 12 of the scope of the patent application, wherein the diameter of the first conductive electrode at the top is about 15 nm, and the diameter of the bottom of the first conductive electrode is about 100. nm, the diameter of the second conductive electrode is about 200 nm. · 14. The dynamic random access memory cell capacitor as described in item 12 of the scope of the patent application, wherein the first- and second-conductive electrodes are separated from each other by about 100 nm, and the storage electrode is adjacent to the storage electrode. About 150nm apart. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)---.......-i -...... I--id t ^ i I---- ^^ 1 \ —Ψ -5 (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs