TW299482B - Manufacturing method of capacitor of memory cell in DRAM - Google Patents

Manufacturing method of capacitor of memory cell in DRAM Download PDF

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Publication number
TW299482B
TW299482B TW85110544A TW85110544A TW299482B TW 299482 B TW299482 B TW 299482B TW 85110544 A TW85110544 A TW 85110544A TW 85110544 A TW85110544 A TW 85110544A TW 299482 B TW299482 B TW 299482B
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Taiwan
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layer
capacitor
conductive layer
forming
conductive
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TW85110544A
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Chinese (zh)
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Chyuan-Jong Wang
Menq-Song Liang
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Taiwan Semiconductor Mfg
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Abstract

A manufacturing method of capacitor of memory cell in DRAM, which is applicable to semiconductor substrate with formed MOS transistor to implement capacitor of memory cell, comprises of the following steps: (1) on the above semiconductor substrate in sequence forming insulator and etch stop layer; (2) on insulator and etch stop layer of either drain or source region of the above MOS transistor forming contact hole; (3) on the above contact hole and etch stop layer forming first conductive layer; (4) to the above first conductive layer performing etching back to remove first conductive layer located on the above etch stop layer; (5) forming second conductive layer, and performing etching back, and on internal wall of the above contact hole on first conductive layer inside the above contact hole forming conductive sidewall spacer; (6) on the above etch stop layer forming first sacrifice layer, and on the above first sacrifice layer forming opening to confine bottom plate range of the above capacitor; (7) on the above opening and first sacrifice layer forming second sacrifice layer; (8) in sequence to the above second sacrifice layer and third conductive layer performing etching back, and removing third conductive layer located on the above first sacrifice layer; (9) removing the above first sacrifice layer and second sacrifice layer, and making first conductive layer, conductive sidewall spacer and third conductive layer located inside the above contact hole become bottom plate of the above capacitor; (10) on bottom plate of the above capacitor forming dielectric; and (11) on the above dielectric forming top plate of the above capacitor.

Description

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（i) -— 本發明係有關於一種動態隨機存取記憶體（DRAM)之 記憶格(memory cell)之電容器的製造方法，特別有關於一 種能狗減少佔晶片的面積且能夠提高可靠度（reliabimy)的 動態随機存取記憶體之記憶格之電容器的製造方法。 動態随機存取記憶體已是廣泛使用的積體電路(ic)。 而一般之動態隨機存取記憶體的記憶格則如第丨圖所示， 包括一 MOS電晶體10以及一電容器12。其中，上述M〇s 電晶體10的閘極係連接至字元線WL(word line)，而其汲 極和源極則分別連接至位元線BL(bit line)和經由上述電容 器12而接地。且上述電容器12係用以儲存資料（data)。 請參照第2圖，第2圖係顯示用以説明習知動態隨機 存取記憶體之記憶格之電容器的製造方法的剖面圖。習知 動態隨機存取記憶體之記憶格之電容器的製造方法係用於 如第2圖（a)所示之形成有MOS電晶體20的半導體基板 2。且在第2圖⑷中，202、204及206分別爲上述MOS 電晶體20的閘極、閘極氧化物及源極/汲極區，而208爲 場區氧化物（field oxide)。又上述習知動態隨機存取記憶體 之記憶格之電容器的製造方法包括下列步驟： (1) 如第2圖（b)所示，於上述半導體基板2上依序沈積 氧化物層212及氮化物層214。 (2) 如第2圖（c)所示，於上述MOS電晶體20之汲極區 及源極區206中之一者上的氧化物層212及氮化物層214 以石版印刷術（photolithography)及乾你刻而形成接觸窗 222 〇 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ2ί>7公釐） (請先閱讀背面之注意事項再填寫本頁) 令· Γ 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（2) (3) 如第2圖（d)所示，於上述接觸窗222及氮化物層214 上形成複晶矽層232(如虛線所示），7然後對上述複晶矽 層232進行回蝕刻（etch back)，而去除位於上述氮化物層 214上的複晶矽層232，進而保留位於上述接觸窗222内 的複晶矽234。 (4) 如第2圖（e)所示，於上述氮化物層214上沈積 PETEOS層242，並於上述PETEOS層242以石版印刷術 及乾蝕刻而形成開口 244，以界定電容器之下電極板的範 圍。 (5) 如第2圖（f)所示，於上述開口 244及PETEOS層242 上依序沈積複晶矽層252及PETEOS層254。 (6) 如第2圖（g)所示，依序對上述PETEOS層254及複 晶秒層252進行回蝕刻，而去除於上述PETEOS層242上 的複晶矽層252。 (7) 如第2圖（h)所示，以濕蝕刻去除上述PETEOS層 242、254 ,而使位於上述接觸窗222内的複晶矽234及複 晶妙層252成爲上述電晶體的下電極板。 (8) 如第2圖⑴所示，於上述下電極板上依序形成介電 層262及上電極板264。 然而，如第3圖所示，由於對上述複晶矽層232進行 回餘刻時，會因爲過蝕刻（over etch)而使複晶矽234低於上 述氮化物層214，進而露出上述氧化物層212，且若於蝕 刻上述開口 244時，因對不準(misalign)，而使上述開口 244 偏離上述複晶矽234，故於濕蝕刻去除上述PETEOS層 本紙張尺度通用中國國家榡率（CNS) A4規格（21Gx297公们 (請先K讀背面之注意事項再填寫本頁) tr S994S2A7 B7 printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (i)-This invention relates to a method for manufacturing a capacitor of a memory cell of a dynamic random access memory (DRAM), in particular The invention relates to a method for manufacturing a capacitor of a memory cell of a dynamic random access memory capable of reducing the area of a chip and improving reliability. Dynamic random access memory is a widely used integrated circuit (ic). The memory cell of a general dynamic random access memory, as shown in FIG. 1, includes a MOS transistor 10 and a capacitor 12. Wherein, the gate of the above-mentioned Mos transistor 10 is connected to the word line WL (word line), and its drain and source are respectively connected to the bit line BL (bit line) and to the ground via the capacitor 12 . And the capacitor 12 is used to store data. Please refer to FIG. 2, which is a cross-sectional view illustrating a method of manufacturing a capacitor for a memory cell of a conventional dynamic random access memory. The manufacturing method of the memory cell capacitor of the dynamic random access memory is used for the semiconductor substrate 2 on which the MOS transistor 20 is formed as shown in FIG. 2 (a). And in FIG. 2 (2), 202, 204, and 206 are the gate, gate oxide, and source / drain regions of the MOS transistor 20, respectively, and 208 is the field oxide. In addition, the manufacturing method of the memory cell capacitor of the conventional dynamic random access memory includes the following steps: (1) As shown in FIG. 2 (b), an oxide layer 212 and nitrogen are sequentially deposited on the semiconductor substrate 2化 物 层 214. (2) As shown in FIG. 2 (c), the oxide layer 212 and the nitride layer 214 on one of the drain region and the source region 206 of the MOS transistor 20 are photolithography The contact window is formed as you cut it 222. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210Χ2ί > 7mm) (please read the precautions on the back before filling out this page) Order · Γ The Ministry of Economic Affairs Central Standards Bureau Printed by staff consumer cooperatives A7 B7 V. Description of the invention (2) (3) As shown in Figure 2 (d), a polycrystalline silicon layer 232 is formed on the contact window 222 and the nitride layer 214 (shown by the dotted line) 7. Then, the polysilicon layer 232 is etched back to remove the polysilicon layer 232 located on the nitride layer 214, thereby remaining the polysilicon 234 located in the contact window 222. (4) As shown in FIG. 2 (e), a PETEOS layer 242 is deposited on the nitride layer 214, and an opening 244 is formed in the PETEOS layer 242 by lithography and dry etching to define an electrode plate under the capacitor Scope. (5) As shown in FIG. 2 (f), a polycrystalline silicon layer 252 and a PETEOS layer 254 are sequentially deposited on the opening 244 and the PETEOS layer 242. (6) As shown in FIG. 2 (g), the PETEOS layer 254 and the polycrystalline second layer 252 are etched back in order to remove the polycrystalline silicon layer 252 on the PETEOS layer 242. (7) As shown in FIG. 2 (h), the PETEOS layers 242 and 254 are removed by wet etching, so that the polycrystalline silicon 234 and the polycrystalline wonderful layer 252 located in the contact window 222 become the lower electrode of the transistor board. (8) As shown in Fig. 2 (1), a dielectric layer 262 and an upper electrode plate 264 are formed in this order on the lower electrode plate. However, as shown in FIG. 3, when the polysilicon layer 232 is returned to the rest, the polysilicon 234 is lower than the nitride layer 214 due to over-etching, thereby exposing the oxide Layer 212, and if the opening 244 is etched, the opening 244 deviates from the polycrystalline silicon 234 due to misalignment, so the PETEOS layer is removed by wet etching. The paper standard is the general Chinese national rate (CNS ) A4 specification (21Gx297 males (please read the notes on the back before filling in this page) tr S994S2

經濟部中央標準局員工消費合作社印製 發明説明（^ 254、242時，會經由上述複晶層252與上述氮化物層214 之間的間隙272而蝕刻到上述氧化物層212，進而形成空 洞274，因而降低其可靠度。又若欲加大上述開口 244， 以解決上述問題，則會增加其所佔晶片的面積。 有錯於此，本發明之目的係爲了解決上述問題而提供 一種動態隨機存取記憶體之記憶格之電容器的製造方法， 適用於形成有MOS電晶體的半導體基板上製作記憶格的 電容器’而上述動態随機存取記憶體之記憶格之電容器的 製造方法包括下列步驟：於上述半導體基板上依序形成絕 緣層及蝕刻終止層；於上述M〇s電晶體之汲極區及源極區 中之一者上的絕緣層及蝕刻終止層形成接觸窗；於上述接 觸窗及蝕刻終止層上形成第一導電層；對上述第一導電層 進行回蚀刻，而去除位於上述蚀刻終止層上的第一導電 層，形成第二導電層，並進行回蚀刻，而於上述接觸窗内 的第一導層上的上述接觸窗内壁形成導電邊牆間隔物；於 上述蝕刻終止層上形成第一犧牲層，並於上述第一犧牲層 形成開口，以界定上述電容器之下電極板的範圍；於上述 開口及第一犧牲層上形成第三導電層；於上述第三導電層 上形成第二犧牲層；依序對上述第二犧牲層及第三導電層 進行回蝕刻，而去除位於上述第一犧牲層上的第三導電 層；去除上述第一犧牲層及第二犧牲層；而使位於上述接 觸窗内的第一導電層、導電邊牆間隔物及第三導電層成爲 上述電容器的下電極板；於上述電容器的下電極板上形成 介電層；以及於上述介電層上形成上述電容器的上電極 表紙張尺度適家橾準（CNS ) A4規格（210X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁)The invention description printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (^ 254, 242 is etched into the oxide layer 212 through the gap 272 between the polycrystalline layer 252 and the nitride layer 214, thereby forming a cavity 274 Therefore, the reliability is reduced. If you want to increase the opening 244 to solve the above problem, it will increase the area of the chip. Wrong here, the purpose of the present invention is to solve the above problem and provide a dynamic random A manufacturing method of a capacitor for accessing a memory cell of a memory is suitable for manufacturing a capacitor of a memory cell on a semiconductor substrate formed with a MOS transistor, and the manufacturing method of the capacitor of a memory cell of the dynamic random access memory includes the following steps : Forming an insulating layer and an etch stop layer on the semiconductor substrate in sequence; forming a contact window on the insulating layer and the etch stop layer on one of the drain and source regions of the Mos transistor; forming the contact A first conductive layer is formed on the window and the etch stop layer; the first conductive layer is etched back, and the first layer on the etch stop layer is removed A conductive layer, forming a second conductive layer, and etching back, and forming a conductive sidewall spacer on the inner wall of the contact window on the first conductive layer in the contact window; forming a first sacrificial layer on the etch stop layer, And forming an opening in the first sacrificial layer to define the range of the electrode plate under the capacitor; forming a third conductive layer on the opening and the first sacrificial layer; forming a second sacrificial layer on the third conductive layer; The second sacrificial layer and the third conductive layer are etched back to remove the third conductive layer on the first sacrificial layer; the first sacrificial layer and the second sacrificial layer are removed; The first conductive layer, the conductive sidewall spacer and the third conductive layer become the lower electrode plate of the capacitor; forming a dielectric layer on the lower electrode plate of the capacitor; and forming the upper electrode of the capacitor on the dielectric layer Table paper size suitable family standard (CNS) A4 specification (210X 297mm) (Please read the precautions on the back before filling this page)

經濟部中央標準局員工消費合作社印製 A7 ------- B7 五、發明説明（4 ) ~~~' —'~~ 板。 依據本發明之動態隨機存取記憶體之記憶格之電容器 $製造方法，由於在接觸窗内的第一導電層上的上述接觸 =的内壁形成導電邊播間_，故即使用以界定電容器之 I巧用的開口對不準，亦不會於絕緣㈣成空洞，而能夠 提高其可靠度。且由於亦可縮小上述開口的寬度至大體與 上述接觸窗相同，故能夠縮小其所佔晶片的面積。 以下，就圖式説明本發明之動態隨機存取記億體之記 憶格之電容器的製造方法的實施例。 圖式簡單説明 第1圖係顯示動態随機存取記憶體之記憶格部份的電 路圖； 第2圖係顯示用以説明習知動態隨機存取記憶體之記 憶格之電容器的製造方法的剖面圖； 第3圖係顯示用以説明習知動態隨機存取記憶體之記 憶格之電容器的製造方法所造成之問題的剖面圖； 第4圖係顯示用以説明本發明之動態随機存取記憶體 之記憶格之電容器的製造方法的剖面圖；以及 第5圖係顯示用以説明本發明之動態随機存取記憶體 之記憶格之電容器的製造方法所解決之問題的剖面圖。 [符號説明] 2、3〜半導體基板；10、20、30〜MOS電晶體；12〜 電容器；202、302〜閘極；204、304〜閘極氧化物； 206、306〜源極/汲極區；208、308〜場區氧化物；212~ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 〖袈-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局^:工消費合作社印製 A7 B7 五、發明説明（5 ) 氧化物層；214〜氮化物層；222、322〜接觸窗；242、 254〜PETEOS 廣；244、344〜開 232、234、252〜複 晶矽層；262、362~介電層；264、346〜上電極板；272〜 空隙；274〜空洞；312〜絕緣層；314〜蝕刻終止層； 332、334、336、352〜導電層；338〜導電邊牆間隔物； 342、354〜犧牲層。 實施例 請參照第4圖，第4圖係顯示用以説明本發明之動態 隨機存取記憶體之記憶格之電容器的製造方法剖面圖。本 發明之動態隨機存取記憶體之記憶格之電容器的製造方法 係適用於如第4圖（a)所示之形成有MOS電晶體30的半導 體基板3。且在第4圖（a)中，302、304、306分別爲上 述MOS電晶體30閘極、閘極氧化物及源極/汲極區，而308 爲場區氧化物。又上述本發明之動態隨機存取記憶體之記 憶格之電容器的製造方法包括下列步驟。 步驟一 如第4圖（b)所示，於上述半導體基板3上依序形成絕 緣層312及蝕刻終止層314。 例如，依序沈積氧化物層312及氮化物層314。 步驟二 如第4圖（c)所示，於上述MOS電晶體30之汲極區及 源極區306中之一者上的絕緣層312及蝕刻終止層314形 成接觸窗322。 例如以石版印刷術（photolithography)及乾餘刻（例如 本紙張尺度適用中國國家標準（CNS〉A4规格（210X297公釐） I - I .^1 - - - n ^ I 丁............. I I US. i·- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（6 ) RIE)來蝕刻出上述接觸窗322。 步驟三 如第4圖（d)所示，首先於上述接觸窗322及蝕刻終止 層314上形成第一導電層332(如虛線所示），然後對上述第 一導電層332進行回餘刻（etch back)，而去除位於上述餘 刻終止層314上的第一導電層332，進而保留位於上述接 觸窗322内的第一導電層334。 例如，首先沈積複晶矽層332，然後對上述複晶層332 進行回蝕刻，而保留位於上述接觸窗322内的複晶矽334。 步驟四 如第4圖（e)所示，形成第二導電層336(如虛線所示）， 並對上述第二導電層336進行回蝕刻，而於上述接觸窗322 内的第一導電層334上的上述接觸窗322的内壁形成導電 邊摇間隔物（sidewall spacer)338。 例如，首先沈積複晶矽層336(如虛線所示），然後對上 述複晶矽層336進行回蝕刻，而形成上述複晶矽邊牆間隔 物338。此時，由於上述複晶矽334亦會蝕刻出凹陷部 334a，故可增加電容器的容電面積。 步驟五 如第4圖（f)所示，於上述蝕刻終止層314上形成第一 犧牲層342，並於上述第一犧牲層342形成開口 344，以 界定上述電容器之下電極板的範圍。 例如，首先沈積PETEOS層342，然後以石版印刷術 及乾蝕刻（例如RIE)來蝕刻出上述開口 344。 8 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） --------4 裝------訂------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（7 ) 步驟六 如第4圖（g)所示，於上述開口 344及第一犧牲層342 上依序形成第三導電層352及第二犧牲層354。 例如，依序沈積複晶矽層352及PETEOS層354。 步驟七 如第4圖（h)所示，依序對上述第二犧牲層354及上述 第三導電層352進行回蝕刻，而去除位於上述第一犧牲層 342上的第三導電層352。 步驟八 如第4圖⑴所示，去除上述第一犧牲層342及第二犧 牲層354，而使位於上述接觸窗322内的第一導電層334、 導電邊牆間隔物338及第三導電層352成爲上述電容器的 下電極板。 例如，以濕蝕刻來去除上述PETOES層342及354。 步驟九 如第4圖⑴所示，依序於上述電容器的下電極板上形 成介電層362及上述電容器的上電極板364。 例如，上述介電層362可由氧化物-氣化物-氧化物 (ΟΝΟ)構成，而上述電容器的上電極板364可由沈積複晶 砂層來形成。 功效 請參照第5圖，第5圖係顯示用以説明本發明之動態 隨機存取記憶體之記憶格之電容器的製造方法所解決之問 題的剖面圖。由於本發明於第一導電層334上的接觸窗322 9 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ：297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝- 、1Τ A7 '—------- B7 五、發明説明（8 ) _ ~ 内壁形成有導電邊輪間隔物338，而不會露出上述絕緣廣 312，故即使界定上述電容器之範圍用的開口 344對不準， 耶不會於餘刻上述第-犧牲看342及第二犧牲廣354時蚀 刻到上述絕緣層312，而可縮小上述開口 344(例如使上述 開口 344的寬度大體等於上述接觸窗322)，進而可縮小其 所佔晶片的面積，且可提高其可靠度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脱離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之保 濩範圍當視後附之申請專利範圍所界定者爲準。 I i^n I I nn m In ^ -I -- - K^— m n^i J vs. ,-* (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製A7 ------- B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (4) ~~~ '—' ~~ board. According to the manufacturing method of the capacitor of the memory cell of the dynamic random access memory of the present invention, since the inner wall of the above-mentioned contact = on the first conductive layer in the contact window forms a conductive edge space_, it is even used to define the capacitor The opening used by I is not correct, and it will not form a hole in the insulation, which can improve its reliability. Moreover, since the width of the opening can be reduced to be substantially the same as that of the contact window, the area of the wafer can be reduced. Hereinafter, an embodiment of a method for manufacturing a dynamic random access memory cell capacitor of the present invention will be described with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a memory cell portion of a dynamic random access memory; FIG. 2 is a cross section illustrating a method of manufacturing a capacitor for a memory cell of a conventional dynamic random access memory Figure 3 is a cross-sectional view showing the problems caused by the manufacturing method of a conventional dynamic random access memory cell capacitor; Figure 4 is a dynamic random access used to illustrate the present invention A cross-sectional view of a method of manufacturing a memory cell capacitor of a memory; and FIG. 5 is a cross-sectional view illustrating a problem solved by a method of manufacturing a memory cell capacitor of a dynamic random access memory of the present invention. [Description of symbols] 2, 3 ~ semiconductor substrate; 10, 20, 30 ~ MOS transistor; 12 ~ capacitor; 202, 302 ~ gate; 204, 304 ~ gate oxide; 206, 306 ~ source / drain Area; 208, 308 ~ field oxide; 212 ~ This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 〖袈-(please read the precautions on the back before filling this page) Order the Ministry of Economy Central Bureau of Standards ^: Printed by the Industry and Consumer Cooperatives A7 B7 V. Description of the invention (5) Oxide layer; 214 ~ nitride layer; 222, 322 ~ contact window; 242, 254 ~ PETEOS wide; 244, 344 ~ Kai 232, 234, 252 ~ polycrystalline silicon layer; 262, 362 ~ dielectric layer; 264, 346 ~ upper electrode plate; 272 ~ void; 274 ~ void; 312 ~ insulating layer; 314 ~ etch stop layer; 332, 334, 336, 352 ~ conductive layer; 338 ~ conductive side wall spacer; 342, 354 ~ sacrificial layer. Embodiment Please refer to FIG. 4, which is a cross-sectional view showing a method for manufacturing a capacitor of a memory cell of a dynamic random access memory of the present invention. The manufacturing method of the memory cell capacitor of the dynamic random access memory of the present invention is applicable to the semiconductor substrate 3 in which the MOS transistor 30 is formed as shown in FIG. 4 (a). And in FIG. 4 (a), 302, 304, and 306 are the gate, gate oxide, and source / drain regions of the MOS transistor 30, respectively, and 308 is the field region oxide. In addition, the manufacturing method of the memory cell capacitor of the dynamic random access memory of the present invention includes the following steps. Step 1 As shown in FIG. 4 (b), an insulating layer 312 and an etch stop layer 314 are formed on the semiconductor substrate 3 in this order. For example, the oxide layer 312 and the nitride layer 314 are deposited in sequence. Step 2 As shown in FIG. 4 (c), the insulating layer 312 and the etch stop layer 314 on one of the drain region and the source region 306 of the MOS transistor 30 form a contact window 322. For example, lithography (photolithography) and dry engraving (for example, this paper scale is applicable to the Chinese national standard (CNS> A4 specification (210X297 mm) I-I. ^ 1---n ^ I Ding ... ....... II US. I ·-(Please read the precautions on the back before filling in this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention Instructions (6) RIE) to be etched The contact window 322. As shown in FIG. 4 (d), the third step is to first form a first conductive layer 332 (shown by a dotted line) on the contact window 322 and the etch stop layer 314, and then to the first conductive layer 332 An etch back is performed to remove the first conductive layer 332 located on the etch stop layer 314, thereby remaining the first conductive layer 334 located in the contact window 322. For example, the polycrystalline silicon layer 332 is first deposited Then, the polycrystalline layer 332 is etched back, leaving the polycrystalline silicon 334 located in the contact window 322. Step 4 is as shown in FIG. 4 (e), forming a second conductive layer 336 (shown by broken lines) , And the second conductive layer 336 is etched back, and the first in the contact window 322 A conductive sidewall spacer 338 is formed on the inner wall of the contact window 322 on the conductive layer 334. For example, a polycrystalline silicon layer 336 (shown by a dotted line) is first deposited, and then the polycrystalline silicon layer 336 is etched back To form the polysilicon sidewall spacer 338. At this time, since the polysilicon 334 will also etch the concave portion 334a, it can increase the capacitance area of the capacitor. Step 5 is shown in Figure 4 (f) , A first sacrificial layer 342 is formed on the etch stop layer 314, and an opening 344 is formed on the first sacrificial layer 342 to define the range of the electrode plate under the capacitor. For example, the PETEOS layer 342 is first deposited, and then lithographically printed And dry etching (such as RIE) to etch the above opening 344. 8 This paper size is applicable to the Chinese National Standard Falcon (CNS) A4 specification (210X297mm) -------- 4 Pack ------ Order ------ ^ (Please read the precautions on the back before filling out this page) A7 B7 printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (7) Step 6 is as shown in Figure 4 (g) Shown, sequentially formed on the opening 344 and the first sacrificial layer 342 The third conductive layer 352 and the second sacrificial layer 354. For example, the polycrystalline silicon layer 352 and the PETEOS layer 354 are deposited in sequence. Step 7 As shown in FIG. 4 (h), the second sacrificial layer 354 and the above are sequentially deposited The third conductive layer 352 is etched back, and the third conductive layer 352 on the first sacrificial layer 342 is removed. Step 8: As shown in FIG. 4 (1), the first sacrificial layer 342 and the second sacrificial layer 354 are removed, so that the first conductive layer 334, the conductive sidewall spacer 338, and the third conductive layer in the contact window 322 are removed 352 becomes the lower electrode plate of the above capacitor. For example, the above-mentioned PETOES layers 342 and 354 are removed by wet etching. Step 9: As shown in Fig. 4 (1), a dielectric layer 362 and an upper electrode plate 364 of the capacitor are formed in this order on the lower electrode plate of the capacitor. For example, the dielectric layer 362 may be composed of oxide-vapor-oxide (ONO), and the upper electrode plate 364 of the capacitor may be formed of a deposited polycrystalline sand layer. Efficacy Please refer to FIG. 5, which is a cross-sectional view illustrating a problem solved by a method for manufacturing a memory cell capacitor of a dynamic random access memory of the present invention. Due to the contact window 3229 of the present invention on the first conductive layer 334, the paper size is applicable to the Chinese National Standard (CNS) Α4 specification (210Χ: 297mm) (please read the precautions on the back before filling this page). 1Τ A7 '----------- B7 V. Description of the invention (8) _ ~ The inner wall is formed with conductive side wheel spacers 338 without exposing the above-mentioned insulation width 312, so even if the opening for the scope of the above-mentioned capacitor is defined 344 is misaligned, it will not be etched into the insulating layer 312 when the first-sacrificial view 342 and the second sacrificial view 354 are left, and the opening 344 can be reduced (for example, the width of the opening 344 is substantially equal to the contact window 322), which can reduce the area of the wafer it occupies, and can improve its reliability. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the attached patent application. I i ^ n I I nn m In ^ -I--K ^ — m n ^ i J vs.,-* (please read the notes on the back before filling this page) Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

Claims (1)

、申請專利範圍 方法，W ra動^隨機存取記憶體之記憶格之電容器的製造 格的電^於形成有M Qs電^體的半導體基板上製作記憶 器，製:方二 =機存取記憶體之記憶格之電容 於上述半導體基板上依序形成絕緣層及餘刻終止屬； 绍绐t上述M〇S電晶體之汲極區及源極區中之-者上的 絕緣看及蚀刻終止層形成接觸窗； 於上述接觸窗及蝕刻終止層上形成第一導電層； 對上逑第-導電層進行回餘刻，而去除位於上述蚀刻 終止層上的第一導電層； 形成第二導電層，並進行回蝕刻，而於上述接觸窗内 的第了導層上的上述接觸窗内壁形成導電邊牆間隔物； 於上述蝕刻終止層上形成第一犧牲層，並於上述第— 犧牲層形成開π，以界定上述電容器之下電極板的範圍； 於上述開口及第一犧牲層上形成第三導電層； 於上述第三導電層上形成第二犧牲層； 依序對上述第二犧牲層及第三導電層進行回蝕刻，而 去除位於上述第一犧牲層上的第三導電廣； 經濟部中央標準局員工消費合作社印裝 ί Ί — (請先閱讀背面之注意事項再填寫本頁) 、1Τ 去除上述第一犧牲層及第二犧牲層；而使位於上述接 觸窗内的第一導電層、導電邊牆間隔物及第三導電層成爲 上述電容器的下電極板； 於上述電容器的下電極板上形成介電廣；以及 於上述介電層上形成上述電容器的上電極板。 2.如申請專利範圍第1項所述的動態隨機存取記憶體 私紙張尺度逋用中國國家標準（CNS ) A4規格（210X297公釐} A8 B8 __ C8 '申請專利範園 之《•己tf'格之電容器的製造方法，其中上述絕緣層爲氧化 物。 、二3.如申請專利範圍第2項所述的動態隨機存取記憶體 〈記憶格之電容器的製造方法，其中上述第—犧牲廣及第 二犧牲層爲PETEOS。 4.如申請專利範圍第3項所述的動態随機存取記憶體 《記憶格之電容器的製造方法，其中上述蚀刻終止廣爲氣 化物。 5 ·如申4專利範圍第1、2、3或4項所述的動態隨機 存取記憶體之記憶格之電容器的製造方法，其中上述第一 導電層、第二導電層及第三導電層爲複晶矽。 、6.如申請專利範圍第5項所述的動態隨機存取記憶體 之尤憶格之電容器的製造方法，其中上述介電層係由氧化 物-氮化物-氧化物構成。 7如申請專利範圍第6項所述的動態隨機存取記憶體 之記憶格之電容器的製造方法，其中上述電容器的上電極 板爲複晶矽。 ί -¾------IT------^ ^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印II -紙 本 準 標 家 I國 一國 中 用 適 2 H 釐 一公 7 9 2、 The method of applying for the patent scope, Wra moving ^ random access memory memory cell capacitor manufacturing grid electricity ^ making memory on the semiconductor substrate formed with M Qs electricity body, system: Fang two = machine access The capacitance of the memory cell of the memory is formed on the semiconductor substrate in sequence and the remaining termination is terminated; Shao tiant Insulation and etching on one of the drain and source regions of the above MOS transistor The stop layer forms a contact window; a first conductive layer is formed on the contact window and the etch stop layer; the upper conductive layer is etched back to the rest, and the first conductive layer on the etch stop layer is removed; a second is formed Conductive layer and etch back, and the conductive sidewall spacer is formed on the inner wall of the contact window on the second conductive layer in the contact window; a first sacrificial layer is formed on the etch stop layer, and on the first-sacrifice Forming an opening π to define the range of the electrode plate under the capacitor; forming a third conductive layer on the opening and the first sacrificial layer; forming a second sacrificial layer on the third conductive layer; The sacrificial layer and the third conductive layer are etched back to remove the third conductive layer located on the first sacrificial layer; Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs — (Please read the precautions on the back before filling in this ), 1T removes the first sacrificial layer and the second sacrificial layer; the first conductive layer, the conductive spacer spacer and the third conductive layer in the contact window become the lower electrode plate of the capacitor; the capacitor Forming a dielectric layer on the lower electrode plate; and forming an upper electrode plate of the capacitor on the dielectric layer. 2. As stated in item 1 of the patent application scope, the dynamic random access memory private paper standard adopts the Chinese National Standard (CNS) A4 specification (210X297 mm) A8 B8 __ C8 'Applicable Patent Park' 'The manufacturing method of the grid capacitor, wherein the above-mentioned insulating layer is an oxide. 2. 2. The dynamic random access memory as described in item 2 of the scope of the patent application <The manufacturing method of the capacitor of the memory grid, wherein the first-sacrifice The second and second sacrificial layer is PETEOS. 4. The manufacturing method of dynamic random access memory "Memory Cell Capacitor" as described in item 3 of the patent scope, wherein the above etching termination is widely vaporized. 5 · Rushen 4. The method for manufacturing a memory cell capacitor of a dynamic random access memory as described in item 1, 2, 3 or 4 of the patent scope, wherein the first conductive layer, the second conductive layer and the third conductive layer are polycrystalline silicon .6. The method for manufacturing the capacitor of the yuege of the dynamic random access memory as described in item 5 of the scope of the patent application, wherein the dielectric layer is composed of oxide-nitride-oxide. Patent Fan Item 6 is a method of manufacturing a memory cell capacitor for dynamic random access memory, wherein the upper electrode plate of the capacitor is polycrystalline silicon. Ί -¾ ------ IT ------ ^ ^ (Please read the precautions on the back before filling out this page) Printed by the Employees ’Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs II-the paper standard bidder I, the country, the country, and the country. 2 H. 1 g. 7 9 2
TW85110544A 1996-08-29 1996-08-29 Manufacturing method of capacitor of memory cell in DRAM TW299482B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441418B1 (en) * 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction
US6551923B1 (en) 1999-11-01 2003-04-22 Advanced Micro Devices, Inc. Dual width contact for charge gain reduction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6441418B1 (en) * 1999-11-01 2002-08-27 Advanced Micro Devices, Inc. Spacer narrowed, dual width contact for charge gain reduction
US6551923B1 (en) 1999-11-01 2003-04-22 Advanced Micro Devices, Inc. Dual width contact for charge gain reduction

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