TW451426B - Forming method of bit line contact for DRAM of capacitor under bit line - Google Patents

Abstract

The present invention provides a forming method of bit line contact for DRAM of capacitor under bit line which includes the following steps: first, forming a first dielectric on a semiconductor substrate; etching the first dielectric to form the hole in the first dielectric; then, forming silicon material on the hole; forming the capacitor dielectric on the silicon material; then, sequentially forming the conductive layer, the second dielectric on the capacitor dielectric; removing part of the second dielectric, the conductive layer, the capacitor dielectric and the first dielectric to form the bit line contact hole in the second dielectric; selectively back etching part of the conductive layer under the second dielectric; forming the insulation film on the second dielectric and in the bit line contact hole; back filling the gap right under the second dielectric formed by back etching; removing the insulation film outside from right under the second dielectric; and finally, forming the first conductive plug in the bit line contact hole.

Description

42 6 V. Description of the invention (1) Field of the invention: The present invention relates to a method for forming a bit 1 ine contact of a semiconductor integrated circuit structure, especially a capacitor under a bit line. Method for forming bit line contact of dynamic random access memory (DRAM). Background of the Invention: With the progress of the semiconductor industry, the accumulation of dynamic random access memory (DRAM) has also increased rapidly. The DR AM memory cell (Ce 1 1) is composed of a transistor and a capacitor. One end of the capacitor is connected to the doped region of the transistor. The other end of the capacitor is connected to the reference potential. 'Electrical contact' digital information is stored in the capacitor, and the digital data in the capacitor is obtained by using an MOSFET, word line, and bit line (bi ΐ 1 ine) array. . Under the shrinking of the components to increase the accumulation and the surface area of the capacitor is reduced, the capacitor manufacturing method and structure so that the performance of the capacitor does not decrease is the capacitor: Ya) The direction of technical development efforts. Because to increase the DRAM accumulation level, the size of the DRAM must be reduced, and the reduction of the DRAM size will cause the correctness of the pattern transfer of the bit line contact during the photolithography process. this

Page 4 4 5 Μ 2 6 V. Description of the invention (2) Outer 'misalignment caused the capacitor's charge storage electrode (Storage Node) and bit line contact isolation or plate (P1) The isolation between the ate) and the bit line contacts is not easy to control. This is more obvious in the dynamic random access memory of the traditional Capacitor under bit line. Capacitor under bit line dynamic random access memory process technology can refer to "Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory" disclosed in US Patent No. 589373 4. (DRAM) using tungesten landing plug contacts " 〇 Now briefly explain the traditional method of forming bit line crown-type (crown shape) dynamic random access memory bit line contact as follows:

Referring to FIG. 1A, a shallow trench isolation region (shallow trench · i sο 1 ati on; ST I) 1 is sequentially formed in a semiconductor substrate 10 using a known technique 1 2. A plurality of transistor gate structures 1 4. Drain / source 16, first oxide layer 18, poly plug 20, second oxide layer 22. The transistor gate structure 14 is used as a word line, and the outer layer is an insulating material. Then, a part of the second oxide layer 22 is removed to form a contact hole, so that the subsequent capacitor can be in electrical contact with the electric crystal. After that, a silicon layer (hemispherical grains silicon; HSG-S i) 2 6 is formed in the second oxidation.

Kiss 42s V. Description of the invention (3) ~ On the material layer 22 'Next, the HSG-Si 26 on the second oxide layer 22 is removed by etch-back or chemical mechanical polishing technology. The above-mentioned Hemi-Spherical Grain (HSG) is used as the bottom electrode plate of the capacitor, which can effectively increase the surface area β of the storage electrode and then deposit a dielectric along the surface of the HSG-Si 26 structure. The thin film 30 is used as the dielectric layer of the capacitor, and a conductive layer 32 is used on the dielectric thin film 30 as the top electrode plate of the capacitor. A first photoresist layer 36 is then formed on the conductive 32 'and a portion of the first photoresist layer 36 is removed to define a plate contact pattering 37. The dielectric thin film 30 may be a nitride / oxide (N / ⑴'combination layer) composed of an oxide layer and a nitride layer, or a compound formed of an oxide layer, a nitride layer, or an oxide layer. / Nitride / oxide composite layer (0 / N / 0). '' Please refer to FIG. 1 β, and then use the first photoresist layer 36 as a mask to remove a part of the conductive layer 32 and the dielectric film 3 0 'In order to expose part of the second oxide, the upper surface of layer 2 2. After removing the first photoresist layer 36, a third oxide layer 38 and a second photoresist layer 40 are formed on the conductive layer 32 and the second The second photoresist layer 40 on the oxide layer 22 is removed to define the bit line contact circle. Please refer to FIG. 1C, and then use the second photoresist layer 40 as a military curtain to remove a portion of the third oxide layer. 38. The second oxide layer 22 is formed until a portion of the upper surface of the polycrystalline dream plug 20 is exposed to form a bit line contact hole 42.

Page 6 45 ---------- V. Description of the invention (4) Method, 1 Refer to Figure 1 D ', and then use sputtering or other related methods ^ to form a conductive plug 4 6 on the bit line The contact hole 42 serves as a conductive connection. ^^ The above-mentioned conductive plug "contains titanium: ^ layer" is a W / TiN / Ti composite layer composed of a titanium nitride layer and a tungsten (W) layer 46c. = * Wherein the first oxide layer 18 ', the second oxide layer 22, and the second emulsion layer 38 are used for insulation. In Figure 1A, "If the contact pattern of the plate defined by the first photoresist layer 36 is mis-al igned (see Figure 2A), the subsequent bit line formation will occur." The phenomenon of short circuit between the bit line and the capacitor plate is shown in Figure 2 β, where the short circuit between the bit line and the capacitor plate is shown by the round virtual box labeled A.) If the first photoresistor in Figure 1A The alignment of the plate contact pattern defined by layer 36 is correct, but in Figure 1B, 'the process window (C process window) used for the pattern transfer of bit line contact is too narrow, causing a second photoresist If the bit line contact pattern defined by layer 40 is misaligned (see Figure 2c), a short circuit between the bit 7C line and the capacitor plate will occur, and the subsequent deposition of the conductive plug 46 and the polycrystalline silicon plug will occur. The contact effect between 20 (poor landing on plug) becomes worse (see Figure 2D, in which the bit line and the capacitor plate are short-circuited as shown by the round virtual box labeled " B, and the conductive plug The phenomenon that the contact effect between 46 and the polycrystalline silicon plug 20 is deteriorated is shown by a circled box with the symbol " c μ.) 0

Page 7 451 42 s V. Description of the invention (5) Therefore, how to avoid the problems generated by the above Figures 2A to 2D is very important. Purpose and summary of the invention: The purpose of the present invention is to increase the size of the bit line contact window of a dynamic random access memory with a capacitor located below the bit line, so as to solve the pattern transfer due to incorrect bit line contact. , Resulting in a short circuit between the bit line contact and the top electrode of the capacitor. According to an embodiment of the present invention, a method for forming a bit line contact of a dynamic random access memory having a capacitor located under a bit line includes the following steps: (1) forming a first dielectric layer on a semiconductor substrate. (2) Etching the first dielectric layer to form holes in the first dielectric layer. (3) The silicon material is formed on the surface of the hole. (4) A capacitor dielectric layer is formed on the surface of the silicon material. (5) A conductive layer is formed to cover the capacitive dielectric layer. (6) A cover layer is formed on the surface of the conductive layer. (7) A first photoresist layer is formed on the surface of the mask layer. (8) The first photoresist layer in the etched part is used to expose the upper surface of the mask layer to define the electrode contact pattern. (9) The first photoresist layer is used as a mask, and a part of the mask layer, the conductive layer, and the capacitor dielectric layer are removed.

A photoresistive layer. (On the surface, and the gap. (14) In addition to the second optical layer and the middle in the contact diagram of the median line board. (The selective second dielectric is conductive to the size of the second and second photoresistors on the bit screen. Except the fifth, the description of the invention (6) (10) Remove the surface of the cover under the first layer of a dielectric layer directly on the wide surface directly below the contact layer. The contact pattern is large and extremely square. (15) Profit The layer and capacitor dielectric are in the holes of the second dielectric layer. (11) 12) Form the backfill to the part (13) to remove the first contact. The pattern needs to be a resist layer as a dielectric layer to cover the dielectric layer. 16) The first ground-etched etch back electric layer is formed on the layer and the photoresist layer is formed, so that a portion of the bit plug can be placed in line with the wire contact, and the portion is located in the mask layer and the etched portion left by The second dielectric defines the bit line electrode contact pattern directly below the second dielectric wire contact hole bit line contact. Before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: (1) Forming a plurality of transistors on a semiconductor substrate. (2) forming a third dielectric layer on the plurality of transistors β (3) forming a second conductive plug in the third dielectric layer, wherein the above-mentioned hole corresponds to the two conductive plugs. The silicon material includes hemispherical grain silicon, and the first conductive plug includes a polycrystalline silicon plug. In addition, the material of the cover layer includes nitride and has a thickness of about 500 to 1,000 angstroms. It can be used by Low Pressure Chemical Vapor Deposition (LPCVD) or atmospheric pressure chemical vapor deposition. form. In addition, the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer include an oxide. The third dielectric layer can be used

Page 9 dSt 42 6 Description of the invention (7) Chemical vapor deposition (Low Pressure Chemical Vapor DepositiOn; LPCVD) is formed to a thickness of about 1500 to 300 Angstroms. In addition, the method for selectively etching back a part of the conductive layer may be a wet etching method of (Ammonia peroxide mixture), which is an aqueous solution containing ammonia and hydrogen peroxide. The method for removing the second dielectric layer, the capacitor dielectric layer, and the first dielectric layer described above includes a method of reactive ion etch (RIE) using a reverse engraving method. According to another embodiment of the present invention, the capacitor is only formed when the bit lines of the DRAM below the _ line are in contact with each other to form a square two-bit array. Steps include: (1) the first dielectric material On the surface of the hole "The second dielectric layer, conductive contact. The electrical layer of the hole in the second dielectric layer is returned to the second dielectric to form the first dielectric layer on a semiconductor substrate. 4 J 玄 l | layer to form holes in the first dielectric layer. (3) Do y% Cheng Shixi on the surface. (4) forming a capacitive dielectric layer on the silicon chair (5) forming a conductive layer to cover the capacitive dielectric layer. (, Layer on the surface of the conductive layer. (7) Remove part of the second shape; layer, capacitor dielectric layer, and first dielectric layer to shape the dielectric

In the second dielectric layer. (8) Selectively etch back the conductive layer under the wide electrical layer. (9) Form the upper surface of the insulating thin layer and the bit line contact holes, and return to the space immediately below the second dielectric layer left by the etched part 3 of the opening. r

W 〇) Insulating film other than directly under the P layer. (Formed a 2

Page 10 45? ^ 6

V. Description of the invention (8) The electric plug is in the bit line contact hole, which means that the formation of the first dielectric layer on the semiconductor substrate includes the following steps: forming a plurality of two, and more. (3) forming a third dielectric layer in a plurality of transistors: body = forming a first conductive plug in the third dielectric layer, which is: two conductive plugs. 4 対 The first silicon material includes hemispherical grain silicon, and the first conductor includes polycrystalline silicon plug β, and the material of the insulating film includes nitride or oxygen, and the thickness is about 50 to 1000 Angstroms. It can be formed by low pressure chemical vapor deposition. In addition, the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer include an oxide. The third dielectric layer can be formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method, and has a thickness of about 15 to 300 angstroms. In addition, the method for selectively etching back a part of the conductive layer may be an APM (Ammonia peroxide mixture) wet etching method. The method for removing a part of the insulating film includes using a wet etching method or a dry etching method, and the solution used in the wet etching method includes a hydrofluoric acid solution or a phosphoric acid solution. Detailed description of the invention:

Page 11 45 / ^ 6 —-----— — ________________ V. Description of the invention (9) The purpose of the present invention is to increase the size of the bit line contact window of a dynamic random access memory with a capacitor located below the bit line. In order to solve the pattern transfer caused by inaccurate bit line contact, a short circuit occurs between the bit line contact and the top electrode of the capacitor. The present invention provides a method for forming bit line contact of a dynamic random access memory with a capacitor located below the bit line. The present invention is described in detail below with reference to a preferred embodiment: Please refer to FIG. 3A. First, a semiconductor is provided. Substrate 60, wherein the semiconductor substrate 60 can be a <100> or <111> crystal-oriented single crystal silicon or other types of semiconductor materials, such as gallium arsenide (GaAs) 'germanium (Ge) or located on an insulating substrate. Stone on insulator (SOI) and so on. Then use known techniques to form isolation areas such as shallow trench isolation areas.

(shallow trench isolation; STI) 62 in the semiconductor substrate 60 to produce an insulating effect. Then, a plurality of transistor gate structures 64 and drain / source electrodes 66 are sequentially formed on the semiconductor substrate 60. The transistor gate structure 64 is used as a word line and its outer layer is insulated. Material. The gate structure here may include an oxide layer, a polycrystalline wheat layer, Menghua Hetang, a nitrided protective layer, and the like. However, the above-mentioned electrode and source electrode 6-6 are formed by ion implantation ~ because the above-mentioned process is made by a technique known in the past and is not the focus of the present invention, it will not be described in detail.

4S ^ 26 ___ on page 12 5. Description of the invention (10) Then, a first dielectric layer for insulation is formed on the semiconductor substrate 60, the shallow trench isolation region 62, the gate structure 64, and the non-source / source 66. Electrical layer 6 8 »After that, a first conductive plug of self-aligned contact (SAC) is formed in the first dielectric layer 6 8 by using etching and deposition technology, wherein the first conductive plug 7 0 It can be a polycrystalline stone plug (ρο 1 yp 1 ug). In this preferred embodiment, a chemical vapor deposition method (Chemical Vapor Deposition; CVD) can be used to deposit the polycrystalline stone and backfill it into the contact hole. Re-etching or grinding is then used to form the above-mentioned polycrystalline silicon plug. In a preferred embodiment, the 'polycrystalline silicon of the present invention is an in-situ doped polysilicon or a doped polysilicon. Doped polysilicon 'and the first dielectric layer 68 is an oxide or silicon dioxide formed of TEOS. —

Then refer to FIG. 3B ′ to form a second dielectric layer M for insulation on the upper surfaces of the first dielectric layer 68 and the first conductive plug 70. After that, a dielectric layer between the bottom electrode plate, the top electrode plate and the two electrode plates of the capacitor is fabricated. Here's a description of the production of a crown type capacitor as an example. A first photoresist layer 74 is first formed on the second dielectric layer 72, and a portion of the first photoresist layer 74 is removed to define a contact window pattern 75. Then referring to FIG. 3c, using the first photoresist layer 74 as a mask, a part of the second dielectric layer 72 is removed to form a contact hole in the second dielectric layer 72, so that subsequent electrical Office can make electrical contact with the transistor. After the first photoresist layer 74 is removed, a silicon layer (hemispherieal guins silU (Dn; HSG-Sm)) 76 on the second dielectric layer 72 is filled in the contact hole for

4514 ^ β 5. Description of the invention (11) ~~~ 一 --η is used as the bottom electrode plate of the capacitor. Next, a cash back or chemical mechanical grinding technique is used to remove 0-3176 on the second dielectric layer 72. -In a preferred embodiment, 'selecting a hemispherical stone grain can effectively increase the surface area of the storage electrode. The silicon with hemispherical silicon grains is formed by first depositing a silicon thin film, and then forming a silicon seed (nuclei) on the shixi thin film. For example, a silicon-containing gas such as Si Xun Rong S i Formation, which causes the process temperature to be between about 500 ° C to 60 CTC, and the pressure to be between about 103 to 10 _Tor 'followed by a thermal tempering process under a high vacuum environment To form hemispherical stone eve grains. The process temperature is about 5 0 (fc to 60 1) ° C, and the pressure is about 1 E (-7) to 1 E (-9) Torr. As shown in FIG. 3D, the next step is to deposit a dielectric thin film 80 on the surface of the HSG-Si 76 structure as the dielectric layer of the capacitor. Generally, the dielectric layer 80 can be nitride / oxide Compound (N / 0), oxide / nitride / oxide (0 / N / 0) composite film or film using high dielectric such as Ta 20 5,

TiO 舁. A conductive layer 82 is deposited on the above-mentioned dielectric film 80 to cover the dielectric film 80 as the top electrode plate of the capacitor. In this preferred embodiment, the method of depositing the 'conductive layer 82 can be low voltage. (Low Pressure Chemical Vapor Deposition; LPCVD), &quot; y, and the conductive layer 82 can use doped polysilicon, in-situ doped polysilicon )form. A mask layer 84 is then deposited along the surface of the conductive layer 82 as a hard mask for subsequent excavation of the contact window.

45u2 on page 14 5. Explanation of the invention (12) Please refer to FIG. 3E. After the production of the electric valley is completed, a second photoresist layer 86 is then formed on the mask layer 84. Then the second photoresist layer 86 is removed. To define a plate contact pattern (Plate contact pattering) In this preferred embodiment, the plate contact pattern is approximately aligned with the first conductive plug 70. Then, using the second photoresist layer 86 as a mask, a part of the mask layer 84, the conductive layer 82, and the dielectric sheet 80 are removed to expose a portion of the upper surface of the second dielectric layer 72. Referring to FIG. 3F, after the second photoresist layer 86 is removed, the conductive layer 82 partially underneath the mask layer 84 is selectively returned to increase the distance between the top electrodes of the two capacitors, so that the subsequent Deposition bit lines do not cause a short circuit with the conductive layer 8 2 in this preferred embodiment. In this preferred embodiment, the method of selectively returning part of the conductive layer 8 2 may be the wet #etch method of apm (Ammonia peroxide mixture). 'Where APM is an aqueous solution containing ammonia and hydrogen peroxide.

Please refer to FIG. 3G ′, and then deposit a third dielectric layer 88 of sufficient thickness on the mask layer 84 and the second dielectric layer 72, and backfill the mask left by the part of the conductive layer 82 etched back. The gap immediately below the curtain layer 84 is used as a guardring to isolate the conductive layer 82 from contact with subsequent bit lines. In this preferred embodiment, the method of depositing the third dielectric layer 88 can be Low pressure chemical vapor deposition (LPCVD), and its thickness is about 1500 to 300 Angstroms. Then, a third photoresist layer 90 is formed on the third dielectric layer 88, and then a portion of the third photoresist layer 90 is removed to define a bit line contact pattern 91. Here, the size of the bit line contact pattern 91 can be larger than the distance between two crown-type capacitors, and

Page 15 4 ~ 5. Description of the invention (13) The distance between the crown type capacitors should be just below the bit line contact pattern 9 1. In a preferred embodiment, the material selected for the mask layer 84 is different from the material selected for the second dielectric layer 72 and the third dielectric layer 88. The mask layer 84 includes Nitride, and the third dielectric layer 88 includes an oxide or silicon dioxide formed with TEOS. In addition, the deposition method of the mask layer 84 may be a low pressure chemical vapor deposition method (LPCVD) or an atmospheric pressure chemical vapor deposition method, and the thickness of the mask layer 84 is about 500 to 100 Angstroms. Then perform self-aligned (sel f-al igned) contact window etching, see Figure 3H. Using the third photoresist layer 90 as a mask and the mask layer 84 as an etch stop layer, a portion of the third dielectric layer 88 and the second dielectric layer 7'2 are removed until a portion of the first conductivity is exposed The upper surface of the plug 70 is formed so as to form an MT-type bit line contact hole 9 2. In this preferred embodiment, the self-aligning contact window engraving method includes a reactive ion etching (reactive ion e tch, R I E) dry etching method. Then refer to FIG. 3I, and then use sputtering or other related known methods to form a second conductive plug 96 in the bit line contact hole 92 as a conductive connection. The second conductive plug 96 includes a titanium (Ti) layer 96a, a titanium nitride (1 ^ 10 layer 961), and a tungsten (10 layer 96 (; a ¥ / 1 ^ "1 ^ composite layer. Today In another preferred embodiment, the present invention is described in detail as follows: Please refer to FIG. 4A to FIG. 4B ′ in order on a semiconductor substrate 100 to form a shallow trench isolation.

Page 16 6

V. Description of the invention (14) Area 1 0 2, a plurality of transistor gate structures 1 04, a drain / source 1 106, a first dielectric layer 108, and a first conductive plug n in self-aligned contact 〇, the second dielectric layer 112, the first photoresist layer 114, and then remove a part of the first photoresist layer 4 to define the contact window pattern 115. Then referring to FIG. 4c, the first photoresist layer 114 is used as a mask to remove a portion of the second dielectric layer 112 to form a contact hole in the second dielectric layer 112, and then the first photoresist is removed. Layers 1 and 4 and a silicon layer 116 with hemispherical grains are formed on the second dielectric layer π 2 and filled into the contact holes. Next, etch back or chemical mechanical polishing is used to remove 1156-3; 1116 on the second dielectric layer 112. Since Figure 4 and Figure 4 (: the process is the same as that described in Figure 38 and Figure 8), the details will not be repeated. The first dielectric layer 108 described above contains an oxide or a SiO 2 formed of TEO S. As shown in Figure 4D, the next step is to deposit a dielectric film 120 as a dielectric layer of the capacitor along the surface of the HSG-Si 11 6 structure. Generally speaking, the dielectric thin film 120 can be a nitride / Oxide (N / 0), oxide / nitride / oxide (0 / N / 0) composite films or films using high dielectrics such as TaW 5, TiO, etc. Then a conductive layer 12 2 is deposited on the above Above the dielectric film 120 is used as the top electrode plate of the capacitor. In this preferred embodiment, the method for depositing the conductive layer 12 2 may be a Low Pressure Chemical Vapor Deposition (LPCVD) method. The conductive layer 122 can be formed using doped polysilicon and in-situ doped polysilicon. A third dielectric layer 124 and a second light are sequentially formed on the conductive layer 122.

45m2s on page 17 5. Description of the invention (15) ~~ &quot; ----- Resistive layer 126, and then remove the second photoresistive layer 12 6 of the planting side to define the bit line contacting one by one. The size of the bit line contact pattern needs to be smaller than the size of the first pin 110 of the self-aligned contact, and the bit line contact pattern needs to be located directly above the electrical test 110. Then, using the second photoresist layer 1 2 6 as a mask, a part of the third dielectric layer 124, the conductive layer 122, the dielectric film 1 2 0, and the first dielectric layer 1 2 are removed to expose part of the first dielectric layer 124. An upper surface of a conductive plug 110. Please refer to FIG. 4E 'After removing the second photoresist layer 丨 26, the conductive layer 122 located under the second dielectric layer 124 is selectively etched back, so as to enlarge the space between the two, j capacitor top electrodes. Distance, so that the subsequent deposition bit line does not cause a short circuit with the conductive layer 122. In this preferred embodiment, the method of selectively returning silver to the conductive layer 12 may be a wet etching method of ApM. . Please refer to FIG. 4F, and then deposit a thin insulating film. A film 130 is formed on the upper surface of the third dielectric layer 12 and the first conductive plug 110, and is backfilled to the above part of the conductive layer. The gap left immediately below the third dielectric layer 124. In this preferred embodiment, the 'insulating film 1.30 contains a nitride or an oxide and has a thickness of about 500 to 100 angstroms', and its deposition method may be a low-pressure chemical vapor deposition method). In addition, the second dielectric layer 112 and the third dielectric layer 124 include oxides or silicon dioxide 'formed with TE 0 S. The thicknesses are about 500 to 2 50 0 0 Angstroms, respectively.] 1 5 0 0 To 300 angstroms, and the deposition method may be a low pressure chemical vapor deposition method. Please refer to FIG. 4G ′ and then remove the third dielectric layer 12 4 and the first dielectric layer 12 4.

Page 1845l42e_ V. Description of the invention (16) '&quot;' ~~~~ '---- a conductive tether 1 1 0 part of the insulating film 1 3 0, up to the three dielectric layers 1 24 and On the upper surface of the first conductive plug, "the first formed bit line contact hole is exposed." Recycling or other related methods are used to form a second conductive plug 1440 connected to the bit line contact hole. The above-mentioned second conductive plug 14o includes a Uo, W / Ti N / T i composite layer composed of titanium (which is a conductive titanium nitride (ΠN) layer 140b and a tungsten (W) layer 140c. It is preferred here In the embodiment, the removal of the insulation includes the use of a dry money engraving method or a wet silver engraving method. If the insulating thin film film 13 ′ is formed, the solution used in the wet etching method may be phosphoric acid; and 13 0 is nitrogen 1 3 0 is Oxide, the solution used in the wet etching method, film, and * 1 ^ 4 acid 0 — the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention; Equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be regarded as the protection scope of the present invention. The scope of patent protection of the present invention shall be determined by the scope of the attached patent application and its equivalent fields.

Page 19 6 42 Schematic illustrations Using the following description, the contents and advantages are more a 2 L column diagrams, which will give a clearer understanding of the love points of the present invention, in which: Figure 1A is a semiconductor # u _ Sequentially formed on the semiconductor substrate is called the Thunder Two Side®, showing the first crown-type capacitor and the layer used to define the figure as a semiconductor wafer according to the conventional technology on the electrode contact pattern: steps; remove the top of some capacitors A cross-sectional view of an electric cup, showing the steps of defining the first photoresist layer of it @ π sister, and then forming a second-line pattern of the body line of the oxide layer / second photoresist layer according to the conventional technology; The photoresist layer is a mask 9, which is a plan view showing a step according to the conventional technology. FIG. D is a step of contacting a hole in a semiconductor crystal. A conductive pin is formed on a bit. The definition of the plate connection diagram 'shows a picture—a kind of first light). The misalignment (mis-al igned photoresistance of the touch pattern! Cross section of the two ΓΛ conductor wafers shows Misalignment of contact pattern Schematic diagram of the short circuit between the bit line and the capacitor plate; 7C is a cross-sectional view of a semiconductor wafer, showing the figure-schematic diagram of misalignment of the bit% line contact pattern defined by the second light layer Figure 2]) is a cross-sectional view of a semiconductor wafer, showing that due to the misalignment of the bit line contact pattern defined by the second first resistive layer in Figure 2, the vertical lines and capacitor plates are short-circuited, and Allows subsequent deposition of conductive plugs

45j page 20

The 4S 6 diagram simply illustrates the intent of poor landing on plug from the polycrystalline chip; Figure 3A is a cross-sectional view of a semiconductor wafer. Steps of sequentially forming a transistor, a first dielectric layer, and a first conductive plug; FIG. 3B is a cross-sectional view of a semiconductor wafer, showing that a second dielectric is sequentially formed on a semiconductor substrate according to an embodiment of the present invention; An electric layer and a step of defining a first photoresist layer for a contact window pattern; FIG. 3C is a cross-sectional view of a semiconductor wafer showing a step of forming a bottom electrode of a crown-type capacitor on a semiconductor wafer according to an embodiment of the present invention The embodiment of FIG. 3 is an internal electrode, the embodiment of FIG. 3 is an electrical layer, and the embodiment of the top diagram is a top view of the embodiment of FIG. Steps of sequentially forming a dielectric layer and a top cover curtain layer of a crown-type capacitor on a substrate; E is a cross-sectional view of a semiconductor wafer showing a portion of the cover substrate removed from the semiconductor substrate according to the present invention Steps of the intermediate electrode of the crown type capacitor; F is a cross-sectional view of a semiconductor wafer, showing a step of selectively etching back a crown type capacitor electrode partially under the cover layer according to the present invention; G is a step of the semiconductor wafer A cross-sectional view showing a step of sequentially forming a third dielectric layer and forming a photoresist layer with a pattern of contact lines on a semiconductor wafer according to one of the present invention; Η is a cross-sectional view of a semiconductor wafer, showing one

Page 21 45 ~ Brief Description of the Drawings The steps of forming a bit line contact hole on a semiconductor substrate are described in the embodiment. FIG. 3I is a cross-sectional view of a semiconductor wafer, showing a step of forming a second conductive plug in a bit line contact hole as a conductive connection according to an embodiment of the present invention; FIG. 4A is a cross-sectional view of a semiconductor wafer, showing Steps of sequentially forming a transistor, a first dielectric layer, and a first conductive plug on a semiconductor substrate according to another embodiment of the present invention; FIG. 4B is a cross-sectional view of a semiconductor wafer, showing another aspect of the present invention. In the embodiment, a step of sequentially forming a second dielectric layer and a first photoresist layer for defining a contact window pattern on a semiconductor substrate; FIG. 4C is a cross-sectional view of a semiconductor wafer, showing another implementation according to the present invention Example of the step of forming the bottom electrode of a crown-type capacitor on a semiconductor wafer; FIG. 4D is a cross-sectional view of a semiconductor wafer, showing another embodiment of the present invention to sequentially form the dielectric layer of the crown-type capacitor on the semiconductor substrate, the top Steps for the electrode, the third dielectric layer, and the bit line to contact the holes; FIG. 4E is a cross-sectional view of a semiconductor wafer, showing another embodiment of the present invention, selectively The step of etching back the top electrode of the crown-type capacitor under the third dielectric layer; FIG. 4F is a cross-sectional view of a semiconductor wafer, showing an insulating film deposited on the third dielectric layer according to another embodiment of the present invention And the step of back filling the gap immediately below the third dielectric layer left by the top electrode of the partial crown capacitor on the first conductive plug; and FIG. 4G is a cross-sectional view of a semiconductor wafer, showing According to another aspect of the present invention

4SW (.'__ on page 22) The diagram briefly illustrates an embodiment in which a part of the insulating film is removed and a second conductive plug is formed in the bit line contact hole as a conductive connection step. Part of the drawing: Semiconductor substrate 10, 60, 100; Shallow trench isolation areas 12, 62, 102; Gate structure 1 4, 6 4, 10 4; and Pole / source 16, 66, 106; First oxide layer 1 8; First Dielectric layers 68, 108; complex crystals 20, first conductive plugs 70, 11 0; second oxide layers 2 2; second dielectric layers 72, 112; silicon layers with hemispherical grains 2 6, 7 6, 1 1 6; Dielectric films 30, 80, 120; conductive layers 32, 82, 122; first photoresist layers 36, 74, 114; contact window patterns 75, 115; electrode contact patterns 3 7 ; Third oxide layer 3 8; mask 84;

The β-S- pattern on page 23 briefly explains the second photoresist layer 40, 86, 126; the third dielectric layer 88, 124; the third photoresist layer 90; the bit line contact pattern 9 1; the bit line Contact holes 4 2, 9 2; Insulating film 130; Conductive plug 46; Second conductive plug 96, 140; Layers 46a, 96a, 140a; Titanium nitride layers 46b, 96b, 140b; Layers 46c, 96c, 140c.

Page 24

Claims (1)

45 ϋ- VI. Scope of Patent Application 1. A method for forming bit line contact of a dynamic random access memory having a capacitor under a bit line, the method includes at least the following steps: forming a first dielectric layer on a semiconductor substrate Etch the first dielectric layer to form a hole in the first dielectric layer; form a silicon material on the surface of the hole; form a capacitor dielectric layer on the surface of the silicon material; form a conductive layer to cover the A capacitor dielectric layer; forming a mask layer on the surface of the conductive layer; forming a first photoresist layer on the surface of the mask layer; the first photoresist layer in an etched portion is used to expose the mask layer Surface to define the contact pattern of the plate; using the first photoresist layer as a mask, removing a part of the mask layer, the conductive layer and the capacitor dielectric layer; removing the first photoresist layer; selectively returning An etched portion is located on the conductive layer below the mask layer; a second dielectric layer is formed on the surface of the mask layer and the first dielectric layer, and backfilled to a portion of the conductive layer left by etch back The gap just below the cover layer Forming a second photoresist layer on the surface of the second dielectric layer; removing a part of the second photoresist layer to define a bit line contact pattern, wherein the size of the bit line contact pattern can be larger than the plate contact pattern Is large, and the contact pattern of the electrode plate needs to be located directly below the bit line contact pattern; using the second photoresist layer as a mask, removing part of the second dielectric layer, the capacitor dielectric layer, and the A first dielectric layer to form a bit line contact hole Page 25 _ "Guangdong" VI. The scope of patent application is in the second dielectric layer; and a first conductive plug is formed in the bit line contact hole. 2. The method of claim 1, wherein before forming the first dielectric layer on the semiconductor substrate, the method further includes the following steps: forming a plurality of transistors on the semiconductor substrate; forming a third dielectric A layer is formed on the plurality of transistors; and a second conductive plug is formed in the third dielectric layer, wherein the hole corresponds to the second conductive plug. ..V 3. The method according to item 1 of the patent application range, wherein the above-mentioned silicon material includes hemispherical grain silicon. 4. The method according to item 1 of the scope of patent application, wherein the materials of the first dielectric layer and the second dielectric layer described above include oxides. 5. The method according to item 1 of the patent application range, wherein the first conductive plug described above comprises a polycrystalline silicon plug. .. person, 6. The method according to item 1 of the scope of patent application, wherein the material of the cover layer includes nitride. 7. The method according to item 1 of the scope of patent application, wherein the thickness of the cover layer is about 500 to 100 angstroms. 6. Scope of patent application 8 · The method according to item 1 of the patent scope, wherein the mask layer is formed by using Low Pressure Chemical Vapor Deposition (LPCVD) or atmospheric pressure chemical vapor deposition. 9. The method according to item 1 of the scope of patent application, wherein the method for selectively etching back the conductive layer may be APM (Ammonia peroxide mixture) wet etching method. 10. The method of claim 1, wherein the method of removing a portion of the second dielectric layer, the capacitor dielectric layer, and the first dielectric layer includes using a dry etching method. 11. The method according to item 2 of the patent application, wherein the material of the third dielectric layer contains an oxide "1 2 · The method according to item 2 of the patent application, wherein the third dielectric layer uses a low-pressure chemical gas Phase deposition (Low Pressure Chemical Vapor Deposition; LPCVD). 3. The method according to item 2 of the scope of patent application, wherein the thickness of the third dielectric layer is about 1500 to 3000 Angstroms. 14- The method according to the scope of patent application, wherein the above-mentioned dry silver engraving method package IIMI page 27 ◊ ion reactive ion etch, RIE) 6 'patent application scope includes reactive ion etching method 1 5.-a kind of wire contact Forming a first cut, the forming silicon, forming an electrically conductive first removing portion, and a bit method of a dynamic random access memory in which the first capacitance is below a bit line, the method includes at least the following steps: a dielectric layer On a semiconductor substrate; a first dielectric layer to form a hole in the first dielectric layer; a material on the surface of the hole; a capacitive dielectric layer on the surface of the silicon material; an electrical layer to cover the capacitor A dielectric layer; two dielectric layers on the surface of the conductive layer; an electrical layer for the second dielectric layer, the conductive layer, and the capacitor dielectric layer to form a bit line contact hole in the second dielectric The second dielectric layer in the layer is selectively etched back to the conductive layer under the second dielectric layer to form a contact hole. The second dielectric layer is removing the first edge film on the upper surface of the second dielectric layer and the second dielectric layer. Bit line And to backfill the voids of the lower portion of the first conductive layer is etched back to the left; a second dielectric layer other than directly below the insulating film; and a conductive plug in the bit line contact holes in. 16. The method according to item 15 of the patent application scope, wherein before forming the first dielectric layer on the semiconductor substrate, the method further comprises the following steps: forming a plurality of transistors on the semiconductor substrate; Page 28 ~ _______ 6. Apply for a patent to form a third dielectric layer on the plurality of transistors; and form a second conductive plug in the third dielectric layer, wherein the hole corresponds to the Second conductive bolt. 1 7. The method according to item 15 of the scope of patent application, wherein the above-mentioned silicon material includes hemispherical grain silicon. 18. The method according to item 15 of the scope of patent application, wherein the materials of the first dielectric layer and the second dielectric layer include oxides. j 'V-' 19. The method according to item 15 of the patent application, wherein the above-mentioned first conductive plug comprises a polycrystalline silicon plug β 2 0. The method according to item 15 of the patent application, wherein the insulating film The material contains nitride or oxide. 2 1. The method according to item 15 of the scope of patent application, wherein the thickness of the above-mentioned insulating film is about 500 to 100 angstroms. 2 2. The method according to item 15 of the scope of patent application, wherein the above-mentioned insulating film is formed by using a Low Pressure Chemical Vapor a Deposition (LPCVD) method. 2 3. The method according to item 15 of the scope of patent application, wherein the selective etch-back described above Page 29 4 5 〖4 S f_ VI. Application for Patent Fanyuan Part of the method of the conductive layer can be APM (Ammonia peroxide mixture) wet recording method. 24. The method of claim 15 in the scope of patent application, wherein the method for removing a part of the insulating film includes using a wet etching method or a dry etching method. 25. The method according to item 16 of the patent application, wherein the third dielectric layer includes an oxide layer β 26. The method according to item 16 of the patent application park, wherein the third dielectric layer is a low-pressure chemical gas Phase deposition (Low Pressure Chemical Vapor Deposition; LPCVD). 2 7. The method according to item 16 of the scope of patent application, wherein the thickness of the third dielectric layer is about 150 to 300 angstroms. 28. The method of claim 24, wherein the solution used in the wet etching method comprises a hydrofluoric acid solution or a phosphoric acid solution. Page 30